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? 2014 - 2015 microchip technology inc. ds00001719d-page 1 product features ?arm ? cortex ? -m4 processor core - 32-bit arm v7-m instruction set architecture - hardware floating point unit (fpu) - single 4gbyte addressing space (von neu- mann model) - little-endian byte ordering - bit-banding feature included - nvic nested vectored interrupt controller - up to 240 individually-vectored interrupt sources supported - 8 levels of priority, indi vidually assignable by vector - chip-level interrupt aggregator supported, to expand number of interrupt sources or reduce number of vectors - system tick timer - complete arm-standard debug support - jtag-based dap port, comprised of swj-dp and ahb-ap debugger access functions - full dwt hardware functionality: 4 data watchpoints and execution monitoring - full fpb hardware breakpoint functionality: 6 execution breakpoints and 2 literal (data) breakpoints - comprehensive arm-standard trace sup- port - full dwt hardware trace functionality for watchpoint and performance monitoring - full itm hardware trace functionality for instrumented firmware support and profiling - full etm hardware trace functionality for instruction trace - full tpiu functionality for trace output communication ? 128k sram (code or data) - 96k optimized for code - 32k optimized for data ? lpc interface - supports lpc bus frequencies of 19mhz to 33mhz - lpc i/o cycles decoded - lpc memory cycles decoded - clock run support -serial irq - acpi sci interface - smi# output ? two spi memory interfaces - 3-pin full duplex serial communication interface - two private and two shared chip selects - dma support ? 8042 style host interface - mailbox registers interface - forty-three 8-bit scratch registers - two register mailbox command interface - two register smi source interface ? two acpi embedded controller interface - 1 or 4 byte data transfer capable ? acpi power management interface - sci event-generating functions ? embedded memory interface - host serial irq source - provides two windows to on-chip sram for host access ? two register mailbox command interface ? battery backed (vcc0/vbat) resources - power fail register - power-fail status register - battery backed 64 byte memory ? real time clock (rtc) - vcc0 (vbat) powered - 32khz crystal oscillator - 32khz clock output available under vcc1 power - time-of-day and calendar registers - programmable alarms - supports leap year and daylight savings time ? hibernation timers ? general purpose analog to digital converter - 10-bit conversion precision - 10-bit conversion per channel is completed in less than 12us - 5 adc channels - 10-bit conversion with 2.9mv resolution - 0 to 3.3 vdc conversion range - optional continuous sampling at a programmable rate - internal analog voltage reference (3.0v +/- 1%) ? watch dog timer ? four programmable 16-bit and two 32-bit timers - wake-capable auto-reloading timers ? four independent hardware driven ps/2 ports - fully functional on main and/or suspend power - ps/2 edge wake capable ? four programmable pulse-width modulator out- puts - independent clock rates - 16-bit duty cycle granularity - operational in both full on and standby modes MEC1322 keyboard and embedded controller for notebook pc
MEC1322 ds00001719d-page 2 ? 2014 - 2015 microchip technology inc. ? four ec-based smbus 2.0 host controllers - allows master or dual slave operation - controllers are fully operational on standby power - dma-driven i 2 c network layer hardware -i 2 c datalink compatibility mode - multi-master capable - supports clock stretching - programmable bus speeds - 400 khz fast-mode capable - 1 mbps fast-mode plus capable - hardware bus access "fairness" interface - smbus time-outs interface -5 ports - 2 port flexible multiplexing ? peci 3.0 interface ? keyboard matrix scan interface - 18 x 8 interrupt/wake capable multiplexed keyboard scan matrix - row predrive option ? four breathing/blinking led interfaces - programmable blink rates - piecewise linear breathing led output con- troller - operational in ec sleep states ? dual fan tachometer inputs ? rpm-based fan speed control algorithm - utilizes one tach input and one pwm output - 3% accurate from 500 rpm to 16k rpm - automatic tachometer feedback - aging fan or invalid drive detection - spin up routine - ramp rate control - rpm-based fan speed control algorithm ? fast gatea20 & fast cpu_reset ? rsmrst# functionality supporting system deep sleep - compatible with south bridge sus- clk/rsmrst# gating rules - replacement 32k distribution available when rsmrst# is asserted ? integrated power-on reset generator - vcc1_rst# open drain output - accepts external driven reset ? anti-glitch protection on power-on ? all blocks support low power sleep modes ? general purpose input/output pins - low power - high configurability ? two pin debug port with standard 16c550a regis- ter interface - accessible from both host and ec ? bc-link interconnection bus - one high speed bus master controller ? package options - 128-pin vtqfp - 132-pin dqfn - 144-pin wfbga description the MEC1322 incorporates a high-performance 32-bit arm ? cortex ? -m4 embedded microcontroller with 128 kilobytes of sram and 32 ki lobytes of boot rom. it communicates with the system host using the intel ? low pin count (lpc) bus. the MEC1322 has two spi memory interfaces that allow the ec to read its code from external spi flash memory: private spi and/or shared spi. the shared spi interface allows for ec code to be stored in a shared spi chip along wit h the system bios. the pri- vate spi memory interface provides for a dedicated spi flash that is only accessible by the ec. the MEC1322 provides support for loading ec code from the private or shared spi flash device on a vcc1 power-on. before executing the ec code loaded from a spi flash device, the MEC1322 validates the ec code using a digital signature encoded according to pkcs #1. the signature uses rsa-2048 encryption and sha-256 hashing. this provides automated detection of invalid ec code that may be a result of malicious or accidental corruption. it occurs before each boot of the host processor, thereby en suring a hw based root of trust not easily thwarted via physical replacement attack. the MEC1322 is directly powered by two separate sus- pend supply planes (vbat and vcc1) and senses the runtime power plane (vcc) to provide ?instant on? and system power management functions. it also contains an integrated vcc1 reset interface and a system power management interface that supports low-power states and can drive state changes as a result of hard- ware wake events.
? 2014 - 2015 microchip technology inc. ds00001719d-page 3 MEC1322 to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our public ations to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
MEC1322 ds00001719d-page 4 ? 2014 - 2015 microchip technology inc. table of contents 1.0 pin configuration ......................................................................................................... .................................................................... 5 2.0 block overview ............................................................................................................ ................................................................. 45 3.0 power, clocks, and resets ................................................................................................. .......................................................... 48 4.0 vbat register bank ........................................................................................................ ............................................................. 72 5.0 lpc interface ............................................................................................................. ................................................................... 75 6.0 chip configuration ........................................................................................................ ................................................................ 99 7.0 arm m4f based embedded controller ......................................................................................... ............................................. 103 8.0 ram and rom ............................................................................................................... ............................................................. 112 9.0 embedded memory interface (emi) ........................................................................................... ................................................. 114 10.0 acpi embedded controller interface (acpi-eci) ............................................................................ ......................................... 128 11.0 8042 emulated keyboard controller ........................................................................................ ................................................. 145 12.0 mailbox interface ........................................................................................................ ............................................................... 162 13.0 acpi pm1 block interface ................................................................................................. ........................................................ 170 14.0 uart ..................................................................................................................... ................................................................... 178 15.0 ec interrupt aggregator .................................................................................................. .......................................................... 192 16.0 watchdog timer (wdt) ..................................................................................................... ....................................................... 218 17.0 basic timer .............................................................................................................. ................................................................. 222 18.0 hibernation timer ........................................................................................................ .............................................................. 228 19.0 rtc with date and dst adjustment ......................................................................................... ............................................... 231 20.0 gpio interface ........................................................................................................... ............................................................... 243 21.0 internal dma controller .................................................................................................. ........................................................... 258 22.0 smbus interface .......................................................................................................... .............................................................. 272 23.0 peci interface ........................................................................................................... ................................................................ 275 24.0 tach ..................................................................................................................... ................................................................... 278 25.0 pwm ...................................................................................................................... ................................................................... 285 26.0 rpm-pwm interface ........................................................................................................ ......................................................... 290 27.0 general purpose serial pe ripheral interface .............................................................................. .............................................. 308 28.0 blinking/breathing pwm ................................................................................................... ........................................................ 327 29.0 ps/2 interface ........................................................................................................... ................................................................ 343 30.0 keyboard scan interface .................................................................................................. ......................................................... 351 31.0 bc-link master ........................................................................................................... .............................................................. 358 32.0 trace fifo debug port (tfdp) ............................................................................................. ................................................... 364 33.0 analog to digital converter .............................................................................................. ......................................................... 368 34.0 vbat-powered ram ......................................................................................................... ....................................................... 375 35.0 ec subsystem registers ................................................................................................... ....................................................... 378 36.0 test mechanisms .......................................................................................................... ............................................................ 382 37.0 electrical specif ications ................................................................................................ ............................................................ 389 38.0 timing diagrams .......................................................................................................... ............................................................. 397 39.0 memory map ............................................................................................................... .............................................................. 423 appendix a: revision history .................................................................................................. .......................................................... 452 the microchip web site ........................................................................................................ ............................................................ 453 customer change notification service .......................................................................................... ................................................... 453 customer support .............................................................................................................. ............................................................... 453 product identification system ................................................................................................. ........................................................... 454
? 2014 - 2015 microchip technology inc. ds00001719d-page 5 MEC1322 1.0 pin configuration 1.1 description the pin configuration chapter includes a pin list , pin description , pin multiplexing and package outline . 1.2 terminology and symbols for pins/buffers note 1-1 see the ?pci local bus specificat ion,? revision 2.1, section 4.2.2. note 1-2 see the ?pci local bus specification,? revision 2.1, section 4.2.2 and 4.2.3. 1.3 pin list the pin list for the three package options is shown in table 1-1, table 1-2 and ta b l e 1 - 3 . term definition pin ref. number there is a unique reference number for each pin name. # the ?#? sign at the end of a signal name indicates an active-low signal n the lowercase ?n? preceding a signal name indicates an active-low signal pwr power i digital input is input with schmitt trigger i_an analog input o push-pull output od open drain output io bi-directional pin iod bi-directional pin with open drain output pio programmable as input, output, open drain output , bi-directional or bi-directional with open drain output. pci_i input. these pins meet the pci 3.3v ac and dc characteristics. ( note 1-1 ) pci_o output. these pins meet the pci 3.3v ac and dc characteristics. ( note 1-1 ) pci_od open drain output. these pins meet th e pci 3.3v ac and dc characteristics. ( note 1-1 ) pci_io input/output these pins meet the pci 3.3v ac and dc characteristics. ( note 1-1 ) pci_iclk clock input. these pins meet the pc i 3.3v ac and dc characteristics and timing. ( note 1-2 ) pci_pio programmable as input, output, open drain out put, bi-directional or bi-directional with open drain output. these pins meet the pci 3.3v ac and dc characteristics. ( note 1-1 ). io_peci peci input/output. these pins are at the peci v ref level. see chapter 37.0, "electrical spec- ifications" . note: the pin ref. numbers are the same as the pin numbers in the ?128 vtqfp number? column in table 1-1, "MEC1322 128 vtqfp pin configuration" .
MEC1322 ds00001719d-page 6 ? 2014 - 2015 microchip technology inc. table 1-1: MEC1322 128 vtqfp pin configuration note 1: the xtal2 pin can be used as a single ended clock input. see note 9 in section 1.6, "notes for tables in this chapter," on page 39 . 2: see note 10 in section 1.6, "notes for tables in this chapter," on page 39 for information about the spi pins. 3: the vcc1_rst#/gpio131 pin cannot be used as a gp io pin. the input path to the vcc1_rst# logic is always active and will cause a reset if this pin is set low in gpio mode. 4: the gpio041 pin defaults to output low. this pin mu st be reprogrammed to the gpio function upon power- up. 128 vtqfp nu m b e r pin nam e pin re f. nu m b e r 128 vtqfp nu m b e r pin nam e 128 vtqfp nu m b e r pin nam e 1 gpio036 44 44 adc0/gpio056 87 gpio165/txd/shd_cs1# 2 gpio153/pvt_sclk 45 45 avss 88 gpio023/i2c1_dat0 3 gpio122/shd_sclk 46 46 lad0/gpio112 89 gpio022/i2c1_clk0 4 gpio011/kso16 47 47 vss 90 gpio021/i2c2_dat0 5 kso13/gpio006 48 48 lad1/gpio114 91 gpio020/i2c2_clk0 6 kso12/gpio005 49 49 jtag_rst# 92 gpio105/tach1 7 kso11/gpio107 50 50 lad2/gpio113 93 gpio145 8 kso10/gpio004 51 51 lad3/gpio111 94 gpio164/pvt_miso 9 kso09/gpio106 52 52 lframe#/gpio120 95 gpio124/shd_miso 10 kso08/gpio003 53 53 lreset#/gpio116 96 gpio146/pvt_cs0# 11 vss 54 54 pci_clk/gpio117 97 gpio150/shd_cs0# 12 kso07/ gpio002 55 55 clkrun#/ gpio014 98 gpio 157/bc_clk 13 kso06/gpio001 56 56 vss 99 gpio160/bc_dat 14 vcc1 57 57 ser_irq/gpio115 100 gpio161/bc_int# 15 cap 58 58 vcc1 101 gpio140/tach2/tach2pwm_in 16 kso05/gpio104/tfdp_clk 59 59 gpio041 102 gpio045/a20m/pvt_cs1# 17 kso04/gpio103/tfdp_data/xnor 60 60 nreset_out/gpio121 103 gpio053/ps2_clk3 18 kso03/gpio102/jtag_tdo 61 61 ps2_clk1/gpio050 104 vss 19 kso02/gpio101/jtag_tdi 62 62 ps2_dat1/gpio065 105 gpio152/ps2_dat3 20 kso01/gpio100/jtag_tms 63 63 gpio035 106 vcc1 21 kso00/gpio000/jtag_tck 64 64 gpio027 107 gpio030 22 ksi7/gpio043 65 65 gpio033 108 gpio012/kso17 23 ksi6/gpio042 66 66 ps2_clk0/gpio046 109 i2c0_dat1/gpio017 24 ksi5/gpio040 67 67 ps2_dat0/gpio047 110 i2c0_clk1/gpio134 25 ksi4/gpio142/traceclk 68 68 vbat 111 i2c0_dat0/gpio016 26 ksi3/gpio032/tracedata0 69 69 xtal2 112 i2c0_clk0/gpio015 27 ksi2/gpio144/tracedata1 70 70 vss_vbat 113 led0/gpio154 28 ksi1/gpio126/tracedata2 71 71 xtal1 114 led1/gpio155 29 ksi0/gpio125/tracedata3 72 72 vcc_pwrgd/gpio063 115 led2/gpio156 30 gpio031 73 73 gpio110 116 gpio163 31 gpio127/peci_rdy 74 74 gpio130 117 vss 32 ps2_dat2/gpio052 75 75 32khz_out/gpio013 118 gpio136/pwm1 33 gpio147 76 76 nec_sci/gpio026 119 vcc1 34 gpio151 77 77 vcc1_rst#/gpio131 120 gpio133/pwm0 35 ps2_clk2/gpio051 78 78 gpio141/pwm3/led3 121 gpio034/pwm2/tach2pwm_out 36 vss 79 79 vref_peci 122 gpio135/kbrst 37 vcc1 80 80 gpio132/peci_dat 123 gpio044/nsmi 38 adc4/gpio062 81 81 gpio007/kso14 124 gpio066 39 adc3/gpio061 82 82 vss 125 gpio025/i2c3_dat0 40 avcc 83 83 gpio010/kso15 126 gpio024/i2c3_clk0 41 gpio206 84 84 vcc1 127 gpio054/pvt_mosi 42 adc2/gpio060 85 85 gpio143/rsmrst# 128 gpio064/shd_mosi 43 adc1/gpio057 86 86 gpio162/rxd
? 2014 - 2015 microchip technology inc. ds00001719d-page 7 MEC1322 table 1-2: MEC1322 132 dq fn pin configuration note: table 1-2, "MEC1322 132 dqfn pin configuration" shows the mapping between pin ref. number and 132 dqfn number for the 132 dqfn package. pin re f. nu m b e r 132 dqfn nu m b e r pin nam e pin re f. nu m b e r 132 dqfn number pin name 2 b1 gpio153/pvt_sclk 32 b18 ps2_dat2/gpio052 3 a1 gpio122/shd_sclk 33 a17 gpio147 4 b2 gpio011/kso16 34 b19 gpio151 5 a2 kso13/gpio006 132 a18 gpio211 6 b3 kso12/gpio005 35 b20 ps2_clk2/gpio051 7 a3 kso11/gpio107 37 a19 vcc1 8 b4 kso10/gpio004 38 b21 adc4/gpio062 10 a4 kso08/gpio003 39 a20 adc3/gpio061 9 b5 kso09/gpio106 40 b22 avcc 11 a5 vss 41 a21 gpio206 12 b6 kso07/gpio002 42 b23 adc2/gpio060 13 a6 kso06/gpio001 43 a22 adc1/gpio057 14 b7 vcc1 44 b24 adc0/gpio056 15 a7 ca p 45 a23 avss 129 b8 gpio067 46 b25 lad0/gpio112 130 a8 gpio055 133 a24 gpio200 131 b9 gpio210 48 b26 lad1/gpio114 16 a9 kso05/gpio104/tfdp_clk 49 a25 jta g_rst# 17 b10 kso04/gpio103/tfdp_data/xnor 50 b27 lad2/gpio113 18 a10 kso03/gpio102/jtag_tdo 51 a26 lad3/gpio111 19 b11 kso02/gpio101/jtag_tdi 52 b28 lframe#/gpio120 20 a11 kso01/gpio100/jtag_tms 53 a27 lreset#/gpio116 21 b12 kso00/gpio000/jtag_tck 54 b29 pci_clk/gpio117 22 a12 ksi7/gpio043 55 a28 clkrun#/gpio014 24 b13 ksi5/gpio040 134 b30 gpio123 23 a13 ksi6/gpio042 57 a29 ser_irq/gpio115 25 b14 ksi4/gpio142/traceclk 58 b31 vcc1 26 a14 ksi3/gpio032/tracedata0 59 a30 gpio041 27 b15 ksi2/gpio144/tracedata1 60 b32 n reset_ out/ gpio1 2 1 28 a15 ksi1/gpio126/tracedata2 61 a31 ps2_clk1/gpio050 29 b16 ksi0/gpio125/tracedata3 62 b33 ps2_dat1/gpio065 30 a16 gpio031 63 a32 gpio035 31 b17 gpio127/peci_rdy 64 b34 gpio027
MEC1322 ds00001719d-page 8 ? 2014 - 2015 microchip technology inc. note: table 1-3, "MEC1322 144 wfbga pin configuration" shows the mapping between pin ref. number and 144 wfbga ball number. pin re f. nu m b e r 132 dqfn nu m b e r pin nam e pin re f. nu m b e r 132 dqfn nu m b e r pin nam e 65 b35 gpio033 97 b52 gpio150/shd_cs0# 66 a33 ps2_clk0/gpio046 98 a49 gpio157/bc_clk 67 b36 ps2_dat0/gpio047 99 b53 gpio160/bc_da t 68 a34 vbat 100 a50 gpio161/bc_int# 69 b37 xtal2 101 b54 gpio140/ta ch2/ta ch2pwm_in 70 a35 vss_vbat 102 a51 gpio045/a20m/pvt_cs1# 71 b38 xtal1 103 b55 gpio053/ps2_clk3 72 a36 v cc_pwrgd/gpio063 139 a52 gpio203 73 b39 gpio110 105 b56 gpio152/ps2_dat3 74 a37 gpio130 106 a53 v cc1 75 b40 32khz_out/gpio013 107 b57 gpio030 76 a38 nec_sci/gpio026 108 a54 gpio012/kso17 77 b41 vcc1_rst#/gpio131 109 b58 i2c0_dat1/gpio017 78 a39 gpio141/pwm3/led3 110 a55 i2c0_clk1/gpio134 79 b42 v ref_ peci 111 b59 i2c0_dat0/gpio016 80 a40 gpio132/peci_dat 112 a56 i2c0_clk0/gpio015 81 b43 gpio007/kso14 113 b60 led0/gpio154 136 a41 gpio202 114 a57 led1/gpio155 83 b44 gpio010/kso15 115 b61 led2/gpio156 84 a42 v cc1 116 a58 gpio163 85 b45 gpio143/rsmrst# 141 b62 gpio204 86 a43 gpio162/rxd 118 a59 gpio136/pwm1 87 b46 gpio165/txd/shd_cs1# 119 b63 v cc1 88 a44 gpio023/i2c1_dat0 120 a60 gpio133/pwm0 89 b47 gpio022/i2c1_clk0 121 b64 gpio034/pwm2/tach2pwm_out 90 a45 gpio021/i2c2_dat0 122 a61 gpio135/kbrst 91 b48 gpio020/i2c2_clk0 123 b65 gpio044/nsmi 92 a46 gpio105/tach1 124 a62 gpio066 93 b49 gpio145 125 b66 gpio025/i2c3_dat0 94 a47 gpio164/pvt_miso 126 a63 gpio024/i2c3_clk0 95 b50 gpio124/shd_miso 127 b67 gpio054/pvt_mosi 96 a48 gpio146/pvt_cs0# 128 a64 gpio064/shd_mosi 137 b51 gpio201 1 b68 gpio036
? 2014 - 2015 microchip technology inc. ds00001719d-page 9 MEC1322 table 1-3: MEC1322 144 wfbga pin configuration pin re f. nu m b e r 144 wfbga nu m b e r pin nam e pin re f. nu m b e r 144 wfbga nu m b e r pin nam e 1 c3 gpio036 37 h5 v cc1 2 f5 gpio153/pv t_sclk 38 n5 a dc4/gpio062 3 f6 gpio122/shd_sclk 39 m5 a dc3/gpio061 4 a2 gpio011/kso16 40 l5 avcc 5 a1 kso13/gpio006 41 n6 gpio206 6 b1 kso12/gpio005 42 m6 adc2/gpio060 7 b2 kso11/gpio107 43 l6 adc1/gpio057 8 c2 kso10/gpio004 44 n7 adc0/gpio056 9 c1 kso09/gpio106 45 m7 avss 10 d2 kso08/gpio003 46 n8 lad0/gpio112 11 d1 vss 47 a5 vss 12 e2 kso07/gpio002 48 m8 lad1/gpio114 13 e1 kso06/gpio001 49 j3 jtag_rst# 14 g5 vcc1 50 l8 lad2/gpio113 15 f1 cap 51 l9 lad3/gpio111 16 g2 kso05/gpio104/tfdp_clk 52 n9 lframe#/gpio120 17 h3 kso04/gpio103/tfdp_data/xnor 53 n10 lreset#/gpio116 18 h1 kso03/gpio102/jtag_tdo 54 m9 pci_clk/gpio117 19 j1 kso02/gpio101/jtag_tdi 55 m10 clk run#/gpio014 20 h2 kso01/gpio100/jtag_tms 56 f3 vss 21 j2 kso00/gpio000/jtag_tck 57 l 1 0 ser_ irq/gpio11 5 22 k1 ksi7/gpio043 58 j5 vcc1 23 k3 ksi6/gpio042 59 n11 gpio041 24 k2 ksi5/gpio040 60 n12 nreset_out/gpio121 25 l1 ksi4/gpio142/traceclk 61 n13 ps2_clk1/gpio050 26 l2 ksi3/gpio032/tracedata0 62 l11 ps2_dat1/gpio065 27 l3 ksi2/gpio144/tracedata1 63 m12 gpio035 28 m2 ksi1/gpio126/tracedata2 64 m13 gpio027 29 m1 ksi0/gpio125/tracedata3 65 l12 gpio033 30 n2 gpio031 66 k11 ps2_clk0/gpio046 31 n1 gpio127/peci_rdy 67 j12 ps2_dat0/gpio047 32 m3 ps2_dat2/gpio052 68 k12 vbat 33 n3 gpio147 69 l13 xtal2 34 m4 gpio151 70 k13 vss_vbat 35 l4 ps2_clk2/gpio051 71 j13 xtal1 36 e3 v ss 72 j11 v cc_pwrgd/gpio063
MEC1322 ds00001719d-page 10 ? 2014 - 2015 microchip technology inc. note: the nc pin in the 144 wfbga package should be left unconnected on the board. pin re f. nu m b e r 144 wfbga number pin name pin re f. nu m b e r 144 wfbga nu m b e r pin nam e 73 h13 gpio110 109 b9 i2c0_dat1/gpio017 74 h11 gpio130 110 a9 i2c0_clk1/gpio134 75 h12 32khz_out/gpio013 111 a8 i2c0_dat0/gpio016 76 g13 nec_sci/gpio026 112 c8 i2c0_clk0/gpio015 77 h8 vcc1_rst#/gpio131 113 a7 led0/gpio154 78 g8 gpio141/pwm3/led3 114 b8 led1/gpio155 79 g12 vref_peci 115 c7 led2/gpio156 80 g9 gpio132/peci_dat 116 b7 gpio163 81 g11 gpio007/kso14 117 c10 vss 82 j9 vss 118 a6 gpio136/pwm1 83 f13 gpio010/kso15 119 g6 vcc1 84 j6 vcc1 120 b6 gpio133/pwm0 85 f11 gpio143/rsmrst# 121 c5 gpio034/pwm2/tach2pwm_out 86 d13 gpio162/rxd 122 a4 gpio135/kbrst 87 f7 gpio165/txd/shd_cs1# 123 b4 gpio044/nsmi 88 e13 gpio023/i2c1_dat0 124 c4 gpio066 89 e12 gpio022/i2c1_clk0 125 b3 gpio025/i2c3_dat0 90 e11 gpio021/i2c2_dat0 126 a3 gpio024/i2c3_clk0 91 d11 gpio020/i2c2_clk0 127 e6 gpio054/pvt_mosi 92 d12 gpio105/ta ch1 128 e5 gpio064/shd_mosi 93 c13 gpio145 129 g3 gpio067 94 f9 gpio164/pvt_miso 130 f2 gpio055 95 e9 gpio124/shd_miso 131 g1 gpio210 96 f8 gpio146/pvt_cs0# 132 n4 gpio211 97 e8 gpio150/shd_cs0# 133 l7 gpio200 98 b12 gpio157/bc_clk 134 j7 gpio123 99 b13 gpio160/bc_dat 135 h7 vcc1 100 a12 gpio161/bc_int# 136 f12 gpio202 101 a13 gpio140/tach2/tach2pwm_in 137 c12 gpio201 102 e7 gpio045/a20m/pvt_cs1# 138 h9 vss 103 c11 gpio053/ps2_clk3 139 b11 gpio203 104 j8 vss 140 c9 vss 105 a11 gpio152/ps2_dat3 141 c6 gpio204 106 h6 vcc1 142 m11 nc 107 a10 gpio030 143 d3 vss 108 b10 gpio012/kso17 144 b5 vss
? 2014 - 2015 microchip technology inc. ds00001719d-page 11 MEC1322 the pin name to package ball mapping of the 144 pin wfbga package is shown in figure 1-1: figure 1-1: MEC1322 pin name to 14 4-pin wfbga ball mapping (top) 1234567 a kso13/gpio00 6 gpio011/kso1 6 gpio024/i2c3_c lk0 gpio135/kbrst vss gpio136/pwm1 led0/gpio154 b kso12/gpio00 5 kso11/gpio10 7 gpio025/i2c3_d at0 gpio044/nsmi vss gpio133/pwm0 gpio163 c kso09/gpio10 6 kso10/gpio00 4 gpio036 gpio066 gpio034/pwm2/ tach2pwm_ou t gpio204 led2/gpio156 d vss kso08/gpio00 3 vss no ball no ball no ball no ball e kso06/gpio00 1 kso07/gpio00 2 vss no ball gpio064/shd_m osi gpio054/pvt_m osi gpio045/a20m/p vt_cs1# f cap gpio055 vss no ball gpio153/pvt_s clk gpio122/shd_s clk gpio165/txd/sh d_cs1# g gpio210 kso05/gpio10 4/tfdp_clk gpio067 no ball vcc1 vcc1 no ball h kso03/gpio10 2/jtag_tdo kso01/gpio10 0/jtag_tms kso04/gpio103/ tfdp_data/xno r no ball vcc1 vcc1 vcc1 j kso02/gpio10 1/jtag_tdi kso00/gpio00 0/jtag_tck jtag_rst# no ball vcc1 vcc1 gpio123 k ksi7/gpio043 ksi5/gpio040 ksi6/gpio042 no ball no ball no ball no ball l ksi4/gpio142/t raceclk ksi3/gpio032/t racedata0 ksi2/gpio144/tr acedata1 ps2_clk2/gpio 051 avcc adc1/gpio057 gpio200 m ksi0/gpio125/t racedata3 ksi1/gpio126/t racedata2 ps2_dat2/gpio 052 gpio151 adc3/gpio061 adc2/gpio060 avss n gpio127/peci_ rdy gpio031 gpio147 gpio211 adc4/gpio062 gpio206 adc0/gpio056
MEC1322 ds00001719d-page 12 ? 2014 - 2015 microchip technology inc. 1.3.1 non 5 volt tolerant pins there are no 5 volt toler ant pins in the MEC1322. 8 9 10 11 12 13 i2c0_dat0/gpio 016 i2c0_clk1/gpio 134 gpio030 gpio152/ps2_d at3 gpio161/bc_int # gpio140/tach2/ tach2p w m_in a led1/gpio155 i2c0_da t1/gp io 017 gpio012/kso17 gpio203 gpio157/bc_cl k gpio160/bc_da t b i2c0_clk0/gpio 015 vss vss gpio053/ps2_cl k3 gpio201 gpio145 c no ball no ball no ball gpio020/i2c2_c lk0 gpio105/tach1 gpio162/rxd d gpio150/shd_c s0# gpio124/shd_mi so no ball gpio021/i2c2_d at0 gpio022/i2c1_c lk0 gpio023/i2c1_d at0 e gpio146/pvt_c s0# gpio164/pvt_mi so no ball gpio143/rsmrs t# gpio202 gpio010/kso15 f gpio141/pwm3/ led3 gpio132/peci_d at no ball gpio007/kso14 vref_peci nec_sci/gp io02 6 g vcc1_rst#/gpi o131 vss no ball gpio130 32khz_out/gpi o013 gpio110 h vss vss no ball vcc_pw rgd/g pio063 ps2_dat0/gpio 047 xta l 1 j no ball no ball no ball ps2_clk0/gpio 046 vbat vss_vbat k lad2/gpio113 lad3/gpio111 ser_irq/gpio1 15 ps2_dat1/gpio 065 gpio033 xtal2 l lad1/gpio114 pci_clk/gpio11 7 clkrun#/gpio0 14 nc gpio035 gpio027 m lad0/gpio112 lframe#/gpio1 20 lreset#/gpio1 16 gpio041 nreset_out/g pio121 ps2_clk1/gpio 050 n
? 2014 - 2015 microchip technology inc. ds00001719d-page 13 MEC1322 1.3.2 por glitch protected pins all pins in the MEC1322 have por output glitch protection. po r output glitch protection ensures that pins will have a steady-state output during vcc1 por. in addition, signals in table 1-4 have additional drive low por circuitry. signals in ta b l e 1 - 4 refer to pin reference num- bers as defined in table 1-1 . these pins are anti-glitch, driven low on vcc1 por. table 1-4: glitch protec ted por drive low pins the following signals require a pull-down on the board: ? nreset_out/gpio121 ? gpio143/rsmrst# 1.3.3 non backdrive protected pins table 1-5 lists pins which do not have backdrive protection. signals in table 1-5 refer to pin reference numbers as defined in table 1-1 . these pins have no backdrive protection. if vcc1 is off must insure that none of these pins is above 0v to prevent back- drive onto the vcc1 supply. note: the gpio025/i2c3_dat0 pin is driven low, glitch free, while vcc1 is coming up. however, after vcc1 is up and stable, the pin becomes an input (i.e., tri-stated open drain type), as shown in table 1-37, ?multi- plexing table (16 of 18),? on page 36 . note: these glitch protected pins hav e no backdrive protection. see section 1.3.3, "non backdrive protected pins" . pin reference number pin name 60 nreset_out/gpio121 77 vcc1_rst#/gpio131 85 gpio143/rsmrst# 125 gpio025/i2c3_dat0
MEC1322 ds00001719d-page 14 ? 2014 - 2015 microchip technology inc. table 1-5: non backdrive protected pins 1.4 pin description 1.4.1 overview the following tables describe the signal functions in the MEC1322 pin configuration. see section 1.6, "notes for tables in this chapter," on page 39 for notes that are referenced in the pin description tables. 1.4.2 host interface table 1-6: host interface pin reference number pin name 38 adc4/gpio062 39 adc3/gpio061 42 adc2/gpio060 43 adc1/gpio057 44 adc0/gpio056 46 lad0/gpio112 48 lad1/gpio114 50 lad2/gpio113 51 lad3/gpio111 52 lframe#/gpio120 53 lreset#/gpio116 54 pci_clk/gpio117 55 clkrun#/gpio014 57 ser_irq/gpio115 60 nreset_out/gpio121 69 xtal2 71 xtal1 77 vcc1_rst#/gpio131 79 vref_peci 80 gpio132/peci_dat 85 gpio143/rsmrst# 125 gpio025/i2c3_dat0 host interface (11 pins) pin ref. number signal name description notes 57 ser_irq serial irq note 1 53 lreset# lpc reset. lreset# is the same as the system pci reset, pcirst# 54 pci_clk pci clock 52 lframe# frame signal. indicates start of new cycle and termination of broken cycle 46 lad0 lpc multiplexed command, address and data bus bit 0. note 1 48 lad1 lpc multiplexed command, address and data bus bit 1. note 1 50 lad2 lpc multiplexed command, address and data bus bit 2. note 1 51 lad3 lpc multiplexed command, address and data bus bit 3. note 1 55 clkrun# pci clock control 76 nec_sci power management event 123 nsmi smi output
? 2014 - 2015 microchip technology inc. ds00001719d-page 15 MEC1322 1.4.3 bc-link interface table 1-7: bc-link interface 1.4.4 jtag interface table 1-8: jtag interface 1.4.5 master clock interface table 1-9: master clock interface 1.4.6 analog data acquisition interface table 1-10: analog data acquisition note: jtag_tdo is a push-pull output. this function is not configur ed through the associated gpio pin control register ; however the drive strength is configured through the associated gpio pin control register 2 . bc-link interface (3 pins) pin ref. number signal name description notes 98 bc_clk bc-link master clock 99 bc_dat bc-link master data i/o note 7 100 bc_int# bc-link master interrupt jtag interface (5 pins) pin ref. number signal name description notes 21 jtag_tck jtag test clock 19 jtag_tdi jtag test data in 18 jtag_tdo jtag test data out 20 jtag_tms jtag test mode select 49 jtag_rst# jtag test reset (active low) note 2 master clock interface (3 pins) pin ref. number signal name description notes 71 xtal1 32.768 khz crystal output note 9 69 xtal2 32.768 khz crystal input (single-ended 32.768 khz clock input) note 9 75 32khz_out 32.768 khz digital output analog data acquisition interface (5 pins) pin ref. number signal name description notes 44 adc0 adc channel 0 note 8 43 adc1 adc channel 1 note 8 42 adc2 adc channel 2 note 8 39 adc3 adc channel 3 note 8 38 adc4 adc channel 4 note 8
MEC1322 ds00001719d-page 16 ? 2014 - 2015 microchip technology inc. 1.4.7 fan tachometer and pwm interface table 1-11: fan tachometer and pwm interface 1.4.8 general purp ose i/o interface table 1-12: gpio interface 1.4.9 miscellaneous functions table 1-13: miscellaneous functions note 1: the kbrst pin function is the out put of cpu_reset described in section 11.11.2, "cpu_reset hard- ware speed-up," on page 151 . 2: the nreset_out pin function is an external output sig nal version of the intern al signal nsio_reset. see the ireset_out bit in the power reset control (pwr_rst_ctrl) register on page 71 and nsio_re- set in table 3-7, ?definition of reset signals,? on page 52 . 3: xnor is a push-pull output. this function is not configured through the associated gpio pin control reg- ister ; however the drive strength is conf igured through the associated gpio pin control register 2 . note: no gpio pin should be left floating in a system. if a gpio pin is not in use, it should be ei ther tied high, tied low, or pulled to either power or ground through a resistor. pwm & tachometer (6 pins) pin ref. number signal name description notes 92 tach1 fan tachometer input 2 101 tach2pwm_in tach input to rpm-based fan speed control algorithm 120 pwm0 pulse width modulator output 0 118 pwm1 pulse width modulator output 1 78 pwm3 pulse width modulator output 3 121 tach2pwm_out pulse width modulator output from rpm based fan speed control algorithm gpio interface pin ref. number signal name description notes see pin configuration table gpio general purpose input output pins note 12 misc functions (13 pins) pin ref. number signal name description notes 102 a20m kbd gatea20 output 122 kbrst cpu_reset 113 led0 led (bllinking/breathing pwm) output 0 114 led1 led (bllinking/breathing pwm) output 1 115 led2 led (bllinking/breathing pwm) output 2 78 led3 led (bllinking/breathing pwm) output 3 16 tfdp_clk trace fifo debug port - clock 17 tfdp_data trace fifo debug port - data 60 nreset_out ec-driven external system reset note 6 72 vcc_pwrgd system main power indication 77 vcc1_rst# reset generator output 85 rsmrst# resume reset output note 6 17 xnor test output
? 2014 - 2015 microchip technology inc. ds00001719d-page 17 MEC1322 1.4.10 ps/2 interface table 1-14: ps/2 interface 1.4.11 power interface table 1-15: power interface application note: see figure 3-1: recommended battery circuit on page 49 . 1.4.12 smbus interface table 1-16: smbus interface ps/2 interface (8 pins) pin ref. number signal name description notes 35 ps2_clk2 ps/2 clock 2 32 ps2_dat2 ps/2 data 2 61 ps2_clk1 ps/2 clock 1 62 ps2_dat1 ps/2 data 1 66 ps2_clk0 ps/2 clock 0 67 ps2_dat0 ps/2 data 0 103 ps2_clk3 ps/2 clock 3 105 ps2_dat3 ps/2 data 3 power interface (18 pins) pin ref. number signal name description notes 70 vss_vbat vbat associated ground 68 vbat vbat supply 15 cap internal voltage regulator capacitor note 3 11, 36, 47, 56, 82, 104, 117 vss vcc1 associated ground 14, 37, 58, 84, 106, 119 vcc1 vcc1 supply 45 avss analog adc supply associated ground 40 avcc analog adc vcc1 associated supply smbus interface (10 pins) pin ref. number signal name description notes 112 i2c0_clk0 smbus controller 0 port 0 clock 111 i2c0_dat0 smbus controller 0 port 0 data 110 i2c0_clk1 smbus controller 0 port 1 clock 109 i2c0_dat1 smbus controller 0 port 1 data 89 i2c1_clk0 smbus controller 1 clock 88 i2c1_dat0 smbus controller 1 data 91 i2c2_clk0 smbus controller 2 clock 90 i2c2_dat0 smbus controller 2 data 126 i2c3_clk0 smbus controller 3 clock 125 i2c3_dat0 smbus controller 3 data
MEC1322 ds00001719d-page 18 ? 2014 - 2015 microchip technology inc. 1.4.13 peci interface table 1-17: peci interface 1.4.14 keyboard scan interface table 1-18: keyboard scan interface peci interface (3 pins) pin ref. number signal name description notes 80 peci_dat peci bus 31 peci_rdy peci ready 79 vref_peci peci voltage reference keyboard scan interface (26 pins) pin ref. number signal name description notes 29 ksi0 keyboard scan matrix input 0 note 11 28 ksi1 keyboard scan matrix input 1 note 11 27 ksi2 keyboard scan matrix input 2 note 11 26 ksi3 keyboard scan matrix input 3 note 11 25 ksi4 keyboard scan matrix input 4 note 11 24 ksi5 keyboard scan matrix input 5 note 11 23 ksi6 keyboard scan matrix input 6 note 11 22 ksi7 keyboard scan matrix input 7 note 11 21 kso00 keyboard scan matrix output 0 20 kso01 keyboard scan matrix output 1 19 kso02 keyboard scan matrix output 2 18 kso03 keyboard scan matrix output 3 17 kso04 keyboard scan matrix output 4 16 kso05 keyboard scan matrix output 5 13 kso06 keyboard scan matrix output 6 12 kso07 keyboard scan matrix output 7 10 kso08 keyboard scan matrix output 8 9 kso09 keyboard scan matrix output 9 8 kso10 keyboard scan matrix output 10 7 kso11 keyboard scan matrix output 11 6 kso12 keyboard scan matrix output 12 5 kso13 keyboard scan matrix output 13 81 kso14 keyboard scan matrix output 14 83 kso15 keyboard scan matrix output 15 4 kso16 keyboard scan matrix output 16 108 kso17 keyboard scan matrix output 17
? 2014 - 2015 microchip technology inc. ds00001719d-page 19 MEC1322 1.4.15 spi controller interface table 1-19: spi controller interface 1.4.16 trace debug interface table 1-20: trace debug interface the trace debug interface is enabled using the trace_en bit in the etm trace enable register defined in chapter 35.0, "ec subsystem registers" . 1.4.17 uart port table 1-21: uart port 1.5 pin multiplexing multifunction pin multiplexing in the MEC1322 is controlled by the gpio interface and illustrated in the multiplexing tables that follow. see section 1.6, "notes for tables in this chapter," on page 39 for notes that are referenced in the pin multiplexing tables. see section 20.8.1, "pin control register," on page 250 for pin multiplexing programming details. see also section 20.7, "pin multiplexing control," on page 248 . pin signal functions that exhi bit power domain emulation (see multiplexing tables below) have a different power supply designation in the ?emulated power well? colu mn and ?signal power well? columns of the multiplexing tables in section 1.5.2 . note: these pins are push-pull outpu ts when enabled as the trace debug interface pin functions. this function- ality is not configured through the associated gpio pin control register ; however the drive strength of these pins is configured through the associated gpio pin control register 2 . spi controllers interface (10 pins) pin ref. number signal name description notes 3 shd_sclk shared spi clock note 10 128 shd_mosi shared spi output note 10 95 shd_miso shared spi input note 10 97 shd_cs0# shared spi chip select 0 note 10 87 shd_cs1# shared spi chip select 1 2 pvt_sclk private spi clock note 10 127 pvt_mosi private spi output note 10 94 pvt_miso private spi input note 10 96 pvt_cs0# private spi chip select 0 note 10 102 pvt_cs1# private spi chip select 1 trace debug interface (5 pins) pin ref. number signal name description notes 25 traceclk trace clock 26 tracedata0 trace data 0 27 tracedata1 trace data 1 28 tracedata2 trace data 2 29 tracedata3 trace data 3 uart port (2 pins) pin ref. number signal name description notes 86 rxd uart receive data 87 txd uart transmit data
MEC1322 ds00001719d-page 20 ? 2014 - 2015 microchip technology inc. 1.5.1 vcc2 power domain emulation the system runtime supply power vcc2 is not connected to the MEC1322. the vcc_pwrgd signal is used to indi- cate when power is applied to the system runtime supply. pin signal functions with vcc2 power dom ain emulation are documented in the multiplexing tables as ?signal power well?= vcc1 and ?emulated power well? = vcc2. these pi ns are powered by vcc1 and controlled by the vcc_p- wrgd signal input. outputs on vcc2 power domain emulat ion pin signal functions are tri-stated when vcc_pwrgd is not asserted and are functional when vcc_pwrgd is active. inputs on vcc2 power domain emulation pin signal functions are gated according as defined by the gated state column in the following tables. power well emulation for gpios and for signals that are multiplexed with gpio signals is controlled by the power gating signals field in the gpio pin control register. 1.5.2 multiplexing tables in the following tables, the columns have the following meanings: mux if the pin has an associated gpio, then the mux column refers to the mux control field in the gpio pin control register . setting the mux control field to value listed in the row will configure the pin for the signal listed in the signal column on the same row. the row marked ?default? is the setting that is assigned on system reset. if there is no gpio associated with a pi n, then the pin has a single function. signal this column lists the signals that can appear on each pin, as configured by the mux control. buffer type pin buffer types are defined in table 37-4, ?dc electrical characteristics,? on page 391 . note that all gpio pins are of buffer type pio, which may be configured as input/output, push-pull/od etc. via the gpio pin control register and pin control register 2 . there are some pins where the buffer type is configured by the alternate function selection, in which case that buffer type is shown in this column. default operation this column gives the pin behavior following the power-up of vcc1. all gpio pins are programmable after this event. this default pin behavior corresponds to th e row marked ?default? in the mux column. signal power well this column defines the power well that powers the pin. emulated power well power well emulation for gpios and for signals that are mu ltiplexed with gpio signals is controlled by the power gating signals field in the gpio pin control register. power well emulation for signals that are not multiplexed with gpio signals is defined by the entries in this column. see section 1.5.1, "vcc2 po wer domain emulation" . gated state this column defines the internal value of an input signal wh en either its emulated power well is inactive or it is not selected by the gpio alternate function mux. a value of ?no gate? means that the internal signal always follows the pin even when the emulated power well is inactive. note: an internal pull-up resistor is indicated by (pu) and and internal pull-down is indicated by (pd). these are configured via the gpio pin control register . note: the glitch protected por drive low pins are configured as ?always on?, as indicated by ?on? in this col- umn. note: gated state is only meaningful to the operation of input signals. a gated state on an output pin defines the internal behavior of the gpio mux and does not imply pin behavior.
? 2014 - 2015 microchip technology inc. ds00001719d-page 21 MEC1322 table 1-22: multiplexing table (1 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 1 default: 0 gpio036 pio i (pu) vcc1 vcc1 no gate 1 1 reserved reserved reserved reserved 1 2 reserved reserved reserved reserved 1 3 reserved reserved reserved reserved 2 default: 0 gpio153 pio i vcc1 vcc1 no gate note 10 2 1 pvt_sclk pio vcc1 vcc1 note 10 2 2 reserved reserved reserved reserved 2 3 reserved reserved reserved reserved 3 default: 0 gpio122 pio i (pd) vcc1 vcc1 no gate note 10 3 1 shd_sclk pio vcc1 vcc1 note 10 3 2 reserved reserved reserved reserved 3 3 reserved reserved reserved reserved 4 default: 0 gpio011 pio iod (pd) vcc1 vcc1 no gate 4 1 reserved reserved reserved reserved 4 2 reserved reserved reserved reserved 4 3 kso16 pio vcc1 vcc1 5 0 gpio006 pio vcc1 vcc1 no gate 5 1 reserved reserved reserved reserved 5 2 reserved reserved reserved reserved 5 default: 3 kso13 pio o-4ma vcc1 vcc1 6 0 gpio005 pio vcc1 vcc1 no gate 6 1 reserved reserved reserved reserved 6 2 reserved reserved reserved reserved 6 default: 3 kso12 pio o-4ma (pd) vcc1 vcc1 7 0 gpio107 pio vcc1 vcc1 no gate 7 1 reserved reserved reserved reserved 7 2 reserved reserved reserved reserved 7 default: 3 kso11 pio o-4ma vcc1 vcc1 8 0 gpio004 pio vcc1 vcc1 no gate 8 1 reserved reserved reserved reserved 8 2 reserved reserved reserved reserved 8 default: 3 kso10 pio o-4ma vcc1 vcc1
MEC1322 ds00001719d-page 22 ? 2014 - 2015 microchip technology inc. table 1-23: multiplexing table (2 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 9 0 gpio106 pio vcc1 vcc1 no gate 9 1 reserved reserved reserved reserved 9 2 reserved reserved reserved reserved 9 default: 3 kso09 pio o-4ma vcc1 vcc1 10 0 gpio003 pio vcc1 vcc1 no gate 10 1 reserved reserved reserved reserved 10 2 reserved reserved reserved reserved 10 default: 3 kso08 pio o-4ma vcc1 vcc1 11 vss pwr pwr pwr 11 11 11 12 0 gpio002 pio vcc1 vcc1 no gate 12 1 reserved reserved reserved reserved 12 2 reserved reserved reserved reserved 12 default: 3 kso07 pio o-4ma vcc1 vcc1 13 0 gpio001 pio vcc1 vcc1 no gate 13 1 reserved reserved reserved reserved 13 2 reserved reserved reserved reserved 13 default: 3 kso06 pio o-4ma vcc1 vcc1 14 vcc1 pwr pwr pwr 14 14 14 15 cap pwr pwr pwr note 3 15 15 15 16 0 gpio104 pio vcc1 vcc1 no gate 16 1 tfdp_clk pio vcc1 vcc1 16 2 reserved reserved reserved reserved 16 default: 3 kso05 pio o-4ma vcc1 vcc1
? 2014 - 2015 microchip technology inc. ds00001719d-page 23 MEC1322 table 1-24: multiplexing table (3 of 18) pin ref. number mux signal buffer type default operation signal power well emula te d power well gated state notes 17 0 gpio103 pio vcc1 vcc1 no gate 17 1 tfdp_data pio vcc1 vcc1 17 2 reserved reserved reserved reserved 17 default: 3 kso04 pio o-4ma vcc1 vcc1 18 0 gpio102 pio vcc1 vcc1 no gate 18 1 reserved reserved reserved reserved 18 2 reserved reserved reserved reserved 18 default: 3 kso03 pio o-4ma vcc1 vcc1 19 0 gpio101 pio vcc1 vcc1 no gate 19 1 reserved reserved reserved reserved 19 2 reserved reserved reserved reserved 19 default: 3 kso02 pio o-4ma vcc1 vcc1 20 0 gpio100 pio vcc1 vcc1 no gate 20 1 reserved reserved reserved reserved 20 2 reserved reserved reserved reserved 20 default: 3 kso01 pio o-4ma vcc1 vcc1 21 0 gpio000 pio vcc1 vcc1 no gate 21 1 reserved reserved reserved reserved 21 2 reserved reserved reserved reserved 21 default: 3 kso00 pio o-4ma vcc1 vcc1 22 0 gpio043 pio vcc1 vcc1 no gate 22 1 reserved reserved reserved reserved 22 2 reserved reserved reserved reserved 22 default: 3 ksi7 pio i vcc1 vcc1 low note 11 23 0 gpio042 pio vcc1 vcc1 no gate 23 1 reserved reserved reserved reserved 23 2 reserved reserved reserved reserved 23 default: 3 ksi6 pio i vcc1 vcc1 low note 11 24 0 gpio040 pio vcc1 vcc1 no gate 24 1 reserved reserved reserved reserved 24 2 reserved reserved reserved reserved 24 default: 3 ksi5 pio i vcc1 vcc1 low note 11
MEC1322 ds00001719d-page 24 ? 2014 - 2015 microchip technology inc. table 1-25: multiplexing table (4 of 18) pin ref. number mux signal buffer type default operation signal power well emula te d power well gated state notes 25 0 gpio142 pio vcc1 vcc1 no gate 25 1 reserved reserved reserved reserved 25 2 reserved reserved reserved reserved 25 default: 3 ksi4 pio i vcc1 vcc1 low note 11 26 0 gpio032 pio vcc1 vcc1 no gate 26 1 reserved reserved reserved reserved 26 2 reserved reserved reserved reserved 26 default: 3 ksi3 pio i vcc1 vcc1 low note 11 27 0 gpio144 pio vcc1 vcc1 no gate 27 1 reserved reserved reserved reserved 27 2 reserved reserved reserved reserved 27 default: 3 ksi2 pio i vcc1 vcc1 low note 11 28 0 gpio126 pio vcc1 vcc1 no gate 28 1 reserved reserved reserved reserved 28 default: 2 ksi1 pio i vcc1 vcc1 low note 11 28 3 reserved reserved reserved reserved 29 0 gpio125 pio vcc1 vcc1 no gate 29 1 reserved reserved reserved reserved 29 default: 2 ksi0 pio i vcc1 vcc1 low note 11 29 3 reserved reserved reserved reserved 30 default: 0 gpio031 pio i (pu) vcc1 vcc1 no gate 30 1 reserved reserved reserved reserved 30 2 reserved reserved reserved reserved 30 3 reserved reserved reserved reserved 31 default: 0 gpio127 pio i vcc1 vcc1 no gate 31 1 peci_rdy pio vcc1 vcc1 high 31 2 reserved reserved reserved reserved 31 3 reserved reserved reserved reserved 32 0 gpio052 pio vcc1 vcc1 no gate 32 1 reserved reserved reserved reserved 32 default: 2 ps2_dat2 pio iod-12ma vcc1 vcc1 low 32 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 25 MEC1322 table 1-26: multiplexing table (5 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 33 default: 0 gpio147 pio i (pu) vcc1 vcc1 no gate 33 1 reserved reserved reserved reserved 33 2 reserved reserved reserved reserved 33 3 reserved reserved reserved reserved 34 default: 0 gpio151 pio i (pu) vcc1 vcc1 no gate 34 1 reserved reserved reserved reserved 34 2 reserved reserved reserved reserved 34 3 reserved reserved reserved reserved 35 0 gpio051 pio vcc1 vcc1 no gate 35 1 reserved reserved reserved reserved 35 default: 2 ps2_clk2 pio iod-12ma vcc1 vcc1 low 35 3 reserved reserved reserved reserved 36 vss pwr pwr pwr 36 36 36 37 vcc1 pwr pwr pwr 37 37 37 38 0 gpio062 pio vcc1 vcc1 no gate 38 default: 1 adc4 i_an i_an avcc1_adc avcc1_adc low note 8 38 2 reserved reserved reserved reserved 38 3 reserved reserved reserved reserved 39 0 gpio061 pio vcc1 vcc1 no gate 39 default: 1 adc3 i_an i_an avcc1_adc avcc1_adc low note 8 39 2 reserved reserved reserved reserved 39 3 reserved reserved reserved reserved 40 avcc pwr pwr pwr 40 40 40
MEC1322 ds00001719d-page 26 ? 2014 - 2015 microchip technology inc. table 1-27: multiplexing table (6 of 18) pin ref. number mux signal buffer type default operation signal power well emula te d power well gated state notes 41 default: 0 gpio206 pio i vcc1 vcc1 no gate 41 1 reserved reserved reserved reserved 41 2 reserved reserved reserved reserved 41 3 reserved reserved reserved reserved 42 0 gpio060 pio vcc1 vcc1 no gate 42 default: 1 adc2 i_an i_an (pu) avcc1_adc avcc1_adc low note 8 42 2 reserved reserved reserved reserved 42 3 reserved reserved reserved reserved 43 0 gpio057 pio vcc1 vcc1 no gate 43 default: 1 adc1 i_an i_an avcc1_adc avcc1_adc low note 8 43 2 reserved reserved reserved reserved 43 3 reserved reserved reserved reserved 44 0 gpio056 pio vcc1 vcc1 no gate 44 1 adc0 i_an avcc1_adc avcc1_adc low note 8 44 2 reserved reserved reserved reserved 44 default: 3 adc0 i_an i_an avcc1_adc avcc1_adc low note 8 45 avss pwr pwr pwr 45 45 45 46 0 gpio112 pci_pio vcc1 vcc1 no gate 46 default: 1 lad0 pci_io pci_io vcc1 vcc1 high note 1 46 2 reserved reserved reserved reserved 46 3 reserved reserved reserved reserved 47 vss pwr pwr pwr 47 47 47 48 0 gpio114 pci_pio vcc1 vcc1 no gate 48 default: 1 lad1 pci_io pci_io vcc1 vcc1 high note 1 48 2 reserved reserved reserved reserved 48 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 27 MEC1322 table 1-28: multiplexing table (7 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 49 default: 0 jtag_rst# i i vcc1 vcc1 no gate note 2 49 1 reserved reserved reserved reserved 49 2 reserved reserved reserved reserved 49 3 reserved reserved reserved reserved 50 0 gpio113 pci_pio vcc1 vcc1 no gate 50 default: 1 lad2 pci_io pci_io vcc1 vcc1 high note 1 50 2 reserved reserved reserved reserved 50 3 reserved reserved reserved reserved 51 0 gpio111 pci_pio vcc1 vcc1 no gate 51 default: 1 lad3 pci_io pci_io vcc1 vcc1 high note 1 51 2 reserved reserved reserved reserved 51 3 reserved reserved reserved reserved 52 0 gpio120 pci_pio vcc1 vcc1 no gate 52 default: 1 lframe# pci_i pci_i vcc1 vcc1 high 52 2 reserved reserved reserved reserved 52 3 reserved reserved reserved reserved 53 0 gpio116 pci_pio vcc1 vcc1 no gate 53 default: 1 lreset# pci_i pci_i vcc1 vcc1 low 53 2 reserved reserved reserved reserved 53 3 reserved reserved reserved reserved 54 0 gpio117 pci_pio vcc1 vcc1 no gate 54 default: 1 pci_clk pci_clk pci_clk vcc1 vcc1 low 54 2 reserved reserved reserved reserved 54 3 reserved reserved reserved reserved 55 0 gpio014 pci_pio vcc1 vcc1 no gate 55 default: 1 clkrun# pci_i pci_i vcc1 vcc1 low 55 2 reserved reserved reserved reserved 55 3 reserved reserved reserved reserved 56 vss pwr pwr pwr 56 56 56
MEC1322 ds00001719d-page 28 ? 2014 - 2015 microchip technology inc. table 1-29: multiplexing table (8 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 57 0 gpio115 pci_pio vcc1 vcc1 no gate 57 default: 1 ser_irq pci_i pci_i vcc1 vcc1 high note 1 57 2 reserved reserved reserved reserved 57 3 reserved reserved reserved reserved 58 vcc1 pwr pwr pwr 58 58 58 59 0 gpio041 pio vcc1 vcc1 no gate 59 default: 1 reserved pio o-8ma (pd) low vcc1 on note 12 59 2 reserved reserved reserved reserved 59 3 reserved reserved reserved reserved 60 0 gpio121 pio vcc1 vcc1 no gate 60 default: 1 nreset_out pio o-8ma vcc1 on note 6 60 2 reserved reserved reserved reserved 60 3 reserved reserved reserved reserved 61 0 gpio050 pio vcc1 vcc1 no gate 61 1 reserved reserved reserved reserved 61 default: 2 ps2_clk1 pio iod-12ma vcc1 vcc1 low 61 3 reserved reserved reserved reserved 62 0 gpio065 pio vcc1 vcc1 no gate 62 1 reserved reserved reserved reserved 62 default: 2 ps2_dat1 pio iod-12ma vcc1 vcc1 low 62 3 reserved reserved reserved reserved 63 default: 0 gpio035 pio i (pu) vcc1 vcc1 no gate 63 1 reserved reserved reserved reserved 63 2 reserved reserved reserved reserved 63 3 reserved reserved reserved reserved 64 default: 0 gpio027 pio i (pu) vcc1 vcc1 no gate 64 1 reserved reserved reserved reserved 64 2 reserved reserved reserved reserved 64 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 29 MEC1322 table 1-30: multiplexing table (9 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 65 default: 0 gpio033 pio i (pu) vcc1 vcc1 no gate 65 1 reserved reserved reserved reserved 65 2 reserved reserved reserved reserved 65 3 reserved reserved reserved reserved 66 0 gpio046 pio vcc1 vcc1 no gate 66 1 reserved reserved reserved reserved 66 default: 2 ps2_clk0 pio iod-12ma vcc1 vcc1 low 66 3 reserved reserved reserved reserved 67 0 gpio047 pio vcc1 vcc1 no gate 67 1 reserved reserved reserved reserved 67 default: 2 ps2_dat0 pio iod-12ma vcc1 vcc1 low 67 3 reserved reserved reserved reserved 6 8 vbat pwr pwr pwr 68 68 68 69 default: 0 xtal 2 ic l k vbat vbat n o te 9 69 1 reserved reserved reserved reserved 69 2 reserved reserved reserved reserved 69 3 reserved reserved reserved reserved 7 0 vss_ vbat pwr pwr pwr 70 70 70 71 default: 0 xtal 1 oc l k vbat vbat n o te 9 71 1 reserved reserved reserved reserved 71 2 reserved reserved reserved reserved 71 3 reserved reserved reserved reserved 72 0 gpio063 pio vcc1 vcc1 no gate 72 default: 1 vcc_pwrgd pio i vcc1 vcc1 high 72 2 reserved reserved reserved reserved 72 3 reserved reserved reserved reserved
MEC1322 ds00001719d-page 30 ? 2014 - 2015 microchip technology inc. table 1-31: multiplexing table (10 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 73 default: 0 gpio110 pio i vcc1 vcc1 no gate 73 1 reserved reserved reserved reserved 73 2 reserved reserved reserved reserved 73 3 reserved reserved reserved reserved 74 default: 0 gpio130 pio i vcc1 vcc1 no gate 74 1 reserved reserved reserved reserved 74 2 reserved reserved reserved reserved 74 3 reserved reserved reserved reserved 75 0 gpio013 pio vcc1 vcc1 no gate 75 1 reserved reserved reserved reserved 75 default: 2 32khz_out pio o-4ma vcc1 vcc1 75 3 reserved reserved reserved reserved 76 0 gpio026 pio vcc1 vcc1 no gate 76 1 reserved reserved reserved reserved 76 default: 2 nec_sci pio od-12ma vcc1 vcc1 76 3 reserved reserved reserved reserved 77 0 gpio131 pio vcc1 vcc1 no gate 77 default: 1 vcc1_rst# pio od-4ma vcc1 on high 77 2 reserved reserved reserved reserved 77 3 reserved reserved reserved reserved 78 default: 0 gpio141 pio i vcc1 vcc1 no gate 78 1 pwm3 pio vcc1 vcc1 78 2 led3 pio vcc1 vcc1 78 3 reserved reserved reserved reserved 79 vref_peci vref_peci vref_peci vref_peci 79 79 79 80 default: 0 gpio132 pio i vcc1 vcc1 no gate 80 1 peci_dat peci_io vref_peci vref_peci low 80 2 reserved reserved reserved reserved 80 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 31 MEC1322 table 1-32: multiplexing table (11 of 18) pin ref. number mux signal buffer type default operation signal power well emula te d power well gated state notes 81 default: 0 gpio007 pio i vcc1 vcc1 no gate 81 1 reserved reserved reserved reserved 81 2 reserved reserved reserved reserved 81 3 kso14 pio vcc1 vcc1 82 vss pwr pwr pwr 82 82 82 83 default: 0 gpio010 pio i vcc1 vcc1 no gate 83 1 reserved reserved reserved reserved 83 2 reserved reserved reserved reserved 83 3 kso15 pio vcc1 vcc1 84 vcc1 pwr pwr pwr 84 84 84 85 default: 0 gpio143 pio i vcc1 on no gate 85 1 rsmrst# pio vcc1 vcc1 note 6 85 2 reserved reserved reserved reserved 85 3 reserved reserved reserved reserved 86 default: 0 gpio162 pio i vcc1 vcc1 no gate 86 1 rxd pio vcc1 vcc1 high 86 2 reserved reserved reserved reserved 86 3 reserved reserved reserved reserved 87 default: 0 gpio165 pio i vcc1 vcc1 no gate 87 1 txd pio vcc1 vcc1 high 87 2 shd_cs1# pio vcc1 vcc1 high 87 3 reserved reserved reserved reserved 88 default: 0 gpio023 pio i vcc1 vcc1 no gate note 5 88 1 reserved reserved reserved reserved 88 2 i2c1_dat0 pio vcc1 vcc1 high 88 3 reserved reserved reserved reserved
MEC1322 ds00001719d-page 32 ? 2014 - 2015 microchip technology inc. table 1-33: multiplexing table (12 of 18) pin ref. number mux signal buffer type default operation signal power well emula te d power well gated state notes 89 default: 0 gpio022 pio i vcc1 vcc1 no gate note 5 89 1 reserved reserved reserved reserved 89 2 i2c1_clk0 pio vcc1 vcc1 high 89 3 reserved reserved reserved reserved 90 default: 0 gpio021 pio i vcc1 vcc1 no gate 90 1 reserved reserved reserved reserved 90 2 i2c2_dat0 pio vcc1 vcc1 high 90 3 reserved reserved reserved reserved 91 default: 0 gpio020 pio i vcc1 vcc1 no gate 91 1 reserved reserved reserved reserved 91 2 i2c2_clk0 pio vcc1 vcc1 high 91 3 reserved reserved reserved reserved 92 default: 0 gpio105 pio i vcc1 vcc1 no gate 92 1 tach1 pio vcc1 vcc1 low 92 2 reserved reserved reserved reserved 92 3 reserved reserved reserved reserved 93 default: 0 gpio145 pio i (pu) vcc1 vcc1 no gate 93 1 reserved reserved reserved reserved 93 2 reserved reserved reserved reserved 93 3 reserved reserved reserved reserved 94 default: 0 gpio164 pio i vcc1 vcc1 no gate note 10 94 1 pvt_miso pio vcc1 vcc1 low note 10 94 2 reserved reserved reserved reserved 94 3 reserved reserved reserved reserved 95 default: 0 gpio124 pio i vcc1 vcc1 no gate note 10 95 1 shd_miso pio vcc1 vcc1 low note 10 95 2 reserved reserved reserved reserved 95 3 reserved reserved reserved reserved 96 default: 0 gpio146 pio i vcc1 vcc1 no gate note 4, note 10 96 1 pvt_cs0# pio vcc1 vcc1 high note 10 96 2 reserved reserved reserved reserved 96 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 33 MEC1322 table 1-34: multiplexing table (13 of 18) pin ref. number mux signal buffer type default operation signal power well emula te d power well gated state notes 97 default: 0 gpio150 pio i vcc1 vcc1 no gate note 10 97 1 shd_cs0# pio vcc1 vcc1 high note 10 97 2 reserved reserved reserved reserved 97 3 reserved reserved reserved reserved 98 default: 0 gpio157 pio i (pu) vcc1 vcc1 no gate 98 1 bc_clk pio vcc1 vcc1 98 2 reserved reserved reserved reserved 98 3 reserved reserved reserved reserved 99 default: 0 gpio160 pio i (pu) vcc1 vcc1 no gate 99 1 bc_dat pio vcc1 vcc1 low note 7 99 2 reserved reserved reserved reserved 99 3 reserved reserved reserved reserved 100 default: 0 gpio161 pio i (pu) vcc1 vcc1 no gate 100 1 bc_int# pio vcc1 vcc1 high 100 2 reserved reserved reserved reserved 100 3 reserved reserved reserved reserved 101 default: 0 gpio140 pio i vcc1 vcc1 no gate 101 1 tach2 pio vcc1 vcc1 low 101 2 reserved reserved reserved reserved 101 3 tach2pwm_in pio vcc1 vcc1 low 102 default: 0 gpio045 pio i vcc1 vcc1 no gate 102 1 a20m pio vcc1 vcc1 102 2 pvt_cs1# pio vcc1 vcc1 high 102 3 reserved reserved reserved reserved 103 default: 0 gpio053 pio i vcc1 vcc1 no gate 103 1 reserved reserved reserved reserved 103 2 ps2_clk3 pio vcc1 vcc1 low 103 3 reserved reserved reserved reserved 104 vss pwr pwr pwr 104 104 104
MEC1322 ds00001719d-page 34 ? 2014 - 2015 microchip technology inc. table 1-35: multiplexing table (14 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 105 default: 0 gpio152 pio i vcc1 vcc1 no gate 105 1 reserved reserved reserved reserved 105 2 ps2_dat3 pio vcc1 vcc1 low 105 3 reserved reserved reserved reserved 106 vcc1 pwr pwr pwr 106 106 106 107 default: 0 gpio030 pio i vcc1 vcc1 no gate 107 1 reserved reserved reserved reserved 107 2 reserved reserved reserved reserved 107 3 reserved reserved reserved reserved 108 default: 0 gpio012 pio i vcc1 vcc1 no gate 108 1 reserved reserved reserved reserved 108 2 reserved reserved reserved reserved 108 3 kso17 pio vcc1 vcc1 109 0 gpio017 pio vcc1 vcc1 no gate 109 1 reserved reserved reserved reserved 109 default: 2 i2c0_dat1 pio iod-4m a vcc1 vcc1 high 109 3 reserved reserved reserved reserved 110 0 gpio134 pio vcc1 vcc1 no gate 110 1 reserved reserved reserved reserved 110 default: 2 i2c0_clk1 pio iod-4m a vcc1 vcc1 high 110 3 reserved reserved reserved reserved 111 0 gpio016 pio vcc1 vcc1 no gate 111 1 reserved reserved reserved reserved 111 default: 2 i2c0_dat0 pio iod-4m a vcc1 vcc1 high 111 3 reserved reserved reserved reserved 112 0 gpio015 pio vcc1 vcc1 no gate 112 1 reserved reserved reserved reserved 112 default: 2 i2c0_clk0 pio iod-4m a vcc1 vcc1 high 112 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 35 MEC1322 table 1-36: multiplexing table (15 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 113 0 gpio154 pio vcc1 vcc1 no gate 113 1 reserved reserved reserved reserved 113 default: 2 led0 pio od-12ma vcc1 vcc1 113 3 reserved reserved reserved reserved 114 0 gpio155 pio vcc1 vcc1 no gate 114 1 reserved reserved reserved reserved 114 default: 2 led1 pio od-12ma vcc1 vcc1 114 3 reserved reserved reserved reserved 115 0 gpio156 pio vcc1 vcc1 no gate 115 1 reserved reserved reserved reserved 115 default: 2 led2 pio od-12ma vcc1 vcc1 115 3 reserved reserved reserved reserved 116 default: 0 gpio163 pio i vcc1 vcc1 no gate 116 1 reserved reserved reserved reserved 116 2 reserved reserved reserved reserved 116 3 reserved reserved reserved reserved 117 vss pwr pwr pwr 117 117 117 118 default: 0 gpio136 pio i vcc1 vcc1 no gate 118 1 pwm1 pio vcc1 vcc1 118 2 reserved reserved reserved reserved 118 3 reserved reserved reserved reserved 119 vcc1 pwr pwr pwr 119 119 119 120 default: 0 gpio133 pio i vcc1 vcc1 no gate 120 1 pwm0 pio vcc1 vcc1 120 2 reserved reserved reserved reserved 120 3 reserved reserved reserved reserved
MEC1322 ds00001719d-page 36 ? 2014 - 2015 microchip technology inc. table 1-37: multiplexing table (16 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 121 default: 0 gpio034 pio i vcc1 vcc1 no gate 121 1 pwm2 pio vcc1 vcc1 121 2 reserved reserved reserved reserved 121 3 tach2pwm_out pio vcc1 vcc1 122 default: 0 gpio135 pio i vcc1 vcc1 no gate 122 1 kbrst pio vcc1 vcc1 122 2 reserved reserved reserved reserved 122 3 reserved reserved reserved reserved 123 default: 0 gpio044 pio i vcc1 vcc1 no gate 123 1 nsmi pio vcc1 vcc1 123 2 reserved reserved reserved reserved 123 3 reserved reserved reserved reserved 124 default: 0 gpio066 pio i vcc1 vcc1 no gate 124 1 reserved reserved reserved reserved 124 2 reserved reserved reserved reserved 124 3 reserved reserved reserved reserved 125 default: 0 gpio025 pio i vcc1 on no gate 125 1 reserved reserved reserved reserved 125 2 i2c3_dat0 pio vcc1 vcc1 high 125 3 reserved reserved reserved reserved 126 default: 0 gpio024 pio i (pu) vcc1 vcc1 no gate 126 1 reserved reserved reserved reserved 126 2 i2c3_clk0 pio vcc1 vcc1 high 126 3 reserved reserved reserved reserved 127 default: 0 gpio054 pio i vcc1 vcc1 no gate note 10 127 1 pvt_mosi pio vcc1 vcc1 note 10 127 2 reserved reserved reserved reserved 127 3 reserved reserved reserved reserved 128 default: 0 gpio064 pio i vcc1 vcc1 no gate note 10 128 1 shd_mosi pio vcc1 vcc1 note 10 128 2 reserved reserved reserved reserved 128 3 reserved reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 37 MEC1322 table 1-38: multiplexing table (17 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 129 default: 0 gpio067 pio i (pd) vcc1 on no gate 129 1 reserved reserved reserved reserved 129 2 reserved reserved reserved reserved 129 3 reserved reserved reserved reserved 130 default: 0 gpio055 pio i (pd) vcc1 on no gate 130 1 reserved reserved reserved reserved 130 2 reserved reserved reserved reserved 130 3 reserved reserved reserved reserved 131 default: 0 gpio210 pio i (pd) vcc1 on no gate 131 1 reserved reserved reserved reserved 131 2 reserved reserved reserved reserved 131 3 reserved reserved reserved reserved 132 default: 0 gpio211 pio i (pd) vcc1 on no gate 132 1 reserved reserved reserved reserved 132 2 reserved reserved reserved reserved 132 3 reserved reserved reserved reserved 133 default: 0 gpio200 pio i (pd) vcc1 on no gate 133 1 reserved reserved reserved reserved 133 2 reserved reserved reserved reserved 133 3 reserved reserved reserved reserved 134 default: 0 gpio123 pio i (pd) vcc1 on no gate 134 1 reserved reserved reserved reserved 134 2 reserved reserved reserved reserved 134 3 reserved reserved reserved reserved 135 vcc1 pwr pwr pwr 135 135 135 136 default: 0 gpio202 pio i (pd) vcc1 on no gate 136 1 reserved reserved reserved reserved 136 2 reserved reserved reserved reserved 136 3 reserved reserved reserved reserved
MEC1322 ds00001719d-page 38 ? 2014 - 2015 microchip technology inc. table 1-39: multiplexing table (18 of 18) pin ref. number mux signal buffer type default operation signal power well emulated power well gated state notes 137 default: 0 gpio201 pio i (pd) vcc1 on no gate 137 1 reserved reserved reserved reserved 137 2 reserved reserved reserved reserved 137 3 reserved reserved reserved reserved 138 vss pwr pwr pwr 138 138 138 139 default: 0 gpio203 pio i (pd) vcc1 on no gate 139 1 reserved reserved reserved reserved 139 2 reserved reserved reserved reserved 139 3 reserved reserved reserved reserved 140 vss pwr pwr pwr 140 140 140 141 default: 0 gpio204 pio i (pd) vcc1 on no gate 141 1 reserved reserved reserved reserved 141 2 reserved reserved reserved reserved 141 3 reserved reserved reserved reserved 142 nc 142 142 142 143 vss pwr pwr pwr 143 143 143 144 vss pwr pwr pwr 144 144 144
? 2014 - 2015 microchip technology inc. ds00001719d-page 39 MEC1322 1.6 notes for tables in this chapter 1.7 pin states after vcc1 power-on pins that default to iod or od in the multiplexing tables are open drain and come up tri-stated after vcc1 power-on. pins that default to i are inputs and also come up tri-stated (high-z). table 1-40 shows pins that have specific states after vcc1 power-on. note 1 the lad and ser_irq pins require an external weak pull-up resistor of 10k-100k ohms. note 2 when the jtag_rst# pin is not asserted (logic '1'), the jtag_tdi, jtag_tdo, jtag_tck, jtag_tms signal functions in the jtag interface are unconditionally routed to the interface; the pin control register for these pins has no effect. when the jtag_rst# pin is asserted (logic '0'), the jtag_tdi, jtag_tdo, jtag_tck, jtag_tms signal functions in the jtag interface are not routed to the interface and the pin control register for these pins controls the muxing. the pin control registers can not be used to route the jtag interface to the pins. the system board designer should terminate this pin in all functional states using jumpers and pull-up or pull down resistors, etc. note 3 an external cap must be connected as close to the cap pin/ball as possible with a routing resistance and cap esr of less than 100mohms. the capacitor value is 1uf and must be ceramic with x5r or x7r dielectric. the cap pin/ball should remain on the top layer of the pcb and traced to the cap. avoid adding vias to other layers to minimize inductance. note 4 a pull-down is required on the gpio146/pvt_cs0# pin if there is no private spi flash device on the board. note 5 this i2c port supports 1mbps (pin 88, gpio023/i2c1_dat0 and pin 89, gpio022/i2c1_clk0). for 1mbps i2c recommended capacitance/pull-up relationships from intel, refer to the shark bay platform guide, intel ref number 486714. refer to the pch - smbus 2.0/smlink interface design guidelines, table 20-5 bus capacitance/pull-up resistor relationship. note 6 the following glitch protected pins require a pull-down on the board: pin 60, nreset_out/gpio121 and pin 85, gpio143/rsmrst#. the nreset_out pin w ill drive low when vcc1 comes on and stays low until the ireset_out bit is cleared after vcc pwrgd asserts. the rsmrst# pin also drives low (as a gpio push-pull output) following a vcc1 power-on until firmware deasserts it by writing the gpio data bit to '1'. the gpio143/rsmrst# pin operates in this manner as a gpio; the rsmrst# function is not a true alternate function and the gpio143 control register must not be changed from the gpio default function. note 7 the bc dat pin requires a weak pull up resistor (100 k ohms). note 8 the voltage on the adc pins must not exceed 3.6 v or damage to the device will occur. note 9 the xtal1 pin should be left floating when using the xtal2 pin for the single ended clock input. note 10 MEC1322: the spi pins are configured to their spi function by rom boot code as follows. shared spi pins are configured to the following spi functions: shd_clk, shd_mosi, shd_miso and shd_cs0#. if the pvt_cs0# pin (pin 96) is sampled high, then the private spi pins are configured to the following spi functions after a successful load from flash: pvt_clk, pvt_mosi, pvt_miso and pvt_cs0#; otherwise these pins are left as the gpio function. it is recommended that user code reconfigures the shared spi pins to the gpio input function before releasing rsmrst#. note 11 the ksi[7:0] pins have the internal pull-up enabled by rom boot code. therefore the buffer type on these pins is i (pu) after the rom boot code runs. note 12 the gpio041 pin defaults to output low. this pin must be reprogrammed to the gpio function upon power- up.
MEC1322 ds00001719d-page 40 ? 2014 - 2015 microchip technology inc. table 1-40: pin states after vcc1 power-on pin reference num ber pin name pin state after vcc1 power-on 21 kso00/gpio000/jtag_tck push-pull - high 20 kso01/gpio100/jtag_tms push-pull - high 19 kso02/gpio101/jtag_tdi push-pull - high 18 kso03/gpio102/jtag_tdo push-pull - high 17 kso04/gpio103/tfdp_data/xno r push-pull - high 16 kso05/gpio104/tfdp_clk push-pull - high 13 kso06/gpio001 push-pull - high 12 kso07/gpio002 push-pull - high 10 kso08/gpio003 push-pull - high 9 kso09/gpio106 push-pull - high 8 kso10/gpio004 push-pull - high 7 kso11/gpio107 push-pull - high 6 kso12/gpio005 push-pull - high 5 kso13/gpio006 push-pull - high 113 led0/gpio154 od - low 114 led1/gpio155 od - low 115 led2/gpio156 od - low 66 ps2_clk0/gpio046 iod - low 61 ps2_clk1/gpio050 iod - low 35 ps2_clk2/gpio051 iod - low 60 nreset_out/gpio121 glitch protected - driven low w hile vc c 1 is rising. the pin becom es a push-pull output after vcc1 is up and stable (requires a pull-down on the board) 77 vcc1_rst#/gpio131 glitch protected - driven low w hile vc c 1 is rising. the pin becom es od after vcc1 is up and stable (requires a pull-up on the board) 85 gpio143/rsmrst# glitch protected - driven low w hile vc c 1 is rising. the pin becom es a push-pull output after vcc1 is up and stable (requires a pull-down on the board) 125 gpio025/i2c3_dat0 glitch protected - driven low while vcc1 is rising. the pin becom es an input (i.e., tri-stated od type) after vcc1 is up and stable.
? 2014 - 2015 microchip technology inc. ds00001719d-page 41 MEC1322 1.8 package outline figure 1-2: 128-pin vtqfp package outline
MEC1322 ds00001719d-page 42 ? 2014 - 2015 microchip technology inc. figure 1-3: 132-pin dqfn package outline (1 of 2)
? 2014 - 2015 microchip technology inc. ds00001719d-page 43 MEC1322 figure 1-4: 132-pin dqfn package outline (2 of 2)
MEC1322 ds00001719d-page 44 ? 2014 - 2015 microchip technology inc. figure 1-5: 144-pin wfbga package outline
? 2014 - 2015 microchip technology inc. ds00001719d-page 45 MEC1322 2.0 block overview this chapter provides an overview of the blocks in the MEC1322. the block diagram of the MEC1322 is shown in figure 2-1 . table 2-1 on page 46 lists address ranges for each of the blocks. figure 2-1: block diagram adc ch0-4 peci shared spi master pwm0 tach 0 pwm3 lpc rpm_pwm debug and test bc-link led control (x4) glue logic nreset _out, vcc1 _rst# vref_peci gpio vbat resources ps/2 ps/2 crystal osc pm1 acpi ec (x2) mbx 8042 kbc interfaces uart port92 pnp cfg executable sram vbat ram vbat regs. boot rom ring osc kb scan on-chip clocking pwm2 smb0 port 0 port 1 private spi master clock gen & dist timer 16-bit x4 timer 32-bit x2 hibernation timer wdt tach 1 smb1 port 0 smb2 port 0 smb3 port 0 ec_reg bank tfdp dma controller interrupt aggregater rtc emi ps/2 ps/2 pwm1 adc to pwm ec core floating point unit
MEC1322 ds00001719d-page 46 ? 2014 - 2015 microchip technology inc. table 2-1: block address ranges feature logical device no. (ldn) base address (hex) end of range (hex) instance emi/imap 0 400f0000 400f03ff 0 8042 emulation 6 400f0400 400f07ff acpi full duplex 3 400f0c00 400f0fff 0 acpi full duplex 4 400f1000 400f13ff 1 acpipm1 5 400f1400 400f17ff uart 7 400f1c00 400f1fff legacy (fast kb) 1 400f1800 400f1bff mailbox 9 400f2400 400f27ff rtc b 400f2c00 400f2dff global configuration 3f 400ffc00 400fffff lpc c 400f3000 400f33ff gpio 40081000 400817ff jtag 40080000 400800ff pcr 40080100 40080fff interrupts 4000c000 400c3fff dma 40002400 400027ff 16 bit timer 40000c00 40000c1f 0 16 bit timer 40000c20 40000c3f 1 16 bit timer 40000c40 40000c5f 2 16 bit timer 40000c60 40000c7f 3 32 bit timer 40000c80 40000c9f 4 32 bit timer 40000ca0 40000cbf 5 smb 4000ac00 4000afff 1 smb 4000b000 4000b3ff 2 smb 4000b400 4000b7ff 3 smb 40001800 40001bff 0
? 2014 - 2015 microchip technology inc. ds00001719d-page 47 MEC1322 table 2-1: block address ranges (continued) feature logical device no. (ldn) base address (hex) end of range (hex) instance 64 byte vbat ram 4000a800 4000abff vbat registers 4000a400 4000a7ff rpm fan 4000a000 4000a3ff keyscan 40009c00 40009fff hibernation timer 40009800 40009bff gp-spi 40009400 4000947f 0 gp-spi 40009480 400094ff 1 ps/2 40009000 4000903f 0 ps/2 40009040 4000907f 1 ps/2 40009080 400090bf 2 ps/2 400090c0 400090ff 3 adc 40007c00 40007c7f pwm 40005800 4000580f 0 pwm 40005810 4000581f 1 pwm 40005820 4000582f 2 pwm 40005830 4000583f 3 tach 40006000 4000600f 0 tach 40006010 4000601f 1 wdt 40000400 400007ff tfdp 40008c00 40008fff bc-link 4000bc00 4000bfff peci 40006400 400067ff b/b led 4000b800 4000b8ff 0 b/b led 4000b900 4000b9ff 1 b/b led 4000ba00 4000baff 2 b/b led 4000bb00 4000bbff 3 ec_reg_bank 4000fc00 4000fc1b data space sram 00118000 0011ffff code space sram 00100000 00117fff rom 00000000 00007fff
MEC1322 ds00001719d-page 48 ? 2014 - 2015 microchip technology inc. 3.0 power, clocks, and resets 3.1 introduction the power, clocks, and resets (pcr) chapter identifies all the power supplies, clock sources, and reset inputs to the chip and defines all the derived power, clock, and reset signals. in addition, this section identifies power, clock, and reset events that may be used to generate an interrupt event, as well as, the chip power management features . 3.2 references no references have been cited for this chapter. 3.3 interrupts the power, clocks, and resets logic generates no events 3.4 power 3.4.1 power sources table 3-1 lists the power supplies from which the MEC1322 draws current. these current values are defined in section 37.4, "power consumption," on page 395 . note 3-1 note on battery replacement: microchip recommend s removing all power sources to the device defined in table 3-1, "power source definitions" and all external voltage references defined in table 3-2, "voltage reference definitions" before removing and replacing the battery. in addition, upon removing the battery, ground the batt ery pin before replacing the battery. application note: battery circuit requirement: ? vcc0 must always be present if vcc1 is present. table 3-1: power source definitions power well nominal voltage description source vcc1 3.3v main battery pack supply power well. this is the ?always-on? supply. pin interface vbat (vcc0) ( note 3-1 ) 3.0v system battery back-up power well. this is the ?coin-cell? battery. pin interface note: the minimum rise/fall time requirement on vcc1 is 200us. note: the minimum rise time requirement on vbat is 100us.
? 2014 - 2015 microchip technology inc. ds00001719d-page 49 MEC1322 the following circuit is recommended to fulfill this requirement: figure 3-1: recommended battery circuit 3.4.2 voltage references table 3-2 lists the external voltage references to whic h the MEC1322 provides high impedance interfaces. note 3-2 the vref_peci does not have a power good signal associated with it. see vref buffer type definition in table 37-4, ?dc electrical characteristics,? on page 391 . 3.4.3 power good signals the power good timing and thresholds are defined in the section 38.1, "voltage thresholds and power good timing," on page 397 . table 3-2: voltage reference definitions power well nominal input voltage scaling ratio nominal monitored voltage description source vref_peci ( note 3-2 ) variable n/a variable processor voltage external voltage reference used to scale processor interface signals pin interface table 3-3: power good signal definitions power good signal description source vcc1gd vcc1gd is an internal power good signal used to indicate when the vcc1 rail is on and stable. vcc1gd is asserted following a delay after the vcc1 power well exceeds its preset voltage threshold. vcc1gd is de-asserted as soon as this voltage drops below this thresh- old. pwrgd pwrgd is used to indicate when the main power rail voltage is on and stable. vcc_pwrgd input pin vcc0 to ec to ec as vcc1 3.0v nom coin cell ?rtc? rail (pch, system) + (schottky diode) (schottky diode) 3.3v nom, from ac source or battery pack () possible current limiter (1k typ.) 3.3v max with vcc1 = 0v, 3.6v max with vcc1 = vbat
MEC1322 ds00001719d-page 50 ? 2014 - 2015 microchip technology inc. 3.4.4 system po wer sequencing the following table defines the behavior of the power sources in each of the defined acpi power states. note 3-3 vcc1 power supply is always on while the battery pack or ac power is applied to the system. note 3-4 this device requires that the vbat power is on when the vcc1 power supply is on. external circuitry, a diode isolation circuit, is implemented on the mo therboard to extend the battery life. this external circuitry ensures the vbat pin will derive power from the vcc1 power well wh en it is on. therefore, the vbat supply will never appear to be off when the vcc1 rail is on. see application note: on page 48 . 3.5 clocks the following section defines the MEC1322 clocks that are genera ted or referenced. table 3-4: typical power supplies vs. acpi power states supply name acpi power state description s0 (full on) s1 (pos) s3 (str) s4 (std) s5 (soft off) g3 (mech off) vcc1 on on on on on off MEC1322 ?always-on? supply. ( note 3-3 ) vbat (vcc0) on on on on ( note 3-4 ) on ( note 3-4 ) on ( note 3-4 ) MEC1322 battery back-up supply table 3-5: clock definitions clock name frequency description source susclk 32.768 khz 32.768 khz suspend well clock source is a single-ended input that is an accurate 32.768khz clock. ( note 3-5 ) pin interface (xtal2) 32.768 khz crystal oscillator 32.768 khz a 32.768 khz parallel resonant crys- tal connected between the xtal1 and xtal2 pins. pin interface (xtal1 and xtal2) 48 mhz ring oscillator 48mhz the 48 mhz ring oscillator is a high- accuracy, low power, low start-up latency 48 mhz ring oscillator. enabled by vcc1 power ( note 3-6 ). may be stopped by chip power man- agement features . 24mhz_clk 24 mhz derived clock for uart 48 mhz ring oscillator 16mhz_clk 16mhz derived clock for smbus controller 48 mhz ring oscillator 1.8432mhz_clk 1.843 mhz derived clock for uart 48 mhz ring oscillator 100khz_clk 100 khz derived for several blocks in the ec subsystem, including, but not limited to, pwm, tach. 48 mhz ring oscillator 32khz_clk 32.768 khz internal 32khz clock domain pin interface: xtal2: 32khz crystal input/ single- ended clock source input pin. xtal1: 32khz crystal output the xosel bit configures the source of this clock domain as either a sin- gle-ended 32.768 khz clock input ( susclk ) or the 32.768 khz crystal oscillator ( note 3-7 ). if neither of these is available, this clock domain is derived from the 48 mhz ring oscillator .
? 2014 - 2015 microchip technology inc. ds00001719d-page 51 MEC1322 note 3-5 the chipset will not produce a valid 32khz clock unt il about 5 ms (pch) or 110 ms (ich) after the deassertion of rsmrst#. see chipset specification for the actual timing. note 3-6 the 48 mhz ring oscillator is reset by vcc1gd . note 3-7 the clock enable register contains the xosel bit and the 32k_en bit (see section 4.7.2, "clock enable register," on page 73 ). the 32.768 khz oscillator provides a stable timebase for the 48 mhz ring oscillator as well as the clock source for the 32khz clock domain. after vbat por there is a 500ms max time for the 48 mhz ring oscillator to become accurate. 3.5.1 32khz clock switching the 32khz clock switchi ng logic switches the clock source of the 32 khz clock domain to be either the single-ended 32.768 khz clock input or the 32.768 khz crystal oscillator . if neither of these is available, this clock domain is derived from the 48 mhz ring oscillator . following a vbat_por , the xosel bit and the 32k_en bit in the clock enable register are programmed to configure the source of this clock domain. if the single-ended 32.768 khz clock input is configured as the source of the 32khz clock domain, then following a vcc1_reset , the time for this clock domain to become accurate at 32.768khz after the susclk input goes active is 100us (max). if the 32.768 khz crystal oscillator is configured as the source of th e 32khz clock domain, then following a vcc1_re- set , there is 100us (max) delay time for this cl ock domain to become accurate at 32.768khz. 3.5.2 clock domains vs. acpi power states table 3-6, "typical MEC1322 clocks vs. acpi power states" shows the relationship between acpi power states and MEC1322 clock domains: table 3-6: typical MEC1322 clocks vs. acpi power states clock name acpi power state description s0 (full on) s1 (pos) s3 (str) s4 (std) s5 (soft off) g3 (mech off) susclk on on on on on off this clock is the system suspend clock source. ( note 3-5 ). 32.768 khz crystal oscillator on on on on on on this clock is generated from a 32.768 khz paral- lel resonant crystal con- nected between the xtal1 and xtal2 pins. 32khz_clk on on on on on on/ off this clock domain is gen- erated from the 32khz clock input (susclk) when available or the crystal oscillator pins. otherwise it is generated internally from the 48 mhz ring oscillator .
MEC1322 ds00001719d-page 52 ? 2014 - 2015 microchip technology inc. 3.6 resets 48 mhz ring oscilla- tor on on on on on off this clock is powered by the MEC1322 suspend supply (vcc1) but may start and stop as described in section 3.7, "chip power manage- ment features," on page 54 (see also note 3-3 ). table 3-7: definition of reset signals reset description source vbat_por internal vbat reset signal. this signal is used to reset vbat powered registers. vbat_por is a pulse that is asserted at the ris- ing edge of vcc1gd if the vbat voltage is below a nominal 1.25v. vbat_por is also asserted as a level if, while vcc1gd is not asserted (?0?), the coin cell is replaced with a new cell that delivers at least a nominal 1.25v. in this latter case vbat_por is de-asserted when vcc1gd is asserted. no action is taken if the coin cell is replaced, or if the vbat voltage falls below 1.25 v nominal, while vcc1gd is asserted. vcc1_reset internal vcc1 reset signal. this signal is used to reset vcc1 powered registers. vcc1_reset is asserted when vcc1gd is low and is deasserted when vcc1gd is high. the vcc1_rst# pin asserted as input will also cause a vcc1_reset. a wdt_reset event will also cause a vcc1_reset assertion. pci reset# system reset signal connected to the lpc lreset# pin. pin interface, lreset# pin. see note 3-8 . nsio_reset performs a reset when vcc is turned off or when the system host resets the lpc interface. nsio_reset is a signal that is asserted if vcc1gd is low, pwrgd is low, or pci reset# is asserted low and may be deasserted when these three signals are all high. the ire- set_out bit controls the deassertion of nsio_reset . see note 3-8 . a wdt_reset event will also cause an nsio_reset assertion. table 3-6: typical MEC1322 clocks vs. acpi power states (continued) clock name acpi power state description s0 (full on) s1 (pos) s3 (str) s4 (std) s5 (soft off) g3 (mech off)
? 2014 - 2015 microchip technology inc. ds00001719d-page 53 MEC1322 note 3-8 if the lreset# pin is assigned to the gpio functi on rather than lreset#, the internal lreset# signal is gated low, and therefore the nreset _out function will not operate properly. 3.6.1 integrated vcc1 powe r on reset (vcc1_rst#) the vcc1_rst# pin is used to control the power up sequenc e for external devices. the vcc1_rst# timing is shown in section 38.1.1, "vcc1_rst# timing," on page 397 . the following summarizes the operation of the vcc1_rst# signal. ? the vcc1_rst# pin is both a rese t input and an output to the system. ? the vcc1_rst# output provides a por reset during power up transition ? the vcc1_rst# output has ou tput pin glitch protection ? the vcc1_rst# output stretches an external driven reset by 1ms (typ). ? the vcc1_rst# input detects an externally driven reset and places the MEC1322 into a vcc1 por state. the vcc1_rst# is an open drain pin. an external pull- up is required for the vcc1_rst# signal to be high. the following sequence illustrates the interaction between t he internally and externally driven assertion of vcc1_rst#: 1. the integrated vcc1 power on reset generator insu res vcc1_rst# is driven low during a vcc1 por from vcc1 = 1v to 2.4v (typ) without glitches. 2. the vcc1_rst# pin is driven low during the por tran sition until vcc1 > 2.4v (typ) and then the vcc1_rst# pin remains low afterwards for 1ms (typ) delay window. the vcc1_rst# input is not examined during the 1ms (typ) delay window; ther efore, the system input and/or the external pi n termination may be modified (i.e. drive it low, let it float, etc.) - the vcc1_rst# input is not examined during the por tr ansition while vcc1 < 2.4v (typ); therefore, the system input to the vcc1_rst # pin may modify the output termi nation (i.e. drive it lo w, let it float, etc.) 3. the vcc1_rst# pin is driven low during the 1ms (typ) delay window. the MEC1322 is in the vcc1_por state during this time. 4. after the 1ms (typ) window, the vcc1_rst# pin open dr ain output from the mec132 2 is not driven/released. the strap option pins are sampled at this time. 5. the MEC1322 will remain in the vcc1 por for 2.65us (min) after the vcc1_rst# pin is released the vcc1_rst# input pin is ignored during this time. 6. the vcc1_rst# pin input is sampled at 2.65u s (min) after the vcc1_rst# pin is released. - if the vcc1_rst# pin is high when sampled, then the ec starts executing. - if the vcc1_rst# pin is low when sampled, the pin is being driven externally (i.e., the system is forcing a reset): - the vcc1_rst# pin is driven low for 1ms (typ), then sampled at 2.65us (min) after the vcc1_rst# pin is released (see step 3 ). wdt_reset internal wdt reset si gnal. this signal resets vcc1 powered registers with the exception of the wdt event count register. note that the glitch protect circuits do not activate on a wdt reset. wdt_reset does not reset vbat registers or logic. a wdt_reset is asserted by a wdt event . note: this event is indicated by the wdt bit in the power-fail and reset sta- tus register ec_proc_ reset internal reset signal to reset the processor in the ec subsystem. an ec_proc_ reset is a stretched version of the vcc1_reset . this reset asserts at the same time that vcc1_reset asserts and is held asserted for 1ms after the vcc1_reset deasserts. note: the external pull-up on the vcc1_rst# pi n must be chosen to meet the timing in table 38-2, ?vcc1_rst# rise time,? on page 397 . table 3-7: definition of reset signals (continued) reset description source
MEC1322 ds00001719d-page 54 ? 2014 - 2015 microchip technology inc. note 1: the minimum low pulse provided to initiate reset = 20ns. 2: there is no glitch protection or noise filtering (i.e. a vary narrow noise pulse cause a reset). 3.7 chip power management features this device is designed to always operate in its lowest po wer state during normal operation. in addition, this device offers additional programmable options to put in dividual logical blocks to sleep as defined in section 3.7.1, "block low power modes," on page 54 . 3.7.1 block low power modes all power related control signals are generated and monitored centrally in the chip?s power, clocks, and resets (pcr) block. the power manager of the pcr block uses a sleep inte rface to communicate with all the blocks. the sleep inter- face consists of three signals: ? sleep_en (request to sleep the block) is generated by the pcr block. a gr oup of sleep_en signals are gener- ated for every clock segment. each group consists of a sleep_en signal for every block in that clock segment. ? clk_req (request clock on) is generated by every block. they are grouped by blocks on the same clock segment. the pcr monitors these signals to see when it can gate off clocks. ? reset_en (reset on sleep) bits determine if the block (including regi sters) will be reset when it enters sleep mode. a block can always drive clk_req low synchronously, but it must drive it high asynchronously since its internal clocks are gated and it has to assume that the clock input itself is gated. therefore the block can onl y drive clk_req high as a result of a register access or some other input signal. the following table defines a block?s power management protocol: a wake event clears all sleep enable bits momentarily, and then returns the sleep enable bits back to their original state. the block that needs to respond to the wake event will do so. see section 15.8.1, "wake ge neration," on page 194 . the sleep enable, clock required and reset enable registers are defined in section 3.8, "ec-only registers," on page 55 . power state sleep_en clk_req description normal operation low low block is idle and not requesting clocks. the block gates its own internal clock. normal operation low high block is no t idle and requests clocks. request sleep rising edge low block is idle and enters sleep mode immediately. the block gates its own internal clock. the block cannot request clocks again until sleep_en goes low. request sleep rising edge high then low block is not idle and will st op requesting clocks and enter sleep when it finishes what it is doing. this delay is block specific, but should be less than 1 ms. the block gates its own internal clock. after drivin g clk_req low, the block cannot request clocks again until sleep_en goes low. register access x high register access to a block is always available regardless of sleep_en. therefore the block u ngates its internal clock and drives clk_req high during the access. the block will regate its internal clock and drive clk_req low when the access is done.
? 2014 - 2015 microchip technology inc. ds00001719d-page 55 MEC1322 3.8 ec-only registers note 3-9 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. 3.9 sleep enable and clock required registers the following are the sleep enable and clock required registers for the MEC1322. 3.9.1 chip sleep enable re gister (chip_slp_en) table 3-8: ec-only register base address table block instance instance number host address space base address ( note 3-9 ) pcr 0 ec 32-bit internal address space 4008_0100h table 3-9: power, clocks and reset vcc1-powered registers summary offset register name 00h chip sleep enable register (chip_slp_en) 04h chip clock required status registers (chip_clk_req_sts) 08h ec sleep enable re gister (ec_slp_en) 0ch ec clock required status registers (ec_clk_req_sts) 10h host sleep enable register (host_slp_en) 14h host clock required status registers (host_clk_req) 18h system sleep control re gister (sys_slp_cntrl) 20h processor clock control register (proc_clk_cntrl) 24h ec sleep enable 2 re gister (ec_slp_en2) 28h ec clock required 2 status register (ec_clk_req2_sts) 2ch slow clock control register (slow_clk_cntrl) 30h oscillator id register (chip_osc_id) 34h pcr chip sub-system power rese t status (chip_pwr_rst_sts) 38h chip reset enable register (chip_rst_en) 3ch host reset enable register (host_rst_en) 40h ec reset enable register (ec_rst_en) 44h ec reset enable 2 register (ec_rst_en2) 48h power reset control (pwr_rst_ctrl) register note: all register addresses are naturally aligned on 32-bit boundaries. offsets for registers that are smaller than 32 bits are reserved and must not be used for any other purpose. offset 00h bits description type default reset event 31:2 reserved res 1 mchp reserved ( note 3-10 )r/w0h vcc1_r eset 0 mchp reserved ( note 3-10 )r/w0h vcc1_r eset
MEC1322 ds00001719d-page 56 ? 2014 - 2015 microchip technology inc. note 3-10 mchp reserved bits in the sleep_en registers must be written to 1 in order for the chip to be put into sleep mode. 3.9.2 chip clock required status registers (chip_clk_req_sts) 3.9.3 ec sleep enable register (ec_slp_en) offset 04h bits description type default reset event 31:2 reserved res 1 mchp reserved r 0h vcc1_r eset 0 mchp reserved r - vcc1_r eset offset 08h bits description type default reset event 31 timer16_1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-11 on page 57 . r/w 0h vcc1_r eset 30 timer16_0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-11 on page 57 . r/w 0h vcc1_r eset 29 ec_reg_bank sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 28:23 reserved res 22 pwm3 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 21 pwm2 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 20 pwm1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 19:12 reserved res 11 tach1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 10 smb0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 9 wdt sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 57 MEC1322 note 3-11 the basic timers in this device have an auto-reload mode. when this mode is selected, the block's clk_req equation is always asserted, which will prevent the device from gating its clock tree and going to sleep. when the firmware intends to put the devi ce to sleep, none of the timers should be in auto- reload mode. alternatively, use the timer's halt function inside the control register to stop the timer in auto-reload mode so it can go to sleep. 3.9.4 ec clock required status registers (ec_clk_req_sts) 8 processor sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 7 tfdp sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 6 dma sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 5 pmc sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 4 pwm0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 3 reserved res 2 tach0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 1 peci sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 0 int sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset offset 0ch bits description type default reset event 31 timer16_1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 30 timer16_0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 29 ec_reg_bank clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 28:23 reserved res offset 08h bits description type default reset event
MEC1322 ds00001719d-page 58 ? 2014 - 2015 microchip technology inc. 22 pwm3 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 21 pwm2 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 20 pwm1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 19:12 reserved res 11 tach1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 10 smb0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 9 wdt clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 8 processor clock required 0: block does not need clocks. 1: block requires clocks. r1h vcc1_r eset 7 tfdp clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 6 dma clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 5 pmc clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 4 pwm0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 3 reserved res 2 tach0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 1 peci clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 0 int clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset offset 0ch bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 59 MEC1322 3.9.5 host sleep enable re gister (host_slp_en) 3.9.6 host clock required stat us registers (host_clk_req) offset 10h bits description type default reset event 31:19 reserved res 18 rtc sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 17 reserved res 16 8042em sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 15 acpi pm1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 14 acpi ec 1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 13 acpi ec 0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 12 glbl_cfg 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 11:2 reserved res 1 uart 0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 0 lpc sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset offset 14h bits description type default reset event 31:19 reserved res 18 rtc clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 17 reserved res 16 8042em clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 15 acpi pm1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset
MEC1322 ds00001719d-page 60 ? 2014 - 2015 microchip technology inc. 3.9.7 system sleep control register ( sys_slp_cntrl) the system sleep states shown in table 3-10 and determined by the bits in this register, are only entered if all blocks are sleeping; that is, if the sleep enable bits ar e set for all blocks and no clocks are required. 14 acpi ec 1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 13 acpi ec 0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 12 glbl_cfg clock required 0: block does not need clocks. 1: block requires clocks. r- vcc1_r eset 11:2 reserved res 1 uart 0 clock required 0: block does not need clocks. 1: block requires clocks. r- vcc1_r eset 0 lpc clock required 0: block does not need clocks. 1: block requires clocks. r- vcc1_r eset offset 18h bits description type default reset event 31:3 reserved res 2 core regulator standby 0: keep regulator fully operational when sleeping. 1: standby the regulator when sleeping. allows enough power for chip static operation for memory retention. r/w 0h vcc1_r eset 1 ring oscillator output gate 0: keep rosc ungated when sleeping. 1: gate the rosc output when sleeping. r/w 0h vcc1_r eset 0 ring oscillator power down 0: keep rosc operating when sleeping. 1: disable rosc when sleeping. clocks will start on wakeup, but there is a clock lock latency penalty. r/w 0h vcc1_r eset offset 14h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 61 MEC1322 note 3-12 this is the latency follo wing a wake event until the 48 mhz ring oscillator is locked and clocking the system. 3.9.8 processor cloc k control register (proc_clk_cntrl) 3.9.9 ec sleep enable 2 register (ec_slp_en2) table 3-10: system sleep control bit encoding d2 d1 d0 wake latency (typ) description 0 0 0 0 the core regulator and the ring oscillator remain powered and run- ning during sleep cycles (system heavy sleep 1) (default) 0 1 0 0 the core regulator remains powered and the ring oscillator is running but gated during sleep cycles (system heavy sleep 2) 0 x 1 200us ( note 3-12 ) the core regulator remains powered and the ring oscillator is powered down during sleep cycles (system heavy sleep 3) 1 x 1 1ms the core regulator is suspended and the ring oscillator is powered down during sleep cycles. (system deepest sleep) offset 20h bits description type default reset event 31:8 reserved res 7:0 processor clock divide value 1: divide 48 mhz ring oscillator by 1. 4: divide 48 mhz ring oscillator by 4. 16: divide 48 mhz ring oscillator by 16. 48: divide 48 mhz ring oscillator by 48. no other values are supported. r/w 4h vcc1_r eset offset 24h bits description type default reset event 31:29 reserved res 28 mchp reserved ( note 3-10 )r/w0h vcc1_r eset 27 mchp reserved ( note 3-10 )r/w0h vcc1_r eset 26 mchp reserved ( note 3-10 )r/w0h vcc1_r eset 25 led3 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 24 timer32_1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-11 on page 57 . r/w 0h vcc1_r eset 23 timer32_0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-11 on page 57 . r/w 0h vcc1_r eset
MEC1322 ds00001719d-page 62 ? 2014 - 2015 microchip technology inc. 22 timer16_3 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-11 on page 57 . r/w 0h vcc1_r eset 21 timer16_2_sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-11 on page 57 . r/w 0h vcc1_r eset 20 spi1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 19 bcm sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 18 led2 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 17 led1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 16 led0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 15 smb3 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 14 smb2 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 13 smb1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 12 rpm-pwm sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 11 keyscan sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 10 htimer sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 9 spi0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 8 ps2_3 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-14 . r/w 0h vcc1_r eset offset 24h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 63 MEC1322 note 3-13 the adc vref must be powered down in order to get the lowest deep sleep current. the adc vref power down bit, adc_vref _pd_ref is in the ec subsys tem registers adc vref pd on page 381. note 3-14 the ps2 block will only sleep while the ps2 is disa bled or in rx mode with no traffic on the bus. 3.9.10 ec clock required 2 stat us register (ec_clk_req2_sts) 7 ps2_2 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-14 . r/w 0h vcc1_r eset 6 ps2_1 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-14 . r/w 0h vcc1_r eset 5 ps2_0 sleep enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. see note 3-14 . r/w 0h vcc1_r eset 4 mchp reserved ( note 3-10 ) r/w 0h vcc1_r eset 3 adc sleep enable ( note 3-13 ) 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 2:0 reserved r offset 28h bits description type default reset event 31:29 reserved res 28 mchp reserved r 0h vcc1_r eset 27 mchp reserved r 0h vcc1_r eset 26 mchp reserved r 0h vcc1_r eset 25 led3 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 24 timer32_1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 23 timer32_0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset offset 24h bits description type default reset event
MEC1322 ds00001719d-page 64 ? 2014 - 2015 microchip technology inc. 22 timer16_3 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 21 timer16_2_clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 20 spi1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 19 bcm clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 18 led2 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 17 led1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 16 led0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 15 smb3 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 14 smb2 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 13 smb1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 12 rpm-pwm clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 11 keyscan clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 10 htimer clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 9 spi0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 8 ps2_3 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 7 ps2_2 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset offset 28h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 65 MEC1322 3.9.11 slow clock control register (slow_clk_cntrl) 3.9.12 oscillator id register (chip_osc_id) 6 ps2_1 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 5 ps2_0 clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 4 mchp reserved r0h vcc1_r eset 3 adc clock required 0: block does not need clocks. 1: block requires clocks. r0h vcc1_r eset 2:0 reserved res offset 2ch bits description type default reset event 31:10 reserved res 9:0 slow clock (100 khz) divide value configures the 100khz_clk . 0: clock off n: divide by n. note: the default setting is for 100 khz. r/w 1e0h vcc1_r eset offset 30h bits description type default reset event 31:9 reserved res 8osc_lock oscillator lock status r0h vcc1_r eset 7:0 mchp reserved r n/a vcc1_r eset offset 28h bits description type default reset event
MEC1322 ds00001719d-page 66 ? 2014 - 2015 microchip technology inc. 3.9.13 pcr chip sub-system power r eset status (chip_pwr_rst_sts) note 3-15 this read-only status bit always reflects the current status of the event and is not affected by any reset events. offset 34h bits description type default reset event 31:12 reserved res 11 pciclk_active this bit monitors the state of the pci clock input. this status bit detects edges on the clock input but does not validate the frequency. 0: the 33mhz pci clock input is not present. 1: the 33mhz pci clock is present. r- vcc1_r eset 10 32k_active this bit monitors the state of the 32k clock input. this status bit detects edges on the clock input but does not validate the frequency. 0: the 32k clock input is not present. the internal 32k clock is derived from the ring oscillator 1: the 32k clock input is present. the internal 32k clock is derived from the pin and the ring oscillator is synchronized to the external 32k clock. r- vcc1_r eset 9:7 reserved res 6 vcc1 reset status indicates the status of vcc1_reset . 0 = no reset occurred since the last time this bit was cleared. 1 = a reset occurred. note: the bit will not clear if a write 1 is attempted at the same time that a vcc1_rst_n occu rs, this way a reset event is never missed. r/wc 1h vcc1_r eset 5 vbat reset status indicates the status of vbat_por . 0 = no reset occurred while vcc1 was off or since the last time this bit was cleared. 1 = a reset occurred. note: the bit will not clear if a write 1 is attempted at the same time that a vbat_rst_n occurs, this way a reset event is never missed. r/wc - vcc1_r eset 4 reserved res 3 sio_reset status indicates the status of nsio_reset . 0 = reset active. 1 = reset not active. rxh note 3- 15 2 vcc reset status indicates the status of pwrgd . 0 = reset active ( pwrgd not asserted). 1 = reset not active ( pwrgd asserted). rxh note 3- 15 1:0 reserved res
? 2014 - 2015 microchip technology inc. ds00001719d-page 67 MEC1322 3.9.14 chip reset enable re gister (chip_rst_en) 3.9.15 host reset enable register (host_rst_en) offset 38h bits description type default reset event 31:2 reserved res 1 mchp reserved r 0h vcc1_r eset 0 mchp reserved r/w 0h vcc1_r eset note: if a block is configured such that it is to be reset when it goes to sleep, then registers within the block may not be writable when the block is asleep. offset 3ch bits description type default reset event 31:19 reserved res 18 rtc reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 17 reserved res 16 8042em reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 15 acpi pm1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 14 acpi ec 1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 13 acpi ec 0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 12 glbl_cfg reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 11:2 reserved res 1 uart 0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 0 lpc reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset note: if a block is configured such that it is to be reset when it goes to sleep, then registers within the block may not be writable when the block is asleep.
MEC1322 ds00001719d-page 68 ? 2014 - 2015 microchip technology inc. 3.9.16 ec reset enable register (ec_rst_en) offset 40h bits description type default reset event 31 timer16_1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 30 timer16_0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 29 ec_reg_bank reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 28:23 reserved res 22 pwm3 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 21 pwm2 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 20 pwm1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 19:12 reserved res 11 tach1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 10 smb0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 9 wdt reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 8 processor sleep enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 7 tfdp reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 6 dma reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 5 pmc reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 4 pwm0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 69 MEC1322 3.9.17 ec reset enable 2 register (ec_rst_en2) 3 reserved res 2 tach0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 1 peci reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 0 int reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset note: if a block is configured such that it is to be reset when it goes to sleep, then registers within the block may not be writable when the block is asleep. offset 44h bits description type default reset event 31:29 reserved res 28 mchp reserved r/w 0h vcc1_r eset 27 mchp reserved r/w 0h vcc1_r eset 26 mchp reserved r/w 0h vcc1_r eset 25 led3 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 24 timer32_1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 23 timer32_0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 22 timer16_3 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 21 timer16_2_reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 20 spi1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset offset 40h bits description type default reset event
MEC1322 ds00001719d-page 70 ? 2014 - 2015 microchip technology inc. 19 bcm reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 18 led2 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 17 led1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 16 led0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 15 smb3 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 14 smb2 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 13 smb1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 12 rpm-pwm reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 11 keyscan reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 10 htimer reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 9 spi0 reset enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. r/w 0h vcc1_r eset 8 ps2_3 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 7 ps2_2 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 6 ps2_1 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 5 ps2_0 reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 4 mchp reserved r/w 0h vcc1_r eset offset 44h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 71 MEC1322 3.9.18 power reset control (pwr_rst _ctrl) register 3 adc reset enable 0: block will not be reset on sleep. 1: block will be reset on sleep. r/w 0h vcc1_r eset 2:0 reserved res note: if a block is configured such that it is to be reset when it goes to sleep, then registers within the block may not be writable when the block is asleep. offset 48h bits description type default reset event 31:1 reserved res 0 ireset_out the ireset_out bit is used by fi rmware to control the internal nsio_reset signal function and the ex ternal nreset_out pin. the external pin nreset_o ut is always driven by nsio_reset . firmware can program the state of ireset_out e xcept when the vcc pwrgd bit is not asserted (?0?), in which case ireset_out is ?don?t care? and nsio_reset is asserted (?0?) ( table 3-11: ). the internal nsio_reset signal is asserted when ireset_out is asserted even if the nreset_out pi n is configured as an alternate function. the ireset_out bit must be cleared to take the host out of reset. r/w 1h vcc1_r eset table 3-11: ireset_out bit behavior vcc pwrgd ireset_out nsio_reset & nreset_out description 0 x 0 (asserted) the ireset_out bit does not affect the state of nsio_reset when vcc pwrgd is not asserted. 1 1 0 (asserted) the ireset_out bit can only be written by firmware when vcc pwrgd is asserted. 01 (not asserted) offset 44h bits description type default reset event
MEC1322 ds00001719d-page 72 ? 2014 - 2015 microchip technology inc. 4.0 vbat register bank 4.1 introduction this chapter defines a bank of registers powered by vbat . 4.2 interface this block is designed to be accessed internal ly by the ec via the register interface. 4.3 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 4.3.1 power domains 4.3.2 clock inputs this block does not require any special clock inputs. al l register accesses are synchronized to the host clock. 4.3.3 resets 4.4 interrupts 4.5 low power modes the vbat register bank is designed to always operate in the lowest power consumption state. 4.6 description the vbat register bank block is a bl ock implemented for aggregating miscella neous battery-backed registers required the host and by the embedded controller (ec) subsystem that are not unique to a block implemented in the ec sub- system. 4.7 ec-only registers note 4-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. table 4-1: power sources name description vbat the vbat register bank are all implemented on this single power domain. table 4-2: reset signals name description vbat_por this reset signal, which is an input to this block, resets all the logic and registers to their initial default state. table 4-3: interrupt signals name description pfr_status this interrupt signal from t he power-fail and reset status register indicates vbat rst and wdt events. table 4-4: ec-only register base address table block instance instance number host address space base address ( note 4-1 ) vbat_reg_bank 0 ec 32-bit internal address space 4000a400h
? 2014 - 2015 microchip technology inc. ds00001719d-page 73 MEC1322 4.7.1 power-fail and reset status register the power-fail and reset status register collects and retains the vbat rst and wdt event status when vcc1 is unpowered. 4.7.2 clock enable register application note: the xosel bit should be correctly conf igured by firmware before the 32k_en bit is assserted. table 4-5: runtime register summary offset register name 00h power-fail and reset status register 04h mchp reserved 08h clock enable register address 00h bits description type default reset event 7 vbat_rst the vbat rst bit is set to ?1? by hardware when a vbat_por is detected. this is the register default value. to clear vbat rst ec firmware must write a ?1? to this bit; writing a ?0? to vbat rst has no affect. r/wc 1 vbat_p or 6 reserved res - - 5 wdt the wdt bit is asserted (?1?) following a watch-dog timer forced reset ( wdt event ). to clear the wdt bit ec firmware must write a ?1? to this bit; writing a ?0? to the wdt bit has no affect. r/wc 0 vbat_p or 4:1 reserved res - - 0 det32k_in 0 = no clock detected on the xtal[1:2] pins. 1= clock detected on the xtal[1:2] pins. rx vbat_p or address 08h bits description type default reset event 31:2 reserved res - - 1 32k_en this bit controls the 32.768 khz crystal oscillator as defined in table 4-6: . r/w 0b vbat_p or 0 xosel this bit controls whether a crystal or single ended clock source is used. 1= the 32.768 khz crystal oscillator is driven by a single-ended 32.768 khz clock source connected to the xtal2 pin. 0= the 32.768 khz crystal oscillato r requires a 32.768 khz parallel resonant crystal connected between the xtal1 and xtal2 pins (default). r/w 0b vbat_p or
MEC1322 ds00001719d-page 74 ? 2014 - 2015 microchip technology inc. note 4-2 the 48mhz ring oscillator must not stop before 40 s min after the 32k_en bit is asserted. table 4-6: 32k_en bit 32k_en 32.768 khz crystal oscillator description 0 off vbat_por default. 1 on the 32.768 khz crystal oscillator can only be enabled by firmware ( note 4-2 ).
? 2014 - 2015 microchip technology inc. ds00001719d-page 75 MEC1322 5.0 lpc interface 5.1 introduction the intel? low pin count (lpc) interface is the lpc interf ace used by the system host to configure the chip and com- municate with the logical devices implemented in the design through a series of read/write registers. register access is accomplished throu gh the lpc transfer cycles defined in table 5-8, "lpc cycle types supported" . the logical devices implemented in the design are identified in table 5-16, ?i/o base address registers,? on page 92 . the base address registers allow any logical device?s runtime registers to be relocated in lpc i/o space. all chip con- figuration registers for the device are accessed indirectly through th e lpc i/o configuration port (see section 5.8.3, "configuration port," on page 83 ). lpc memory cycles may also be used to access the base address registers of certain devices. 5.2 references ? intel? low pin count (lpc) interface specification, v1.1 ? pci local bus specification, rev. 2.2 ? serial irq specification for pci systems version 6.0. ? pci mobile design guide rev 1.0 5.3 terminology this table defines specialized terms localized to this feature. table 5-1: terminology term definition system host refers to the external cpu that co mmunicates with this device via the lpc interface. logical devices logical devices are lpc accessible features that are alloca ted a base address and range in lpc i/o address space runtime register runtime registers ar e register that are directly i/o accessible by the system host via the lpc interface. these registers are defined in section 5.10, "runt ime registers," on page 93 . configuration registers registers that are only accessible in config_mod e. these register s are defined in section 5.9, "lpc configur ation registers," on page 88 . ec_only registers registers that are not accessible by the system host. they are only accessible by an internal embedded controller. these registers are defined in section 5.11, "ec-only registers," on page 94 .
MEC1322 ds00001719d-page 76 ? 2014 - 2015 microchip technology inc. 5.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 5.4.1 signal description figure 5-1: block diagram of lpc interface cont roller with clkrun# support table 5-2: signal description table name direction description lad0 input/output bit[0] of the lpc multiplexed command, address, and data bus. lad1 input/output bit[1] of the lpc multiplexed command, address, and data bus. lad2 input/output bit[2] of the lpc multiplexed command, address, and data bus. lad3 input/output bit[3] of the lpc multiplexed command, address, and data bus. serirq lad0 lad1 lad2 lad3 lframe# lreset# lclk lpc interface (logical device ch) lpc controller serial irq state machine interface to configuration registers configuration port clkrun# lpc config registers lpc regis- ters (runtime, ec-only) interface to logical device register
? 2014 - 2015 microchip technology inc. ds00001719d-page 77 MEC1322 5.4.2 register interfaces the registers defined for the lpc interface block are accessible by the va rious hosts as indicated in section 5.9, "lpc configuration registers" , section 5.11, "ec-only registers" and section 5.10, "runtime registers" . 5.5 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 5.5.1 power domains 5.5.2 clock inputs 5.5.3 resets the following table defines the effective reset state that result from the combination of these three reset signals. lframe# input active low signal indicates start of new cycle and termina- tion of broken cycle. lreset# input active low signal used as lpc interface reset. same as pci reset on host. note: lreset# is typically connected to the host pci reset (pcirst#) signal. lclk input pci clock input (pci_clk) serirq input/output serial irq pin used with the lclk signal to transfer inter- rupts to the host. clkrun# open-drain output clock control for lclk table 5-3: power sources name description vcc1 the lpc interface block and registers are powered by vcc1 . table 5-4: clock inputs name description lclk this lpc interface has a single clock input, called lclk . note: the pci_clk input to lclk can run at 19.2mhz to 33mhz. when the pci_clk input frequency is from 19.2mhz (including 24mhz) to 33mhz the handshake bit in the ec clock control register must be set to a ?1? to capture lpc transactions properly. see section 5.11.4, "ec clock control register," on page 96 . table 5-5: reset signals name description vcc1_reset power on reset to the block. this si gnal resets all the register and logic in this block to its default state. nsio_reset this signal is used to indicate when the main power rail in the system is reset. the lpc interface is operationa l when main power is present. this signal is used to reset selected registers as defined in the register interfaces descriptions. lreset# the lreset# signal comes from the lpc pin interface. this signal is defined in the intel? low pin count (lpc) interface specification, v1.1 . table 5-2: signal description table (continued) name direction description
MEC1322 ds00001719d-page 78 ? 2014 - 2015 microchip technology inc. note 5-1 the ec can determine the state of the lreset# input using registers in lpc bus monitor register on page 95 . note 5-2 vcc1_reset is asserted when vcc1 is turned off and is released after vcc1 is turned on. the vcc1_reset will be released before the system host is expected to attempt communication over the lpc interface. note 5-3 see the individual register descriptions to determine which registers are effected by nsio_reset . note 5-4 the lpc interface will be ready to receive a new transaction when lreset# is deasserted. see the individual register descriptions to determine which registers are effected by this reset. in system, the lpc interface is required to be operational in acpi sleep states s0 - s2. when the system enters sleep states s3 - s5 the lpc interface must tristate its output s. the following table shows the behavior of lpc output and input/output signals under reset conditions. 5.6 interrupts this section defines the interrupt sources generated from this block. 5.7 low power modes the lpc controller may be pu t into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. the lpc block has implemented an ec clock control register to determine how the internal clocks are effected by the supported low power modes. see section 5.11.4, "ec clock control register," on page 96 for a description of these options. 5.8 description this lpc controller is compliant with the intel? low pin count (lpc) in terface specification, v1.1 . section 5.8.1, "lpc controller description" further clarifies which lpc in terface features have been im plemented and qualifies any system specific requirements. table 5-6: lpc interface block reset states vcc1_reset ( note 5-2 ) lreset# ( note 5-1 , note 5-4 ) nsio_reset ( note 5-3 ) reset state asserted x x resets all registers and logic deasserted asserted x resets se lected registers and logic deasserted asserted resets selected registers deasserted nothing is in reset note: see section 5.8.1.3, "lpc clock run," on page 80 page 157 for lpc protocol dependent pin state transi- tions requirements. table 5-7: lpc interface signals behavior on reset pins vcc1_reset nsio_reset lreset# asserted lad[3:0] tri-state tri-state tri-state serirq tri-state tri-state tri-state clkrun# tri-state tri-state tri-state source description lpc_internal_err the lpc_internal_err event is sourced by bit d0 of the host bus error register .
? 2014 - 2015 microchip technology inc. ds00001719d-page 79 MEC1322 the lpc controller claims only lpc transactions targeted for one of its peripherals. section 5.8.2, on page 81 , describes the mechanism for claiming and forwarding transactions for supported lpc cycles . lpc transactions may be used to configure the chip and to access registers du ring operation. the mechanism to configure the chip is described in section 5.8.3, "configuration port," on page 83 . lpc memory cycles may also be used to access the base address registers of certain devices. once configured, the lpc peripherals implemen ted as logical devices on chip may use the serirq to notify the host of an event. see section 5.8.4, "serial irqs," on page 84 . 5.8.1 lpc controll er description the following sections qualify the lpc features implemented according to the lpc specification. 5.8.1.1 cycle types supported the following cycle types are supported by the lpc interface controller. all other cycles that it does not support are ignored. when the lpc controller detects a transaction targeted for this device it claims and forwar ds that transaction as defined in section 5.8.2, "claiming and forwarding transa ctions for supported lpc cycles," on page 81 . lpc i/o cycles the system host may use lpc i/o cycles to read/write the i /o mapped configuratio n and runtime registers implemented in this device. see the intel? low pin count (lpc) interface specification, v1.1 , section 5.2 for definition of lpc i/o cycles. lpc memory cycles the system host may use lpc memory cycl es to access memory mapped regist ers implemented in this device. see the intel? low pin count (lpc) in terface specification, v1.1 , section 5.1 for definition of lpc memory cycles. 5.8.1.2 lad[3:0] fields the lad[3:0] signals support multiple fields for each protocol as defined in section 4.2.1 lad[3:0] of the intel? low pin count (lpc) interface specification, v1.1 . the following sections further qualify the fields supported. wait syncs on lpc lpc transactions that access registers located on the device require a minimum of two wait syncs on the lpc bus. the number of syncs may be larger if the internal bus is in use by the embedded controller, of if the data referenced by the host is not present in a register. the device always uses long wait syncs, rather than short wait syncs, when responding to an lpc bus request. error syncs on lpc the device does not issue error sync cycles. table 5-8: lpc cycle types supported cycle type transfer size i/o read 1 byte i/o write 1 byte memory read 1 byte memory write 1 byte note: all lpc transactions are synchronized to the lclk and will complete with a maximum of 8 wait states, unless otherwise noted.
MEC1322 ds00001719d-page 80 ? 2014 - 2015 microchip technology inc. 5.8.1.3 lpc clock run using clkrun# clkrun# is used to indicate the status of lclk as well as to request that a stopped clock be started. see figure 5-2: clkrun# system impl ementation example on page 81 , an example of a typical system implementation using clkrun#. lclk run support can be enabled and disabled via sirq_mode as shown in table 5-9, "lpc controller clkrun# function" . when the sirq_mode is ?0,? serial irqs are disabled, the clkrun# pin is disabled, and the affects of inter- rupt requests on clkrun# are ignored. when the sirq_mode is ?1,? serial irqs are enabled, the clkrun# pin is enabled, and the clkrun# support related to interrupts requests as described in the section below is enabled. the clkrun# pin is an open drain output and input. refer to the pci mobile design guide rev 1.0 for a description of the clkrun# function. if clkrun# is sampled ?high?, lc lk is stopped or stopping. if clkrun# is sampled ?low?, lclk is starting or started (running). clkrun# support for serial irq cycle if a logical device asserts or de-asserts an interrupt and clkrun# is sampled ?high?, the lpc controller can request the restoration of the clock by asserting the clkrun# signal asynchronously ( table 5-9 ). the lpc controller holds clkrun# low until it detects two rising e dges of the clock. after the second clock edge, the controller must disable the open drain driver ( figure 5-3 ). the lpc controller must not assert clk run# if it is already driven low by t he central resource; i.e., the pci clock generator in figure 5-2 . the controller does not assert clkrun# under any conditions if the serial irqs are dis- abled. the lpc controller must not assert cl krun# unless the line has been de-assert ed for two successive clocks; i.e., before the clock was stopped ( figure 5-3 ). the lpc controller does not assert clk run# if it is already driven low by th e central resource; i.e., the pci clock generator. the lpc controller also does not assert clkrun# unless the signal has been de-asserted for two successive clocks; i.e., before the clock was stopped. note 5-5 sirq_mode is defined in section 5.8.4.1, "enabling serirq function," on page 84 . note 5-6 ?change? means either-edge change on any or all parallel irqs routed to the serial irq block. the ?change? detection logic must run asynchronously to lclk and regardless of the serial irq mode; i.e., ?continuous? or ?quiet?. table 5-9: lpc controller clkrun# function sirq_mode ( note 5-5 ) internal interrupt or dma request clkrun# action 0xxnone 1 no change x none change ( note 5-6 )0 none 1 assert clkrun#
? 2014 - 2015 microchip technology inc. ds00001719d-page 81 MEC1322 figure 5-3: clock start illustration note 1: the signal ?any change? is the same as ?change/assertion? in table 5-9 . 2: the lpc controller must continually monitor the state of clkrun# to maintain lclk until an active ?any irq change? condition has been transferred to the host in a serial irq cycle or ?any drq assertion? con- dition has been transferred to the host in a dma cycl e. for example, if ?any ir q change or dr q assertion? is asserted before clkrun# is de-asserted (not shown in figure 5-3 ), the controller mu st assert clkrun# as needed until the serial irq cycle or dma cycle has completed. 5.8.2 claiming and forwarding tran sactions for supported lpc cycles the following sections define how the lpc controller determines if a cycle is targeted for one of the chip?s logical devices and how that transaction is then forwarded to that logical device. the following sections include: ? section 5.8.2.1, "i/o transactions," on page 81 ? section 5.8.2.2, "device memo ry transactions," on page 82 5.8.2.1 i/o transactions the system host will generate i/o comma nds to communicate with i/o peripherals , such as keyboard controller, uart, etc. the lpc controller claims only i/o transactions target ed to it and it ignores all others. the following sections describe how i/o transactions are claimed and forwarde d to access the runtime and configuration registers. figure 5-2: clkrun# system implementation example clkrun# lclk target pci clock generator (central resource) master ec device lclk clkrun# serirq mode bit any change clkrun# driven by ec device ec device stops driving clkrun# (after two rising edges of lclk) 2 clks min.
MEC1322 ds00001719d-page 82 ? 2014 - 2015 microchip technology inc. claiming lpc i/o transactions the lpc controller claims an i/o transacti on that is targeted for one of its per ipherals (also referred to as logical devices). a base address register has been implemented for each logical device. see section 5.9.3, "i/o base address registers (bars)," on page 91 . if one of the addresses programmed in the logical device base address registers matches an lpc i/o address using the following relationship, the lpc cont roller will claim the lpc bus cycle: (lpc address & ~bar.mask) == (bar.lpc_a ddress & ~bar.mask) && (bar.valid == 1) forwarding i/o transactions the system host will use i/o transactions to ac cess the configuration and runtime registers. to access the runtime registers, the host must configure the i/o base address registers (bars) , which are accessible via the configuration port . the configuration port, logical device ch, is located at the base i/o address programmed in the bar configuration regi ster located at offset 60h. if the i/o transaction matches the bar of logical device ch , the transaction will be forward ed to the configuration port, otherwise the transaction will be forwarded to the runtime registers of the targeted logical device. each logical device may have up to 128 contiguous runt ime registers. the runtime registers are located at a defined offset from the logical device?s base address. the host can directly access these registers with a standard lpc i/o command. the logical device number for the matching device is located in the frame field of the bar. when matching lpc i/o addresses, the lp c controller ignores address bits that correspond to ?1b? bits in the mask field. for illustration purposes only, lets examine two types of lo gical devices (these may or may not reside in this design). example 1: the keyboard controller (8042 interface) base address regi ster has 60h in the lpc address field, the frame field is 01h, and the mask field is 04h. because of the single ?1b? bi t in mask, the bar will match lpc i/o patterns in the form ?0000_0000_0110_0x00b?, so both 60h and 64h will be matched and claimed by the lpc controller. example 2: if a standard 16550 uart was located at lpc i/o address 238h, then the uart receive buffer would appear at address 238h and the line status register at 23dh. if th e bar for the uart was set to 0238_8047h, then the uart will be matched at i/o address 238h. 5.8.2.2 device memory transactions alternatively, lpc memory transactions can be used to a ccess certain logical devices. the lpc controller claims a memory transaction that is targeted for one of these logical devices. a device memory base address register has been implemented for the logical devices listed in table 5-17, ?device memory base address register default values,? on page 93 . on every lpc bus memory access all base address registers are checked in parallel and if any matches the lpc mem- ory address the MEC1322 claims the bus cycle. th e memory address is claimed as described in i/o transactions except that the lpc memory cycle address is 32 bits instead of the 16 bit i/o cycle address. software should insure that no two bars map the same lpc memory address. if two bars do map to the same address, the bar_conflict bit in the host bus error regist er is set when an lpc access targeting the bar conflict address. an ec interrupt can be generated. each device memory bar is 48 bits wide. the fo rmat of each device memory bar is summarized in device memory base address register format . an lpc memory request is translated by th e device memory bar into an 8-bit read or write transaction on the ahb bus. the 32-bit lpc me mory address is translated into a 24-bit ahb address the base address register table is itself part of the ah b address space. it resides in the configurat ion quadrant of logical device ch, the lpc interface. note: the lpc controller?s base address register is used to define the base i/o address of the configuration port .
? 2014 - 2015 microchip technology inc. ds00001719d-page 83 MEC1322 5.8.3 configuration port the lpc host can access the chip?s configuration regist ers through the configuration port when config mode is enabled. the device defaults to config mode being disabled. the configuration port is composed of an index and data re gister. the index register is used as an address pointer to an 8-bit configuration register and the data register is us ed to read or write the data value from the indexed config- uration register. once config mode is enabled, reading the configuration port data register will return the data value that is in the indexed configuration register. if no value was written to the index regi ster, reading the data register in the c onfiguration port will return the value in configuration address location 00h (default). note 5-7 the default base i/o address of the configurat ion port can be relocated by programming the bar register for logical device ch (lpc/configuration port) at offset 60h. the relative address shows the general case for determining t he i/o address for each register. 5.8.3.1 enable config mode the index and data registers are effective only when t he chip is in config mode. config mode is enabled when the config entry key is successfully writ ten to the i/o address of the index re gister of the config port while the config mode is disabled (see section 5.8.3.2, "disable config mode" ). config entry key = < 55h> 5.8.3.2 disable config mode config mode defaults to disabled on a vcc1_reset , nsio_reset , and when lreset# is asserted. config mode is also disabled when the following config exit key is successfully written to the i/o address of the index port of the config port while config mode is enabled. config exit key = < aah> 5.8.3.3 configuration sequence example to program the configuration registers, the following sequence must be followed: 1. enable configuration state 2. program the config uration registers 3. disable configuration state. the following is an example of a configurat ion program in intel 8086 assembly language. ;----------------------------. ; enable configuration state ;----------------------------' mov dx,config_port_base_address mov ax,055h; config entry key out dx,al ;----------------------------. ; configure base address, | ; logical device 8 | ;----------------------------' mov dx,config_port_base_address mov al,07h out dx,al; point to ld# config reg mov dx,config_port_base_address+1 note: the data read from the configuration port data regist er is undefined when conf ig mode is not enabled. table 5-10: configuration port default i/o address ( note 5-7 ) type register name relative address default value notes 002eh read / write index configuration port?s base address + 0 00h note 5-7 002fh read / write data configuration port?s base address + 1 00h
MEC1322 ds00001719d-page 84 ? 2014 - 2015 microchip technology inc. mov al, 08h out dx,al; point to logical device 8 ; mov dx,config_port_base_address mov al,60h out dx,al ; point to base address register mov dx,config_port_base_address+1 mov al,02h out dx,al ; update base address register ;-----------------------------. ; disable configuration state ;-----------------------------' mov dx,config_port_base_address mov ax,0aah; config exit key out dx,al. 5.8.4 serial irqs the device supports the serial interrup t scheme, which is adopted by several co mpanies, to transmit interrupt informa- tion to the system. the serial in terrupt scheme adheres to the serial irq specification for pci systems version 6.0. . 5.8.4.1 enabling serirq function each serial irq channel defaults to disabled. to enable a serial irq channel the host must program the serial irq configuration registers on page 89 . 5.8.4.2 timing diagrams for serirq cycle lclk = lclk pin serirq = serial irq pin start frame timing with source sampled a low pulse on irq1 figure 5-4: serial interrupts waveform ?start frame? start frame pulse can be 4-8 clocks wide. stop frame timing with host using 17 serirq sampling period h=host control sl=slave control r=recovery t=turn-around s=sample r tsr ts ser irq lclk host controlle r irq1 irq1 drive source rt none irq0 frame irq1 frame srt irq2 frame none start start frame h sl or h
? 2014 - 2015 microchip technology inc. ds00001719d-page 85 MEC1322 figure 5-5: serial interrupt waveform ?stop frame? stop pulse is two clocks wide for quiet mode, three clocks wide for continuous mode. there may be none, one, or more idle states during the stop frame. the next serirq cycle?s start frame pulse may or may not start immediately after the turn-around clock of the stop frame. 5.8.4.3 serirq cycle control serirq start frame there are two modes of operat ion for the serirq start frame. quiet (active) mode any device may initiate a start frame by driving the serir q low for one clock, while the serirq is idle. after driving low for one clock, the serirq must immediately be tri-stated without at any time driving high. a start frame may not be initiated while the serirq is active. the serirq is id le between stop and start frames. the serirq is active between start and stop frames. this mode of operation al lows the serirq to be idle when there are no irq/data transitions which should be most of the time. once a start frame has been initiated, the host controller will take over driving the serirq low in the next clock and will continue driving the serir q low for a programmable period of three to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller will drive the serirq back high for one clock then tri-state. any serirq device which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host cont roller unless the serirq is already in an serirq cycle and the irq/data tran- sition can be delivered in that serirq cycle. continuous (idle) mode only the host controller can initiate a start frame to update irq/data line information. all other serirq agents become passive and may not initiate a start fram e. serirq will be driven low for four to eight clocks by host controller. this mode has two functions. it can be used to stop or idle the serirq or the host controller can operate serirq in a con- tinuous mode by initiating a start fr ame at the end of every stop frame. an serirq mode transition can only occur during the stop frame. upon reset, serirq bus is defaulted to continuous mode, therefore only the host c ontroller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next serirq cycle?s mode. serirq data frame once a start frame has been initiated, the lpc controller wil l watch for the rising edge of the start pulse and start count- ing irq/data frames from there. each irq/data frame is three clocks: sample phase, recovery phase, and turn- around phase. during the sample phase, the lpc controller must drive the serirq (sirq pin) low, if and only if, its last detected irq/data value was low. if its detected irq/data value is high, serirq must be left tri-stated. during the recovery phase, the lpc controller must drive the serirq high, if and only if, it had driven the serirq low during the previous sample phase. during the turn-a round phase, the controller must tri-st ate the serirq. the device drives the serirq line low at the appropriate sample point if its associ ated irq/data line is low, regardless of which device initi- ated the start frame. h=host control r=recovery t=turn-around s=sample i= idle s r ts serirq lclk host controller irq15 driver r t none irq14 irq15 s r t iochck# none stop r t stop frame h i start next cycle frame frame frame
MEC1322 ds00001719d-page 86 ? 2014 - 2015 microchip technology inc. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minus one e.g. the irq5 sample clock is the sixth irq/data frame, then the sample phase is {(6 x 3) - 1 = 17} the seventeenth clock after the rising edge of the start pulse. the sirq data frame will now support irq2 from a logica l device; previously serirq period 3 was reserved for use by the system management interrupt (lsmi#). when using peri od 3 for irq2, the user should mask off the smi via the esmi mask register. likewise, when using period 3 for ls mi#, the user should not configure any logical devices as using irq2. serirq period 14 is used to transfer irq13. each logical dev ices will have irq13 as a choice for their primary inter- rupt. stop cycle control once all irq/data frames have complet ed, the host controller will terminate seri rq activity by initiating a stop frame. only the host controller can initiate the stop frame. a stop frame is indicated when the serirq is low for two or three clocks. if the stop frame?s low time is two clocks, then the next serirq cycle?s sampled mode is the quiet mode; and any serirq device may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. if the stop frame?s low time is three clocks, then the next serirq cycle?s sampled mode is the continuous mode, and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. 5.8.4.4 latency latency for irq/data updates over t he serirq bus in bridge-less systems with the minimum irq/data frames of 17 will range up to 96 clocks (3.84 s with a 25 mhz lclk or 2.88 s with a 33 mhz lclk). 5.8.4.5 eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transit ion that it should have followed. th is could cause a system fault. the host interrupt controller is responsible for ensuring that thes e latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the serirq cycle latency in order to ensure that these events do not occur out of order. table 5-11: serirq sampling periods serirq period signal sampled # of clocks past start 1not used 2 2irq1 5 3irq2 8 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 note: if one or more pci to pci bridge is added to a system , the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for syn chronous buses, and approximately double for asyn- chronous buses.
? 2014 - 2015 microchip technology inc. ds00001719d-page 87 MEC1322 5.8.4.6 ac/dc spec ification issue all serial irq agents must drive/sample serirq synchrono usly related to the rising edge of lclk. the serirq pin uses the electrical specification of the pci bus. electrical parameters will follow the pci local bus specification, rev. 2.2 definition of ?sustained tri-state.? 5.8.4.7 reset and initialization the serirq bus uses lreset# as its rese t signal and follows the pci bus rese t mechanism. the serirq pin is tri- stated by all agents while lreset# is ac tive. with reset, serirq slaves and bri dges are put into the (continuous) idle mode. the host controller is re sponsible for starting the initial serirq cycl e to collect system?s irq/data default values. the system then follows with the continuous/quiet mode protocol (stop frame pulse width) for subsequent serirq cycles. it is the host controller?s responsibility to provide the default values to the 8259?s and other system logic before the first serirq cycle is performed. for serirq system suspend, inse rtion, or removal applicat ion, the host controller should be programmed into continuous (idle) mode first. this is to ensure the serirq bus is in idle state before the system configuration changes. 5.8.4.8 serirq interrupts the lpc controller routes logical device interrupts onto sirq stream frames irq[0:15]. routing is controlled by the sirq interrupt configuration registers. there is one sirq interrupt configur ation register for each accessible sirq frame (irq); all 16 registers are listed in table 5-15, "sirq interrupt configuration register map" . the format for each sirq interrupt configuration register is described in section 5.9.2.1, "sirq configuration register format," on page 90 . each logical device can have up to two lpc serirq interrupts. when the device is polled by the host, each sirq frame routes the level of the logical device interrupt (selected by the corresponding sirq interrupt configuration register) to the sirq stream. 5.8.4.9 serirq routing each sirq interrupt configuration register controls a series of multiplexers which route to a single logical device inter- rupt as illustrated in figure 5-6: sirq routing internal logical devices on page 88 . the following table defines the serial irq routing for each logical device implemented in the chip. table 5-12: logical d evice sirq routing sirq interrupt configuration register logical device interrupt source select device frame logical device (block instance - note 1: ) interrupt source 0 0 0h emi ec-to-host 1 0 0h emi host event 0 0 1h 8042 keyboard controller kirq 1 0 1h 8042 keyboard controller mirq 0 0 3h acpi ec0 ec_obf 0 0 4h acpi ec1 ec_obf 0 0 5h acpi pm1 n/a 0 0 6h legacy port92/gatea20 n/a 007huart 0 uart 0 0 9h mailbox mbx_host sirq 1 0 9h mailbox mbx_host_smi
MEC1322 ds00001719d-page 88 ? 2014 - 2015 microchip technology inc. note 1: the block instance number is only included if there are multiple instantiations of a block. otherwise, single block instances do not require this differentiation. figure 5-6: sirq routing internal logical devices 5.9 lpc configuration registers the configuration registers listed in table 5-14, "configuration register summary" are for a single instance of the lpc interface . the addresses of each register listed in table 5-14 are defined as a relative offset to the host ?begin address? defined in table 5-13 . 00bhrtc rtc 0 0 ch lpc interface ec_irq note: two logical devices cannot share a serial irq. table 5-12: logical device sirq routing (continued) sirq interrupt configuration register logical device interrupt source select device frame logical device (block instance - note 1: ) interrupt source 0 1 ? ? ? ? ? ? ld 00h- int ld 3fh- int ld 00h-int0 ld 00h-int1 0 1 sirq i conguration register[7:0] device frame select serirq i source 8 7 6 0 1 ld 3fh-int0 ld 3fh-int1
? 2014 - 2015 microchip technology inc. ds00001719d-page 89 MEC1322 note 5-8 the begin address indicates where the first register can be accessed in a particular address space for a block instance. 5.9.1 lpc activate register the lpc activate register controls the lpc device itself. the host can shut down the lpc logical device by clearing the activate bit, but it cannot restart the lpc interface, since once the lpc interface is inactive the host has no access to any registers on the device. the embedded controll er can set or clear the activate bit at any time. application note: the bit in the lpc activate register should not be written ?0? to by the host over lpc. 5.9.2 serial irq conf iguration registers the lpc controller implements 16 irq channels that may be configured to be asserted by any logical device. ? for a description of the sirq configuration register format see table 5-15, ?sirq interrupt configuration regis- ter map,? on page 90 . ? for a summary of the sirq irq configuration registers implemented see table 5-16, ?i/o base address regis- ters,? on page 92 . ? for a list of the sirq sources see table 5-12, ?logical device sirq routing,? on page 87 . table 5-13: config uration register address range table instance name instance number host address space begin address ( note 5-8 lpc interface 0 lpc configuration port index = 00h 0 ec 32-bit internal address space 400f_3300h table 5-14: configuration register summary register name offset size notes lpc activate register 30h 8 sirq configuration register format 40h - 4fh 8 i/o base address registers (bars) see table 5-16 32 device memory base address registers see table 5-17 48 offset 30h bits description type default reset event 7:1 reserved res - - 0 activate 1= activate when this bit is 1, the lpc logical device is powered and functional. 0= deactivate when this bit is 0, the logical device is powered down and inactive. except for the lpc activate register itself, clocks to the block are gated and the lpc logical device will permit the ring oscillator to be shut down (see section 5.11.4, "ec clock control register," on page 96 ). lpc bus output pads will be tri-stated. r/w 0b vcc1_r eset
MEC1322 ds00001719d-page 90 ? 2014 - 2015 microchip technology inc. 5.9.2.1 sirq configuration register format note 5-9 see table 5-15, ?sirq interrupt configuration register map,? on page 90 . 5.9.2.2 sirq configuration registers offset see table 5-15, ?sirq interrupt configuration register map,? on page 90 . bits description type default reset event 7 select if this bit is 1, the first interrupt signal from the logical device is selected for the serirq vector. if this bit is 0, the second interrupt signal from the logical device is selected. note: the keyboard controller is an example of a logical devices that requires a second interrupt signal. most logical devices require only a single interrupt and ignore this field as result. r/w note 5-9 nsio_r eset 6 device this field should always be set to 0 in order to enable a serirq. r/w note 5-9 nsio_r eset 5:0 frame these six bits select the logical device for on-chip devices as the source for the interrupt. note: the lpc logical device (logical device number 0ch) can be used by the embedded controller to generate a serial interrupt request to the host under software con- trol. r/w note 5-9 nsio_r eset table 5-15: sirq interrupt co nfiguration register map offset type reset configuration register name 40h r/w ffh irq0 41h r/w ffh irq1 42h r/w ffh irq2 43h r/w ffh irq3 44h r/w ffh irq4 45h r/w ffh irq5 46h r/w ffh irq6 47h r/w ffh irq7 48h r/w ffh irq8 49h r/w ffh irq9 4ah r/w ffh irq10 4bh r/w ffh irq11 4ch r/w ffh irq12 4dh r/w ffh irq13 4eh r/w ffh irq14 4fh r/w ffh irq15 note: a serirq interrupt is deactivated by setting an entry in the sirq interrupt configuration register map to ffh, which is the default reset value.
? 2014 - 2015 microchip technology inc. ds00001719d-page 91 MEC1322 5.9.3 i/o base address registers (bars) the lpc controller has implemented a base address register (bar) for each logical device in the lpc configuration space. ? for a description of the base address register format see section 5.9.3.1, "i/o base address register format," on page 91 . ? for a description of the bars per logical device see table 5-16, ?i/o base address registers,? on page 92 . on every lpc bus i/o access the unmasked portion of the pr ogrammed lpc host address in each of the base address registers are checked in parallel and if any matches the lpc i/o address the lpc controller claims the bus cycle. the format of each bar is summarized in section 5.9.3.1, "i/o base address register format," on page 91 . 5.9.3.1 i/o base address register format each lpc accessible logical device has a programmable ba se address register. the following table defines the generic format used for all of these registers. see table 5-16, "i/o base address registers" for a list of all the logical device base address registers implemented. note 5-10 offset 60h is the lpc base address register. the lpc base address register is only reset on vcc1_reset . however, bits[31:16] are reloaded on nsio_reset with the value in the lpc bar init register . note 5-11 bits[31:16] lpc host address bit field in the lpc ba se address register at offset 60h must be written lsb then msb. this particular register has a shadow that lets the host come in and write to the lower byte of the 16-bit address, and the resulting 16-bit lpc host address field does not update. writing to the upper byte triggers a full 16-bit field update. note: software should that insure that no two bars map the same lpc i/o address. if two bars do map to the same address, the lpc_internal_err and bar_conflict status bits are set when an lpc access is targeting the address with the bar conflict. offset see table 5-16, ?i/o base address registers,? on page 92 bits description type default reset event 31:16 lpc host address these 16 bits are used to match lpc i/o addresses r/w ( note 5- 11 ) see ta b l e 5 - 1 6 note 5- 10 15 valid if this bit is 1, the bar is valid and will participate in lpc matches. if it is 0 this bar is ignored r/w see ta b l e 5 - 1 6 note 5- 10 14 device (device) this bit combined with frame constitute the logical device num- ber. device identifies the physical location of the logical device. this bit should always be set to 0. r see ta b l e 5 - 1 6 note 5- 10 13:8 frame these 6 bits are used to specify a logical device frame number within a bus. this field is multiplied by 400h to provide the frame address within the peripheral bus address. frame values for frames corresponding to logical devices that are not present on the device are invalid. r see ta b l e 5 - 1 6 note 5- 10 7:0 mask these 8 bits are used to mask off address bits in the address match between an lpc i/o address and the host address field of the bars, as described in section 5.8.2.1, "i/o transactions" . a block of up to 256 8-bit registers can be assigned to one base address. r see ta b l e 5 - 1 6 note 5- 10
MEC1322 ds00001719d-page 92 ? 2014 - 2015 microchip technology inc. 5.9.3.2 logical device i/o bar description the following table defines the lpc i/o bar of each logical device implemented in the design. table 5-16: i/o base address registers 5.9.4 device memory base address registers some logical devices have a memory base address regist er. these device memory bars are located in blocks of configuration registers in logical device 0ch, in the ahb address range 400f_33c0h through 400f_33ffh. the fol- lowing table defines the generic format used for all of these registers. each device memory bar is 48 bits wide. the format of each device memory bar is summarized in device memory base address register format . an lpc memory request is translated by th e device memory bar into an 8-bit read or write transaction on the ahb bus. the 32-bit lpc me mory address is translated into a 24-bit ahb address 5.9.4.1 device memory base address register format offset see table 5-17, "device memory base address register default values" bits description type default reset event 47:16 host_address[31:0] these 32 bits are used to match lpc memory addresses. r/w see ta b l e 5 - 1 7 nsio_r eset 15 valid if this bit is 1, the bar is valid and will participate in lpc matches. if it is 0 this bar is ignored. r/w see ta b l e 5 - 1 7 nsio_r eset 14 reserved res - - bits [d31:d16] bit [d15] bit [d14] bits [d13:d8] bits [d6:d0] offset logical device number logical devices reset default default lpc i/o host address valid device frame mask 60h c lpc interface (configuration port) 002e_0c01 (note 1) 002e 0 0 c 1 64h 0 emi 0 0000_000f 0000 0 0 0 f 68h 7 uart 0 0000_0707 0000 0 0 7 7 78h 1 8042em 0060_0104 0060 0 0 1 4 88h 3 acpi ec0 0062_0304 0062 0 0 3 4 8ch 4 acpi ec1 0066_0407 0066 0 0 4 7 90h 5 acpi pm1 0000_0507 0000 0 0 5 7 94h 6 legacy port92/gatea20 0092_0600 0092 0 0 6 0 98h 9 mailbox 0000_0901 0000 0 0 9 1 9ch b rtc 0000_0b3f 0000 0 0 b 3f base address register bit field descriptions note 2: the frame and mask fields for these legacy devices are not used to determine which lpc i/o addresses to claim. the address range match is maintained within the blocks themselves. note 1: the default base i/o address of the configuration port can be relocated by programming the bar register for logical device ch (lpc/configuration port) at offset 60h.
? 2014 - 2015 microchip technology inc. ds00001719d-page 93 MEC1322 note 5-12 the mask and frame fields of all logical devices ar e read-only except for 3h (acpi ec channel 0). 5.9.4.2 device memory base address register table table 5-17 lists the base address registers for logical devices which have lpc memory access in the MEC1322. lpc memory cycle access is controlled by lpc memory base address registers. lpc memory bar registers are located in ldn ch (lpc interface) at ahb base address 400f_3300h starting at the offset shown in ta b l e 5 - 1 7 . note 1: the valid, device, frame and mask fields are as shown in table 5-16, "i/o base address registers" . 5.10 runtime registers the runtime registers listed in table 5-19, "runtime register summary" are for a single instance of the lpc interface . the addresses of each register listed in table 5-19 are defined as a relative offset to the host ?begin address? define in table 5-2 . note 1: the begin address indicates where the first register can be accessed in a particular address space for a block instance. 2: the lpc runtime registers are only accessible from the lpc interface and are used to implement the lpc configuration port. they are not accessible by any other host. 13:8 frame these 6 bits are used to specify a lo gical device frame number within a bus. this field is multiplied by 400h to provide the frame address within the peripheral bus address. in the MEC1322 frame values for frames corresponding to logical devices that are not present on the MEC1322 are invalid. note 5- 12 see ta b l e 5 - 1 7 nsio_r eset 7:0 mask these bits are used to mask off ad dress bits in the address match between an lpc memory address and the host address field of the bars, as described in the following section. note 5- 12 see ta b l e 5 - 1 7 nsio_r eset table 5-17: device memory base address register default values lpc offset in cr space logical device number logical device memory bar default value lpc memory address c0h 9h mailbox 0000_0000_0901h 0000_0000h c6h 3h acpiec0 0000_0062_0304h 0000_0062h cch 4h acpiec1 0000_0066_0407h 0000_0066h d2h 0h emi 0000_0000_000fh 0000_0000h table 5-18: runtime register address range table instance name instance number host address space begin address lpc interface 0 lpc lpc i/o base i/o address of logical device ch +00h offset see table 5-17, "device memory base address register default values" bits description type default reset event
MEC1322 ds00001719d-page 94 ? 2014 - 2015 microchip technology inc. 5.10.1 index register 5.10.2 data register 5.11 ec-only registers the registers listed in table 5-21, "ec-only register summary" are for a single instance of the lpc interface . their addresses are defined as a relative offset to the host base address defined in ta b l e 5 - 2 0 . the following table defines the fixed host base address for each lpc interface instance. the begin address indicates where the first register can be accessed in a particular address space for a block instance. table 5-19: runtime register summary offset register name 00h index register 01h data register note: the lpc runtime register space has been used to implement the index and data registers in the con- figuration port. in config_mode, the configuration po rt is used to access the configuration registers. offset 00h bits description type default reset event 7:0 index the index register, which is part of the configuration port, is used as a pointer to a configuration register address. note: for a description of accessing the configuration port see section 5.8.3, "configuration port," on page 83 . r/w 0h vcc1_r eset offset 01h bits description type default reset event 7:0 data the data register, which is part of the configuration port, is used to read or write data to the register currently being selected by the index register. note: for a description of accessing the configuration port see section 5.8.3, "configuration port," on page 83 r/w 0h vcc1_r eset note: ec-only registers are not accessible by the lpc interface. table 5-20: ec-only register address range table instance name instance number host address space begin address lpc interface 0 ec 32-bit internal address space 400f_3100h
? 2014 - 2015 microchip technology inc. ds00001719d-page 95 MEC1322 5.11.1 lpc bus monitor register 5.11.2 host bus error register table 5-21: ec-only register summary offset register name 04h lpc bus monitor register 08h host bus error register 0ch ec serirq register 10h ec clock control register 14h mchp test register 18h mchp test register 20h bar inhibit register 24h mchp reserved 28h mchp reserved 2ch mchp reserved 30h lpc bar init register note: mchp reserved registers are read/writ e registers. modifying these registers may have unwanted results. offset 04h bits description type default reset event 31:2 reserved res - - 1 lreset_status this bit reflects the state of the lreset# input pin. the lre- set_status is the inverse of the lreset# pin. when the lreset_status bit is ? 0b?, the lreset# input pin is de- asserted (that is, the pin has the value ?1b?). wh en the lreset_sta- tus bit is ?1b?, the lreset# input pin is asserted (that is, the pin has the value ?0b?). r0h vcc1_r eset 0 mchp reserved r 0h vcc1_r eset offset 08h bits description type default reset event 31:8 erroraddress[23:16] this 24-bit field captures the 24-bit internal address of every lpc transaction whenever the bit lpc_internal_err in this register is 0. when lpc_internal_err is 1 this register is not updated but retains its previous value. when bus errors occur this field saves the address of the first address that caused an error. r0h vcc1_r eset 5dma_err this bit is set to 1 whenever en_internal_err is 1 and an lpc dma access causes an internal bus error. once set, it remains set until cleared by being written with a 1. r/wc 0h vcc1_r eset
MEC1322 ds00001719d-page 96 ? 2014 - 2015 microchip technology inc. 5.11.3 ec serirq register 5.11.4 ec clock control register 4config_err this bit is set to 1 whenever en_internal_err is 1 and an lpc configuration access causes an internal bus error. once set, it remains set until cleared by being written with a 1. r/wc 0h vcc1_r eset 3 runtime_err this bit is set to 1 whenever en_internal_err is 1 and an lpc i/o access causes an internal bus error. this error will only occur if a bar is misconfigured. once set, it remains set until cleared by being written with a 1. r/wc 0h vcc1_r eset 2 bar_conflict this bit is set to 1 whenever a bar conflict occurs on an lpc address. a bar conflict occurs when more than one bar matches the address during of an lpc cycle acce ss. once this bit is set, it remains set until cleared by being written with a 1. r/wc 0h vcc1_r eset 1 en_internal_err when this bit is 0, only a bar conflict, which occurs when two bars match the same lpc i/o address, will cause lpc_internal_err to be set. when this bit is 1, internal bus errors will also cause lpc_internal_err to be set. r/wc 0h vcc1_r eset 0 lpc_internal_err this bit is set whenever a bar conflict or an internal bus error occurs as a result of an lpc acce ss. once set, it remains set until cleared by being written with a 1. this signal may be used to gener- ate interrupts. see section 5.6, "interrupts," on page 78 . r/wc 0h vcc1_r eset offset 0ch bits description type default reset event 31:1 reserved res - - 0ec_irq if the lpc logical device is selected as the source for a serial inter- rupt request by an interrupt configuration register (see section 5.8.4.8, "serirq interrupts," on page 87 ), this bit is used as the interrupt source. r/w 0h vcc1_r eset offset 10h bits description type default reset event 31:3 reserved res - - 2 handshake this bit controls throughput of lpc transactions. when this bit is a ?0? the part supports a 33mhz pci clock. when this bit is a ?1?, the part supports a pci clock from 19.2mhz (includ- ing 24mhz) to 33mhz. res 1h vcc1_ reset offset 08h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 97 MEC1322 5.11.5 mchp test register 5.11.6 mchp test register 1:0 clock_control this field controls when the host in terface will permit the internal ring oscillator to be shut down. the choices are as follows: 0h: reserved 1h: the host interface will permit th e internal clocks to be shut down if the clkrun# signals ?clock stop? and there are no pending serial interrupt request or dma requests from devices associated with the device. the clkrun# signals ?clock stop? by clkrun# being high for 5 lpcclk?s after the raising edge of clkrun# 2h: the host interface will permit the ring oscillator to be shut down after the completion of every lpc transaction. this mode may cause an increase in the time to respond to lpc transactions if the ring oscillator is off when the lpc transaction is detected. 3h: the ring oscillator is not permitted to shut down as long as the host interface is active. when the activate bit in the lpc activate register is 0, the host interface will pe rmit the ring oscillator to be shut down and the clock_control field is ignored. the clock_con- trol field only effects the host interface when the activate bit in the lpc activate register is 1. although the host interface can permit the internal oscillator to shut down, it cannot turn the oscillator on in response to an lpc transac- tion that occurs while the oscillator is off. in order to restart the oscil- lator in order to complete an lpc transaction, ec firmware must enable a wake interrupt on the lpc lframe# input. see the appli- cation note in section 15.8.1, "wake generation" for details. r/w 0h vcc1_ reset offset 14h bits description type default reset event 31:8 reserved res - - 7:0 mchp reserved r 0h vcc1_r eset offset 18h bits description type default reset event 31:2 reserved res - - 1 mchp reserved r/w 0h vcc1_r eset 0 mchp reserved r/w 0h vcc1_r eset offset 10h bits description type default reset event
MEC1322 ds00001719d-page 98 ? 2014 - 2015 microchip technology inc. 5.11.7 bar inhibit register 5.11.8 lpc bar init register offset 20h bits description type default reset event 31:0 bar_inhibit[31:0] when bit di of bar_inhibit is 1, the bar for logical device i is dis- abled and its addresses will not be claimed on the lpc bus, inde- pendent of the value of the valid bit in the bar.the association between bits in bar_inhibit and logical devices is illustrated in table 5-22, "bar inhibit device map" . r/w 0h vcc1_r eset table 5-22: bar inhibit device map bar inhibit bit log ical device number 00h 11h . . . . . . 31 31h offset 30h bits description type default reset event 15:0 bar_init this field is loaded into the lpc bar at offset 60h on nsio_reset . r/w 002eh nsio_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 99 MEC1322 6.0 chip configuration 6.1 introduction this chapter defines the mechanism to configure the device. 6.2 terminology this section documents terms used locally in this chapter. common terminology that is used in the chip specification is captured in the chip-level terminology section. 6.3 interface this block is designed to be accessed via the host accessible configuration port. table 6-1: terminology term definition global configuration registers registers used to co nfigure the chip that are always accessible via the configuration port logical device configuration registers registers used to configure a logical device in the chip. these registers are only accessible via the configuration port when enabled via the global configuration registers. figure 6-1: block diagram of configuration port 00h ? 2fh 30h ? ffh logical device configuration registers chip-level global configuration registers l o g i c a l d e v i c e s [ 0 : n ] configuration port
MEC1322 ds00001719d-page 100 ? 2014 - 2015 microchip technology inc. 6.3.1 host interface the registers defined for the chip configuration are accessible by the configuration port when the device is in config mode. for a description of the configuration port and config mode see the description of the lpc interface. 6.4 power, clocks and reset this section defines the power, clock, and reset input parameters to this block. 6.4.1 power domains 6.4.2 clock inputs this block does not require any special clock inputs. 6.4.3 resets 6.5 interrupts this block does not generate any interrupts. 6.6 low power modes this block always automatically adjusts to operate in the lowest power mode. 6.7 description the chip configuration registers are divided into two group s: global configuration registers and logical device con- figuration registers. the following descriptions assume that the lpc interface has already been configured to operate in config mode. ? global configuration registers are always accessible via the lpc configuration port. ? the logical device configuration registers are only acce ssible via the lpc configuration port when the corre- sponding logical device number is loaded in the logical device number register. the logical device number register is a global configuration register. there are 48 8-bit global configuration registers (at offsets 00h through 2fh), plus up to 208 8-bit registers associated with each logical device. the logical device is selected with the logical device number register (global configuration register 07h ). sequence to access logical device configuration register: a) write the number of the logical device being accessed in the logical device number configuration register by writing 07h into the index port and the logical device number into the data port. b) write the address of the desired logical device configur ation register to the index port and then write or read the value of the configuration register through the data port. note: each logical device has a bank of configuration registers that are accessible at offsets 30h to ffh via the configuration port. the logical device number programmed in offset 07h determines which bank of con- figuration registers is currently accessible. table 6-2: power sources name description vcc1 the logic and registers implemented in this block reside on this single power well. table 6-3: reset signals name description vcc1_reset power on reset to the block. this signal resets all the register and logic in this block to its default state.
? 2014 - 2015 microchip technology inc. ds00001719d-page 101 MEC1322 note 1: if accessing the global configuration registers, step (a) is not required. 2: any write to an undefined or reserved configuration register is terminated normally on the lpc bus without any modification of state in the MEC1322. any read to an undefined or reserved configuration register returns ffh. the following sections define the global configurat ion registers and the logical configuration registers. 6.7.1 global control/co nfiguration registers as with all configuration registers, the index port is used to select a global configuration register in the chip. the data port is then used to access the selected register. the index and data ports are defined in the lpc interface description. the host can access all the global configuration registers at the offsets listed in table 6-4, "chip-level (global) con- trol/configuration registers" through the index port and the data port. the ec can access all the global configuration registers at the offsets listed in table 6-4, "chip-level (global) con- trol/configuration registers" from the base address shown in table 6-6, ?ec-only register address table,? on page 102 . 6.7.2 logical device configuration registers the logical device configuration registers support motherbo ard designs in which the resources required by their com- ponents are known and assigned by the bios at post. each logical device may have a set of directly i/o addressable runtime registers, configuration registers accessible via the configuration port, or dma registers. the following table lists the register types for each lpc host-accessible logical device implemented in the design. the embedded co ntroller (ec) can access all configuration registers and all runtime registers directly. table 6-4: chip-level (global) co ntrol/configurati on registers register offset description chip (global) control registers reserved 00h - 06h reserved - writes are ignored, reads return 0. logical device number 07h a write to this regi ster selects the current logical device. this allows access to the control and configuration registers for each logical device. note: the activate command operates only on the selected logical device. reserved 08h - 1fh reserved - writes are ignored, reads return 0. device id 20h a read-only register which provides device identification: bits[7:0] = 15h device revision hard wired 21h a read-only register which prov ides device revision information. bits[7:0] = current revision when read reserved 24h reserved ? writes are ignored, reads return ?0?. mchp reserved 25h - 2fh mchp reserved. this register locations are reserved for microchip use. modify- ing these locations may cause unwanted results.
MEC1322 ds00001719d-page 102 ? 2014 - 2015 microchip technology inc. table 6-5: host logical devices on MEC1322 6.8 ec-only registers note 6-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. the chip-level (global) registers reside in logical de vice 3fh at ec addresses 400f_ff00h through 400f_ff2fh. the ec can access all these registers at the addresses listed in table 6-4, ?chip-level (global) control/configuration registers,? on page 101 . table 6-6: ec-only register address table block instance instance number host address space base address ( note 6-1 ) host_regs 0 ec 32-bit internal address space 400f_ff00h logical device number logical devices lpc i/o runtime access lpc i/o configuration access 0 emi 0 yes no 1 8042em no yes 3 acpi ec0 yes no 4 acpi ec1 yes no 5 acpi pm1 yes no 6 legacy port92/gatea20 yes yes 7uart 0yesyes 9 mailbox yes no brtcyesno
? 2014 - 2015 microchip technology inc. ds00001719d-page 103 MEC1322 7.0 arm m4f based embedded controller 7.1 introduction this chapter contains a description of the arm m4f embedded controller (ec). the ec is built around an arm ? cortex ? -m4f processor provided by arm ltd. (the ?arm m4f ip?). the arm cortex? m4f is a full-featured 32-bit embedded processor, implem enting the armv7-m thumb instruction set and fpu instruc- tion set in hardware. the arm m4f ip is configured as a von neumann, byte-add ressable, little-endian architecture. it provides a single unified 32-bit byte-level address, for a total direct addressing space of 4gbyte. it has multiple bus interfaces, but these express priorities of access to the chip-level resources (instruction fetch vs. data ram vs. others), and they do not represent separate addressing spaces. the arm m4f ip has configurable options, which are selected as follows. ? little-endian byte ordering is selected at all times (hard-wired) ? bit banding feature is included for efficient bit-level access. ? floating-point unit (fpu) is included, to implement the floating-point instruction set in hardware ? debug features are included at ?ex+? level, defined as follows: ? dwt unit provides 4 data watchpoint comparators and execution monitoring ? fpb unit provides hw breakpointing with 6 instruction an d 2 literal (read-only data) address comparators. the fpb comparators are also available for patching: remapping instruction and literal data addresses. ? trace features are included at ?full? level, defined as follows: ? dwt for reporting breakpoints and watchpoints ? itm for profiling and to timestamp and output messages from instrumented firmware builds ? etm for instruction tracing, and for enhanced reporting of core and dwt events ? the arm-defined htm trace feature is not currently included . ? nvic interrupt controller with 8 priority levels and up to 240 individually-vectored interrupt inputs. ? a microchip-defined interrupt aggregator function (at chip level) may be used to group multiple interrupts onto sin- gle nvic inputs. ? the arm-defined wic feature is not currently included . ? microchip interrupt aggregator function (at chip le vel) is expected to provide wake control instead. ? the arm-defined mpu feature is not currently included . ? memory protection functionality is not expected to be necessary. 7.2 references ? arm limited: cortex?-m4 technical reference manual, ddi0439c, 29 june 2010 ? arm limited: arm?v7-m architecture reference manual, ddi0403d, november 2010 ? note: filename ddi0403d_arm_architecture_v 7m_reference_manual_errata_markup_1_0.pdf ? arm? generic interrupt controller architecture version 1.0 architecture specification, ihi0048a, september 2008 ? arm limited: amba? specification (rev 2.0), ihi0011a, 13 may 1999 ? arm limited: amba? 3 ahb-lite protocol specification, ihi0033a, 6 june 2006 ? arm limited: amba? 3 atb protocol specification, ihi0032a, 19 june 2006 ? arm limited: cortex-m? system design kit technical reference manual, ddi0479b, 16 june 2011 ? arm limited: coresight? v1.0 architecture specification, ihi0029b, 24 march 2005 ? arm limited: coresight? components technical reference manual, ddi0314h, 10 july 2009 ? arm limited: arm? debug interface v5 architec ture specification, ihi0031a, 8 february 2006 ? arm limited: arm? debug interface v5 architectu re specification adiv5.1 supplement, dsa09-prdc-008772, 17 august 2009 ? arm limited: embedded trace macrocell? (etmv1.0 to et mv3.5) architecture specification, ihi0014q, 23 sep- tember 2011 ? arm limited: coresight? etm?-m4 technical reference manual, ddi0440c, 29 june 2010
MEC1322 ds00001719d-page 104 ? 2014 - 2015 microchip technology inc. 7.3 terminology 7.3.1 arm ip terms and acronyms ?cortex-m4f ? the arm designation for the specific ip selected for this product: a cortex m4 processor core containing a hard- ware floating point unit (fpu). ?armv7 ? the identifying name for the general architecture implemented by the cortex-m family of ip products. ? note that armv7 has no relationship to the older ?arm 7? product line, which is classified as an ?armv3? archi- tecture, and is very different. ?fpu ? floating-point unit: a subblock included in the core for implementing the floating point instruction set in hard- ware. ?nvic ? nested vectored interrupt controller subblock. accepts external interrupt inputs. see documents arm limited: arm?v7-m architecture reference manual, ddi0403d, november 2010 and arm? generic interrupt controller architecture version 1.0 architecture specification, ihi0048a, september 2008 . ?fpb ? flash patch breakpoint subblock. provides either rem apping (address substitution) or breakpointing (excep- tion or halt) for a set of instruction addresses and data addresses. see section 8.3 of arm limited: cortex?-m4 technical reference manual, ddi0439c, 29 june 2010 . ? dap ? debug access port, a subblock consisting of dp and ap subblocks ?dp ? any of the ports in the dap subblock for connection to an off-chip debugger. a single swj-dp option is currently selected for this function, providing jtag connectivity. ?swj-dp ?serial wire / jtag debug port, the dp option selected by microchip for the dap . ?ap ? any of the ports on the dap subblock for accessing on-chip resources on behalf of the debugger, independent of processor operations. a single ahb-ap option is currently selected for this function. ?ahb-ap ? ahb access port, the ap option selected by microchip for the dap . ?mem-ap ? a generic term for an ap that connects to a memory-mapped bus on-chip. for this product, this term is synony- mous with the ahb access port, ahb-ap . ? rom table ? a rom-based data structure in the debug section that al lows an external debugger an d/or a fw monitor to deter- mine which of the debug features are present. ?dwt ? data watchdog and trace subblock. this contains comparators and counters used for data watchpoints and core activity tracing. ?etm ? embedded trace macrocell subblock. provides enhancem ents for trace output reporting, mostly from the dwt subblock. it adds enhanced instruction tracing, filtering, triggering and timestamping. ?itm ? instrumentation trace macrocell subblock. provides a hw trace interface for ?printf?-style reports from instru- mented firmware builds, with timestamping also provided. ?tpiu ? trace port interface unit subblock. multiplexes and buffers trace reports from the etm and itm subblocks. ?tpa ? trace port analyzer: any off- chip device that uses the tpiu output. ?atb
? 2014 - 2015 microchip technology inc. ds00001719d-page 105 MEC1322 ? interface standard for trace data to the tpiu from etm and/or itm blocks, defined in amba 3 . see arm limited: amba? 3 atb protocol specification, ihi0032a, 19 june 2006 . ?amba ? the collective term for bus standards originated by arm limited. ? amba 3 defines the ip?s ahb-lite and atb bus interfaces. ? amba 2 (amba rev. 2.0) defines the ec?s ahb bus interface. ?ahb ? advanced high-performance bus, a system-level on-chip amba 2 bus standard. see arm limited: amba? specification (rev 2.0), ihi0011a, 13 may 1999 . ?ahb-lite ? a single-master subset of the ahb bus standard: defined in the amba 3 bus standard. see arm limited: amba? 3 ahb-lite protocol specification, ihi0033a, 6 june 2006 . ? ppb ? private peripheral bus: a specific apb bus with local connect ivity within the ec. ? apb ? advanced peripheral bus, a limited 32-bit-only bus defined in amba 2 for i/o register accesses. this term is rele- vant only to describe the ppb bus internal to the ec core. see arm limited: amba? specification (rev 2.0), ihi0011a, 13 may 1999 . ?mpu ? memory protection unit. this is an optional subblock that is not currently included . ?htm ? ahb trace macrocell. this is an optional subblock that is not currently included . ?wic ? wake-up interrupt controller. this is an optional subblock that is not currently included . 7.3.2 microchip terms and acronyms ? pmu ? this processor memory unit is a module that may be pres ent at the chip level containing any memory resources that are closely-coupled to the MEC1322 ec. it manages accesses from both the ec processor and chip-level bus masters. ? interrupt aggregator ? this is a module that may be present at the chip level, which can combine multiple interrupt sources onto single interrupt inputs at the ec, causing them to share a vector. 7.4 arm m4f ip interfaces this section defines only the interfaces to the arm ip itself. for the interfaces of the entire block, see section 7.5, "block external interfaces," on page 107 . the MEC1322 ip has the following major external interfaces, as shown in figure 7-1: arm m4f based embedded controller i/o block diagram on page 107 : ? icode ahb-lite interface ? dcode ahb-lite interface ? system ahb-lite interface ? debug (jtag) interface ? trace port interface ? interrupt interface the ec operates on the model of a single 32-bit addressing space of byte addresses (4gbytes, von neumann archi- tecture) with little-endian byte ordering. on the basis of an internal decoder (part of the bus matrix shown in figure 7- 1 ), it routes read/write/fetch accesses to one of three external interfaces, or in some cases internally (shown as the ppb interface).
MEC1322 ds00001719d-page 106 ? 2014 - 2015 microchip technology inc. the ec executes instructions out of closely-coupled memory via the icode interface. data accesses to closely-coupled memory are handled via the dcode interface. the ec accesses the rest of the on-chip address space via the system ahb-lite interface. the debugger program in the host c an probe the ec and all ec addressable memory via the jtag debug interface. aliased addressing spaces are provided at the chip level so that specific bus interfaces can be selected explicitly where needed. for example, the ec?s bit banding feature uses the system ahb-lite bus to access resources normally accessed via the dcode or icode interface.
? 2014 - 2015 microchip technology inc. ds00001719d-page 107 MEC1322 7.5 block external interfaces figure 7-1: arm m4f based embedde d controller i/o block diagram icode interface (ahb-lite) dcode interface (ahb-lite) system interface (ahb-lite) nvic nested vectored interrupt controller tpiu trace port interface arm_m4f ip chip-level system bus (amba 2 ahb) processor core w/ fpu misc. sideband dap debug access port mux chip-level jtag tap etm / itm trace outputs debug host amba 2 ahb adapt memory bus adapt memory bus adapt pmc block (ram / rom) data port code port ahb port arm_m4f ec block interrupt aggregator grouped (summary) interrupts directly vectored connections interrupts optionally grouped inputs unconditionally grouped inputs processor clock divider chip-level clock pulse sync & stretch clock gate processor reset core reset (por)
MEC1322 ds00001719d-page 108 ? 2014 - 2015 microchip technology inc. 7.6 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 7.6.1 power domains 7.6.2 clock inputs 7.6.2.1 basic clocking the basic clocking comes from a free-running clock signal provided from the chip level. 7.6.2.2 system tick clocking the system tick clocking is controlled by a signal from chip-level logic. it is the 48 mhz ring oscillator divided by the following: -(( processor clock divide value )x2)+1. 7.6.2.3 debug jtag clocking the debug jtag clocking comes from chip-level logic, which may multiplex or gate this clock. see section 7.9.3, "debugger access support," on page 111 . 7.6.2.4 trace clocking the clock for the trace interface is identical to the 48 mhz ring oscillator input. 7.6.3 resets the reset interface from the chip level is given below. 7.7 interrupts the arm m4f based embedded controller is equipped with an interrupt interface to respond to interrupts. these inputs go to the ip?s nvic block after a small amount of hardware processing to ensure their detection at varying clock rates. see figure 7-1: arm m4f based embedded controller i/o block diagram on page 107 . as shown in figure 7-1 , an interrupt aggregator block may exist at the chip level, to allow multiple related interrupts to be grouped onto the same nvic input, and so allowing them to be serviced using the same vector. this may allow the same interrupt handler to be invoked for a group of related interrupt inputs. it may also be used to expand the total num- ber of interrupt inputs that can be serviced. connections to the chip-level system are given in table 15-3, ?interrupt event aggregator routing summary,? on page 195 . the nmi (non-maskable interrupt) connection is tied off and not used. table 7-1: power sources name description vcc1 the arm m4f based embedded controller is powered by vcc1 . table 7-2: clock inputs name description 48 mhz ring oscillator the ec clock derived from the 48 mhz ring oscillator is the clock source to the arm m4f based embedded controller . division of the clock rate is allowed, according to the processor clock enable. note: the ec clock is controlled from the chip-level power, clocks, and reset (pcr) circuitry. see section 3.9.8, "processor clock control register (proc_clk_cntrl)," on page 61 . table 7-3: reset signals name description ec_proc_ reset the arm m4f based embedded controller is reset by ec_proc_ reset .
? 2014 - 2015 microchip technology inc. ds00001719d-page 109 MEC1322 7.7.1 nvic interrupt interface the nvic interrupt unit can be wired to up to 240 interrupt inputs from the chip level. the interrupts that are actually connected from the chip level are defined in table 15-3, ?interrupt event aggregator routing summary,? on page 195 . all nvic interrupt inputs can be programmed as either puls e or level triggered. they can also be individually masked, and individually assigned to their own hardware-managed priority level. 7.7.2 nvic relationship to exc eption vector table entries the vector table consists of 4-byte entries, one per vector. entry 0 is not a vector, but provides an initial reset value for the main stack pointer. vectors start with the reset vector, at entry #1. entries up through #15 are dedicated for internal exceptions, and do not involve the nvic. nvic entries in the vector table start with entry #16, so that nvic interrupt #0 is at entry #16, and all nvic interrupt numbers are incremented by 16 before accessing the vector table. the number of connections to the nvic determines the nece ssary minimum size of the vector table, as shown below. it can extend as far as 256 entries (255 vectors, plus the non-vector entry #0). a vector entry is used to load the program counter (pc) a nd the epsr.t bit. since the program counter only expresses code addresses in units of two-byte halfwords, bit[0] of the vector location is used to load the epsr.t bit instead, select- ing thumb mode for exception handling. bit[0] must be ?1? in all vectors, otherwise a usagefault exception will be posted (invstate, unimplemented instruction set). if the reset ve ctor is at fault, the exception posted will be hardfault instead. table 7-4: exception and interrupt vector table layout table entry exception number exception special entry for reset stack pointer 0 (none) holds reset value for the main stack pointer. not a vector. core internal exception vectors start here 1 1 reset vector (pc + epsr.t bit) 2 2 nmi (non-maskable interrupt) vector 33hardfault vector 4 4 memmanage vector 55busfault vector 6 6 usagefault vector 7 (none) (reserved by arm ltd.) 8 (none) (reserved by arm ltd.) 9 (none) (reserved by arm ltd.) 10 (none) (reserved by arm ltd.) 11 11 svcall vector 12 12 debug monitor vector 13 (none) (reserved by arm ltd.) 14 14 pendsv vector 15 15 systick vector nvic interrupt vectors start here 16 16 nvic interrupt #0 vector . . . . . . . . . n + 16 n + 16 nvic interrupt #n vector . . . . . . . . .
MEC1322 ds00001719d-page 110 ? 2014 - 2015 microchip technology inc. 7.8 low power modes the arm processor low power modes are handled through the power, clocks, and resets registers, not directly through the arm core registers. see section 3.7, "chip power management features," on page 54 . the arm processor can enter sleep or deep sleep mode inter nally. this action will cause an output signal clock required to be turned off, allowing clocks to be stopped from the chip level. however, clock required will still be held active, or set to active, unless all of the following conditions exist: ? no interrupt is pending. ? an input signal sleep enable from the chip level is active. ? the debug jtag port is inactive (reset or configured not present). in addition, regardless of the above conditions, a chip-level input signal force halt may halt the processor and remove clock required. 7.9 description 7.9.1 bus connections there are three bus connections used from MEC1322 ec blo ck, which are directly related to the ip bus ports. see fig- ure 7-1: arm m4f based embedded controller i/o block diagram on page 107 . for the mapping of addresses at the chip level, see chapter 2.0, "block overview," on page 45 . 7.9.1.1 closely coupled instruction fetch bus as shown in figure 7-1 , the ahb-lite icode port from the ip is conv erted to a more conventional sram memory-style bus and connected to the on-chip memory resources with routing priority appropriate to instruction fetches. 7.9.1.2 closely coupled data bus as shown in figure 7-1 , the ahb-lite dcode port from the ip is conv erted to a more conventional sram memory-style bus and connected to the on-chip memory resources with routi ng priority appropriate to fast data read/write accesses. 7.9.1.3 chip-level system bus as shown in figure 7-1 , the ahb-lite system port from the ip is conver ted from ahb-lite to fully arbitrated multi-master capability (the amba 2 defined ahb bus: see arm limited: amba? specification (rev 2.0), ihi0011a, 13 may 1999 ). using this bus, all addressable on-chip resources are availabl e. the multi-mastering capability supports the microchip dma and emi features if present, as well as the bit-banding feature of the ip itself. as also shown in figure 7-1 , the closely-coupled memory resources are also available through this bus connection using aliased addresses. this is required in order to allow bit banding to be used in these regions, but it also allows them to be accessed by dma and other bus masters at the chip level. application note: registers with properties such as write-1-to -clear (w1c), read-to-clear and fifos need to be handled with appropriate care when being used with the bit band alias addressing scheme. accessing such a regist er through a bit band alias address will cause the hardware to perform a read-modify-write, and if a w1c-type bit is set, it will get cleared with such an access. for example, using a bit band access to the interrupt aggregator, including the interrupt enables and block interrupt status to clear an irq will clear all active irqs. max + 16 max + 16 nvic interrupt #max vector (highest-numbered nvic connection.) . . . . . . . table size may (but need not) extend further. . . 255 255 nvic interrupt #239 (architectural limit of exception table) table 7-4: exception and interrupt vector table layout (continued) table entry exception number exception
? 2014 - 2015 microchip technology inc. ds00001719d-page 111 MEC1322 7.9.2 instruction pipelining there are no special considerations exce pt as defined by arm documentation. 7.9.3 debugger access support an external debugger accesses the chip through a jtag standard interface. the debugger itself, however, is not an arm product, and its capabilities will depend on the third-party product selected for code development and debug. as shown in figure 7-1: arm m4f based embedded controller i/o block diagram on page 107 , there may be other resources at the chip level that share the jtag port pins; for example chip-level boundary scan. see section 1.4.4, "jtag interface," on page 15 for configuring the jtag pins at the chip level for debug purposes. 7.9.3.1 debug and access ports (swj-dp and ahb-ap subblocks) these two subblocks work together to provide access to th e chip for the debugger usin g the debug jtag connection, as described in chapter 4 of the arm limited: arm? debug interface v5 architecture specification, ihi0031a, 8 feb- ruary 2006 . 7.9.4 breakpoint, watchp oint and trace support see arm limited: arm? debug interface v5 architec ture specification, ihi0031a, 8 february 2006 and also arm lim- ited: arm? debug interface v5 architecture specification adiv5.1 supplement, dsa09-prdc-008772, 17 august 2009 . a summary of functionality follows. breakpoint and watchpoint facilities can be programmed to do one of the following: ? halt the processor. this means that the external debugger will detect the event by periodically polling the state of the ec. ? transfer control to an internal debug monitor firmware routine, by triggering the debug monitor exception (see table 7-4, ?exception and interrupt vector table layout,? on page 109 ). 7.9.4.1 instrumentation support (itm subblock) the instrumentation trace macrocell (itm) is for profiling software. this uses n on-blocking register accesses, with a fixed low-intrusion overhead, and can be added to a real-t ime operating system (rtos), application, or exception handler. if necessary, product code can retain the regi ster access instructions, avoiding probe effects. 7.9.4.2 hw breakpoints and rom patching (fpb subblock) the flash patch and breakpoint (fpb) block. this block can remap sections of rom, typically flash memory, to regions of ram, and can set breakpoints on code in rom. this block can be used for debug, and to provide a code or data patch to an application that requires field updates to a product in rom. 7.9.4.3 data watchpoints and trace (dwt subblock) the debug watchpoint and trace (dwt) block provides watc hpoint support, program counter sampling for performance monitoring, and embedded trace trigger control. 7.9.4.4 trace interface (etm and tpiu) the embedded trace macrocell (etm) provides instruction traci ng capability. for details of functionality and usage, see also arm limited: embedded trace macrocell? (etmv1.0 to et mv3.5) architecture specification, ihi0014q, 23 sep- tember 2011 and arm limited: coresight? etm?-m4 technical reference manual, ddi0440c, 29 june 2010 . the trace port interface unit (tpiu) provides th e external interface for the itm, dwt and etm. see section 1.4.16, "trace debug interface," on page 19 for configuring the trace pins at the chip level for trace output. 7.10 arm configuration in order to function correctly, it is necessary to set the ar m auxiliary control register (actlr), located at address 0xe- 000e008, to 0x02. this sets bit[1], disdefwbuf, to 1. this must be done as soon as possible after power on reset, or register corruption may occur.
MEC1322 ds00001719d-page 112 ? 2014 - 2015 microchip technology inc. 8.0 ram and rom sram the 128kbytes sram (code or data) is allocated as follows: ? 96k optimized for code ? 32k optimized for data. the distinction between ?96kb optimized for instructions? and ?32kb optimized for data? srams: is as follows: the MEC1322 has two blo cks of sram, one of 96kb and one of 32kb. both can be used for either instructions or data. as long as the arm fetches instructions from one sram and does loads and stores to the other, code and data accesses operate in parallel and there are no wait states. if on the same cycle the arm fetches an instruction and does a load or a store to the same sram, either the code fe tch will be delayed by one cycle or the data access will be delayed by one cycle. the 96kb sram is opt imized for instructions, in that if the arm accesses this sram for both instructions and data on the same cycle, the instruction fetch will complete in one cycle and the load/store will be delayed for one cycle. the 32kb sram is optimized for data, in that if the arm acce sses this sram for both instructions and data on the same cycle, the load/store will complete in once cycle and the instruction fetch will be delayed for one cycle. in both cases, t he sram arbiter ensures that the arbitr ation loser will wi n on subsequent cycles and thus will not be locked out of the sram indefinitely. user applications, therefore, are free to allocate code and data anywhere in the 128kb sram address space, except that th ere will be an occasional small performance hit if both code and data are allocated in the same sram. the application loader in the MEC1322 rom requires the top 8kb of the 32kb sram in order to perform its functions. the user can therefore load a maximum of 120kb into sram using the rom loader. once the rom application loader has completed its operation, the entire 128kb address space ca n be allocated to whatever functions, code or data, the user wishes. the sram is located at ec base address 00100000h in 32-bit internal address space. rom the 32kbyte boot rom is located at ec base ad dress 00000000h in 32-bit internal address space. the memory map of the ram and rom is represented as follows: note: 120kbytes are available for application code as follo ws: 96k optimized for code, 24k optimized for data. note: 120kb is available for application code in the address range 00100000h to 0011dfffh note: 30kb is available for application code in the address range 00000000h to 000077ffh
? 2014 - 2015 microchip technology inc. ds00001719d-page 113 MEC1322 figure 8-1: memory layout 32kb data ram 96kb code ram 32kb boot rom 0x0000_0000 0x0010_0000 0x0011_8000 0x0000_7fff 0x0011_7fff 0x0011_ffff 0x2000_0000 0x2000_7fff 0x4000_0000 0x4010_3fff 32kb alias data ram spb 1mb data ram reserved for arm bit band alias region 0x2200_0000 0x220f_ffff arm access only arm access only host read access host access host access host access
MEC1322 ds00001719d-page 114 ? 2014 - 2015 microchip technology inc. 9.0 embedded memory interface (emi) 9.1 introduction the embedded memory interface (emi) provides a standard run-time mechanism for the system host to communicate with the embedded controller (ec) and other logical comp onents. the embedded memory interface includes 13 byte- addressable registers in the host?s address space, as well as 22 bytes of registers that are accessible only by the ec. the embedded memory interface can be used by the host to access bytes of memory designated by the ec without requiring any assistance from the ec. the ec may configur e these regions of memory as read-only, write-only, or read/write capable. 9.2 interface this block is designed to be accessed externally and internally via a register interface. 9.3 signal description there are no external signals associated with this block. 9.4 host interface the registers defined for the embedded memory interface (emi) are accessible by the system host and the embedded controller as indicated in section 9.10, "ec-only registers" and section 9.9, "runtime registers" . figure 9-1: i/o diagram of block embedded memory interface (emi) signal description clock inputs interrupts resets host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 115 MEC1322 9.5 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 9.5.1 power domains 9.5.2 clock inputs this block has no special clocking requirements. host regi ster accesses are synchronized to the host bus clock and ec register accesses are synchronized to the ec bus clock, ther eby allowing the transactions to complete in one bus clock. 9.5.3 resets 9.6 interrupts this section defines the interrupt sources generated from this block. 9.7 low power modes the embedded memory interface (emi) automatically enters low power mode when no transaction target it. table 9-1: power sources name description vcc1 the logic and registers implemented in this block reside on this single power well. table 9-2: reset signals name description vcc1_reset this reset signal resets all the logic and register in this block. table 9-3: system interrupts source description host event this interrupt source for the sirq logic is generated when any of the ec_swi bits are asserted and the corresponding ec_swi_en bits are asserted as well. this event is also asserted if the host writes the ec-to-host mailbox register . ec-to-host this interrupt source for the sirq logic is generated by the host writing the ec-to-host mailbox register . table 9-4: ec interrupts source description host-to-ec interrupt source for the interr upt aggregator, generated by the host writ- ing the host-to-ec mailbox register .
MEC1322 ds00001719d-page 116 ? 2014 - 2015 microchip technology inc. 9.8 description the embedded memory interface (emi) is composed of a mailbox, a direct memory interface, and an application id register. the mailbox contains two registers, the host-to-ec mailbox register and the ec-to-host mailbox register , that act as a communication portal between the system host and the embedded controller. when the host-to-ec mailbox reg- ister is written an interrupt is generated to the embedded controller. similarly, when the ec-to-host mailbox register is written an interrupt is generated to the system host. the source of the system host interr upt may be read in the inter- rupt source register. these interrupt events may be individu ally prevented from generating a host event via the inter- rupt mask register. the direct memory interface, which is composed of a byte addressable 16-bit ec address register and a 32-bit ec data register, permits the host to read or write a portion of the ec?s internal address space. the embedded controller may enable up to two regions of the ec?s internal addre ss space to be exposed to the system host. the system host may access these memory locations without intervention or assistance from the ec. the embedded memory interface can be configured so that data transfers between the embedded memory interface data bytes and the 32- bit internal address space may be multiple bytes, while host i/o is always executed a byte at a time. when the host reads one of the four bytes in the embedded memory interface data register, data from the internal 32- bit address space, at the address defined by the embedded memory interface address register, is returned to the host. this read access will load 1, 2, or 4 bytes into the data register depending on the configuration of the access_type bits. similarly, writing one of the four bytes in the data re gister will write the corresponding byte(s) from the data register into the internal 32-bit address space as indicated by the access_type bits. this configuration option is done to ensure that data the ec treats as 16-bit or 32-bit will be consistent in the host, even though one byte of the data may change between two or more 8-bit accesses by the host. in addition, there is an auto-increment function for the embedded memory interface address register. when enabled, the host can read or write bl ocks of memory in the 32- bi t internal address space by re peatedly accessing the embedded memory interface data register, without requiring host updates to the embedded memory interface address register. finally, the application id register may be used by the host to provide an arbitration mechanism if more than one soft- ware thread requires access through the emi interface. see section 9.8.4, "embedded memory interface usage," on page 118 for more details. figure 9-2: embedded memo ry interface block diagram host-to-ec ec-to-host memory region 0 & memory region 1 host ec host-to-ec event ec-to-host event host interrupt source embedded memory address embedded memory data addr addr data data emi host event
? 2014 - 2015 microchip technology inc. ds00001719d-page 117 MEC1322 9.8.1 embedded memory map each embedded memory interface provides direct access fo r the host into two windows in the ec 32-bit internal address space. this mapping is shown in figure 9-3, "embedded memory addressing": figure 9-3: embedded memory addressing the base addresses, the read limits and the write limits are de fined by registers that are in the ec address space and cannot be accessed by the host. in each region, the read limit need not be greater than the write limit. the regions can be contiguous or overlapping. for example, if the region 0 read limit is set to 0 and the write limit is set to a positive number, then the embedded memory interface defines a region in the ec memory that the ec can read and write but is write-only for the host. this might be useful for storage of security data, which the host might wish to send to the ec but should not be readable in the event a virus invades the host. each window into the ec memory can be as large as 32k bytes in the 32-bit internal address space. see figure 8-1: memory layout on page 113 for host accessible regions. 32-bit internal address space 0000_0000h ffff_ffffh region_0_base_address region_0_write_limit region_0_read_limit host read/write host read only no host access no host access region_1_base_address region_1_write_limit region_1_read_limit host read/write host read only no host access
MEC1322 ds00001719d-page 118 ? 2014 - 2015 microchip technology inc. 9.8.2 ec data register the 4 1-byte ec data byte registers function as a 32-bit register, which creates a 4 byte window into the memory region being accessed. the 4-byte window is always aligned on a 4-byte boundary. depending on the read/write con- figuration of the memory region being accessed, the bytes ma y be extracted from or loaded into memory as a byte, word, or a dword. the access_type determines the size of the memory access. the address accessed is deter- mined by the two ec_address byte registers, which t ogether function as a 15-bit ec address register. ? a write to the ec data register when the ec address is in a read-only or a no-access region, as defined by the memory base and limit regi sters, will updat e the ec data register but me mory will not be modified. ? a read to the ec data register when the ec address is in a no-access region, as defined by the memory base and limit registers, will not trigger a memory read and will not modify the ec data register. in auto-increment mode ( access_type =11b), reads of byte 3 of th e ec data register will still trigger in crements of the ec address register when the address is out of bounds, while writes of byte 3 will not. 9.8.3 access types the access type field ( access_type in the ec address lsb register ) defines the type of host access that occurs when the ec data register is read or written. 11: auto-increment 32-bit access. this defines a 32-bit access, as in the 10 case. in addition, any read or write of byte 3 in the ec data register causes the ec data re gister to be incremented by 1. that is, the ec_address field will point to the next 32-bit double word in the 32- bit internal address space. 10: 32-bit access. a read of byte 0 in the ec data register causes the 32 bits in the 32- bit internal address space at an offset of ec_address to be loaded into the entire ec data register. the read then returns the contents of byte 0. a read of byte 1, byte 2 or byte 3 in the ec data register returns the contents of the register, without any update from the 32- bit internal address space. a write of byte 3 in the ec data register causes the ec da ta register to be written into the 32 bits in the 32- bit internal address space at an offset of ec_address. a writ e of byte 0, byte 1 or byte 2 in the ec data register updates the contents of the register, without any change to the 32- bit internal address space. 01: 16-bit access. a read of byte 0 in the ec data register causes the 16 bits in the 32- bit internal address space at an offset of ec_address to be loaded into byte 0 and byte 1 of the ec data register. the read then returns the contents of byte 0. a read of byte 2 in the ec data r egister causes the 16 bits in the 32- bit internal address space at an offset of ec_address+2 to be loaded into byte 2 and byte 3 of the ec data register. the read then returns the contents of byte 2. a read of byte 1 or byte 3 in the ec data register return the contents of the reg- ister, without any update from the 32- bit internal address space. a write of byte 1 in the ec data register causes bytes 1 and 0 of the ec data register to be written into the 16 bits in the 32- bit internal address space at an offset of ec_address. a write of byte 3 in the ec data register causes bytes 3 and 2 of the ec data register to be writte n into the 16 bits in the 32- bit internal address space at an offset of ec_address+2. a write of byte 0 or byte 2 in the ec data register updates the contents of the register, without any change to the 32- bit internal address space. 00: 8-bit access. any byte read of byte 0 through byte 3 in the ec data register causes the corresponding byte within the 32-bit double word addressed by ec_address to be loaded into the byte of ec data register and returned by the read. any byte write to byte 0 through byte 3 in the ec data register writes the corresponding byte within the 32-bit double word addressed by ec_address, as well as the byte of the ec data register. 9.8.4 embedded memory interface usage the embedded memory interface provides a generic facility for communication between the host and the ec and can be used for many functions. some examples are: ? virtual registers. a block of memory in the 32-bit inter nal address space can be used to implement a set of virtual registers. the host is given direct read-only access to this address space, referred to as peek mode. the ec may read or write this memory as needed. ? program downloading. because the instruction closely c oupled memory is implemented in the same 32-bit inter- nal address space, the embedded memory interface can be used by the host to download new program seg- ments for the ec in the upper 32kb sram. the read/write window would be configured by the host to point to the beginning of the loadable program region, which could then be loaded by the host. ? data exchange. the read/write portion of the memory window can be used to contain a communication packet. the host, by default, ?owns? the packet, and can write it at any time. when the host wishes to communicate with the ec, it sends the ec a command, through the host-to-ec message facility, to read the packet and perform
? 2014 - 2015 microchip technology inc. ds00001719d-page 119 MEC1322 some operations as a result. when it is completed processing the packet, the ec can inform the host, either through a message in the ec-to-host channel or by triggering an event such as an smi directly. if return results are required, the ec can write the results into the read/wri te region, which the host can read directly when it is informed that the ec has completed processing. depending on the command, the operations could entail update of virtual registers in the 32-bit internal address space, re ads of any register in the ec address space, or writes of any register in the ec address space. because there are two regions that are defined by the base registers, the memory used for the communication packet does not have to be contiguous with a set of virtual registers. because there are two embedded memory interface memory regions, the embedded memory interface cannot be used for more than two of these functions at a time. the host can request that the ec switch from one function to another through the use of the host-to-ec mailbox register. the application id register is provided to help software applications track ownership of an embedded memory inter- face. an application can write the register with its application id, then immediately read it back. if the read value is not the same as the value written, then another application has ownership of the interface. 9.9 runtime registers the registers listed in the runtime register summary table are for a single instance of the emi. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the runtime register base address table. note 9-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. note: the protocol used to pass commands back and forth through the embedded memory interface registers interface is left to the system designer. microchip can provide an application example of working code in which the host uses the embedded memory interface registers to gain access to all of the ec registers. table 9-5: runtime regi ster base address table block instance instance number host address space base address ( note 9-1 ) emi 0 ec 32-bit internal address space 400f_0000h emi 0 lpc i/o programmed bar table 9-6: runtime register summary offset register name (mnemonic) 00h host-to-ec mailbox register 01h ec-to-host mailbox register 02h ec address lsb register 03h ec address msb register 04h ec data byte 0 register 05h ec data byte 1 register 06h ec data byte 2 register 07h ec data byte 3 register 08h interrupt source lsb register 09h interrupt source msb register 0ah interrupt mask lsb register 0bh interrupt mask msb register 0ch application id register
MEC1322 ds00001719d-page 120 ? 2014 - 2015 microchip technology inc. 9.9.1 host-to-ec mailbox register 9.9.2 ec-to-host mailbox register 9.9.3 ec address lsb register offset 00h bits description type default reset event 7:0 host_ec_mbox 8-bit mailbox used communicate information from the system host to the embedded controller. writing this register generates an event to notify the embedded controller. the embedded controller has the option of clearing some or all of the bits in this register. this is dependent on the protocol layer imple- mented using the emi mailbox. the host must know this protocol to determine the meaning of the value that will be reported on a read. this bit field is aliased to the host_ec_mbox bit field in the host-to-ec mailbox register r/w 0h vcc1_r eset offset 01h bits description type default reset event 7:0 ec_host_mbox 8-bit mailbox used communicate information from the embedded controller to the system host. writin g this register generates an event to notify the system host. the system host has the option of clea ring some or all of the bits in this register. this is dependent on the protocol layer implemented using the emi mailbox. the embedded controller must know this pro- tocol to determine the meaning of the value that will be reported on a read. this bit field is aliased to the ec_host_mbox bit field in the ec-to- host mailbox register r/wc 0h vcc1_r eset offset 02h bits description type default reset event 7:2 ec_address_lsb this field defines bits[7:2] of ec_address [15:0]. bits[1:0] of the ec_address are always forced to 00b. the ec_address is aligned on a dword boundary. it is the address of the memory being accessed by ec data byte 0 register , which is an offset from the programmed base address of the selected region . r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 121 MEC1322 9.9.4 ec address msb register 9.9.5 ec data byte 0 register 1:0 access_type this field defines the type of access that occurs when the ec data register is read or written. 11b=auto-increment 32-bit access. 10b=32-bit access. 01b=16-bit access. 00b=8-bit access. each of these access types are defined in detail in section 9.8.3, "access types" . r/w 0h vcc1_r eset offset 03h bits description type default reset event 7region the field specifies which of two segments in the 32-bit internal address space is to be accessed by the ec_address[14:2] to gener- ate accesses to the memory. 1= the address defined by ec_address[14:2] is relative to the base address specified by the memory base address 1 register. 0= the address defined by ec_address[14:2] is relative to the base address specified by the memory base address 0 register. r/w 0h vcc1_r eset 6:0 ec_address_msb this field defines bits[14:8] of ec_address. bits[1:0] of the ec_ad- dress are always forced to 00b. the ec_address is aligned on a dword boundary. it is the address of the memory being accessed by ec data byte 0 register , which is an offset from the programmed base address of the selected region . r/w 0h vcc1_r eset offset 04h bits description type default reset event 7:0 ec_data_byte_0 this is byte 0 (least significant byte) of the 32-bit ec data register . use of the data byte registers to access ec memory is defined in detail in section 9.8.2, "ec data register" . r/w 0h vcc1_r eset offset 02h bits description type default reset event
MEC1322 ds00001719d-page 122 ? 2014 - 2015 microchip technology inc. 9.9.6 ec data byte 1 register 9.9.7 ec data byte 2 register 9.9.8 ec data byte 3 register 9.9.9 interrupt sour ce lsb register offset 05h bits description type default reset event 7:0 ec_data_byte_1 this is byte 1 of the 32-bit ec data register . use of the data byte registers to access ec memory is defined in detail in section 9.8.2, "ec data register" . r/w 0h vcc1_r eset offset 06h bits description type default reset event 7:0 ec_data_byte_2 this is byte 2 of the 32-bit ec data register . use of the data byte registers to access ec memory is defined in detail in section 9.8.2, "ec data register" . r/w 0h vcc1_r eset offset 07h bits description type default reset event 7:0 ec_data_byte_3 this is byte 3 (most significant byte) of the 32-bit ec data register . use of the data byte registers to access ec memory is defined in detail in section 9.8.2, "ec data register" . r/w 0h vcc1_r eset offset 08h bits description type default reset event 7:1 ec_swi_lsb ec software interrupt least significa nt bits. these bits are software interrupt bits that may be set by the ec to notify the host of an event. the meaning of these bits is dependent on the firmware implemen- tation. each bit in this field is cleared when written with a ?1b?. the ability to clear the bit can be disabled by the ec if the corresponding bit in the host clear enable register is set to ?0b?. this may be used by firm- ware for events that cannot be cleared while the event is still active. r/wc 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 123 MEC1322 9.9.10 interrupt source msb register 9.9.11 interrupt mask lsb register 9.9.12 interrupt mask msb register 0ec_wr ec mailbox write. this bit is set when the ec-to-host mailbox register has been written by the ec at offset 01h of the ec-only registers. note: there is no corresponding mask bit in the interrupt mask lsb register r0h vcc1_r eset offset 09h bits description type default reset event 7:0 ec_swi_msb ec software interrupt most significant bits. these bits are software interrupt bits that may be set by the ec to notify the host of an event. the meaning of these bits is dependent on the firmware implemen- tation. each bit in this field is cleared when written with a ?1b?. the ability to clear the bit can be disabled by the ec. if the corresponding bit in the host clear enable register is set to ?0b?. this may be used by firm- ware for events that cannot be cleared while the event is still active. r/wc 0h vcc1_r eset offset 0ah bits description type default reset event 7:1 ec_swi_en_lsb ec software interrupt enable least significant bits. each bit that is set to ?1b? in this field enables the generation of a host event inter- rupt by the corresponding bit in the ec_swi field in the interrupt source lsb register . r/w 0h vcc1_r eset 0 mchp reserved r/w 0h vcc1_r eset offset 0bh bits description type default reset event 7:0 ec_swi_en_msb ec software interrupt enable most significant bits. each bit that is set to ?1b? in this field enables the generation of a host event inter- rupt by the corresponding bit in the ec_swi field in the interrupt source msb register . r/w 0h vcc1_r eset offset 08h bits description type default reset event
MEC1322 ds00001719d-page 124 ? 2014 - 2015 microchip technology inc. 9.9.13 application id register 9.10 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the embedded memory interface (emi) . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 9.10.1 host-to-ec mailbox register offset 0ch bits description type default reset event 7:0 application_id when this field is 00h it can be written with any value. when set to a non-zero value, writing that value will clear this register to 00h. when set to a non-zero value, writing any value other than the cur- rent contents will have no effect. r/w 0h vcc1_r eset block instance instance number host address space base address emi 0 ec 32-bit internal address space 400f_0100h offset register name (mnemonic) 00h host-to-ec mailbox register 01h ec-to-host mailbox register 04h memory base address 0 register 08h memory read limit 0 register 0ah memory write limit 0 register 0ch memory base address 1 register 10h memory read limit 1 register 12h memory write limit 1 register 14h interrupt set register 16h host clear enable register offset 00h bits description type default reset event 7:0 host_ec_mbox 8-bit mailbox used commun icate information from the system host to the embedded controller. writing this register generates an event to notify the embedded controller. the embedded controller has the option of clearing some or all of the bits in this register. this is dependent on the protocol layer imple- mented using the emi mailbox. the host must know this protocol to determine the meaning of the value that will be reported on a read. this bit field is aliased to the host_ec_mbox bit field in the host-to-ec mailbox register . r/wc 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 125 MEC1322 9.10.2 ec-to-host mailbox register 9.10.3 memory base address 0 register 9.10.4 memory read limit 0 register offset 01h bits description type default reset event 7:0 ec_host_mbox 8-bit mailbox used communicate information from the embedded controller to the system host. wr iting this register generates an event to notify the system host. the system host has the option of clearing some or all of the bits in this register. this is dependent on the protocol layer implemented using the emi mailbox. the embedded controller must know this protocol to determine the meaning of the value that will be reported on a read. this bit field is aliased to ec_host_mbox bit field in the ec-to- host mailbox register . r/w 0h vcc1_r eset offset 04h bits description type default reset event 31:2 memory_base_address_0 this memory base address defines the beginning of region 0 in the embedded controller?s 32-bit internal address space. memory allo- cated to region 0 is intended to be shared between the host and the ec. the region defined by this base register is used when bit 15 of the ec address register is 0. the access will be to a memory loca- tion at an offset defined by the ec_address relative to the beginning of the region defined by this register . therefore, a read or write to the memory that is triggered by the ec data register will occur at mem- ory_base_address_0 + ec_address. r/w 0h vcc1_r eset 1:0 reserved r - - offset 08h bits description type default reset event 15 reserved r - - 14:2 memory_read_limit_0 whenever a read of any byte in the ec data register is attempted, and bit 15 of ec_address is 0, the field ec_address[14:2] in the ec_address_register is compared to this field. as long as ec_ad- dress[14:2] is less than this field the ec_data_register will be loaded from the 24-bit internal address space. r/w 0h vcc1_r eset 1:0 reserved r - -
MEC1322 ds00001719d-page 126 ? 2014 - 2015 microchip technology inc. 9.10.5 memory write limit 0 register 9.10.6 memory base address 1 register 9.10.7 memory read limit 1 register offset 0ah bits description type default reset event 15 reserved r - - 14:2 memory_write_limit_0 whenever a write of any byte in ec data register is attempted and bit 15 of ec_address is 0, the field ec_address_msb in the ec_address register is compared to this field. as long as ec_ad- dress[14:2] is less than memory_write_limit_0[14:2] the addressed bytes in the ec data register will be written into the intern al 24-bit address space. if ec_address[14:2] is greater than or equal to the memory_write_limit_0[14:2] no writes will take place. r/w 0h vcc1_r eset 1:0 reserved r - - offset 0ch bits description type default reset event 31:2 memory_base_address_1 this memory base address defines the beginning of region 1 in the embedded controller?s 32-bit internal address space. memory allo- cated to region 1 is intended to be shared between the host and the ec. the region defined by this base register is used when bit 15 of the ec address register is 1. the access will be to a memory loca- tion at an offset defined by the ec_address relative to the beginning of the region defined by this register . therefore, a read or write to the memory that is triggered by the ec data register will occur at mem- ory_base_address_1 + ec_address. r/w 0h vcc1_r eset 1:0 reserved r - - offset 10h bits description type default reset event 15 reserved r - - 14:2 memory_read_limit_1 whenever a read of any byte in the ec data register is attempted, and bit 15 of ec_address is 1, the field ec_address in the ec_address_register is compared to this field. as long as ec_ad- dress is less than this value, the ec_data_register will be loaded from the 24-bit internal address space. r/w 0h vcc1_r eset 1:0 reserved r - -
? 2014 - 2015 microchip technology inc. ds00001719d-page 127 MEC1322 9.10.8 memory write limit 1 register 9.10.9 interrupt set register 9.10.10 host clear enable register offset 12h bits description type default reset event 15 reserved r - - 14:2 memory_write_limit_1 whenever a write of any byte in ec data register is attempted and bit 15 of ec_address is 1, the field ec_address[14:2] in the ec_ad- dress register is compared to this field. as long as ec_ad- dress[14:2] is less than memory_write_limit_1[14:2] the addressed bytes in the ec data register will be written into the internal 24-bit address space. if ec_address[14:2] is greater than or equal to the memory_write_limit_1[14:2] no writes will take place. r/w 0h vcc1_r eset 1:0 reserved r - - offset 14h bits description type default reset event 15:1 ec_swi_set ec software interrupt set. this register provides the ec with a means of updating the interrupt source registers. writing a bit in this field with a ?1b? sets the corresponding bit in the interrupt source register to ?1b?. writing a bit in this field with a ?0b? has no effect. reading this field returns the current contents of the interrupt source register. r/ws 0h vcc1_r eset 0 reserved r - - offset 16h bits description type default reset event 15:1 host_clear_enable when a bit in this field is ?0b?, the corresponding bit in the interrupt source register cannot be cleared by writes to the interrupt source register. when a bit in this field is ?1b?, the corresponding bit in the interrupt source register can be cleared when that register bit is written with a ?1b?. these bits allow the ec to control whether the status bits in the inter- rupt source register are based on an edge or level event. r/w 0h vcc1_r eset 0 reserved r - -
MEC1322 ds00001719d-page 128 ? 2014 - 2015 microchip technology inc. 10.0 acpi embedded controll er interface (acpi-eci) 10.1 introduction the acpi embedded controller interface (acpi-eci) is a host/ec message interface. the acpi specification defines the standard hardware and software communications interface between the os and an embedded controller. this inter- face allows the os to support a standard driver that c an directly communicate with the embedded controller, allowing other drivers within the system to communicate with and use the ec resources; for example, smart battery and aml code. the acpi embedded controller interface (acpi-eci) provides a four byte full duplex data interface which is a superset of the standard acpi embedded controller interface (acpi-eci) one byte data interface. the acpi embedded control- ler interface (acpi-eci) defaults to the standard one byte interface. the MEC1322 has two instances of the acpi embedded controller interface. 1. the ec host in ta b l e 1 0 - 8 and table 10-10 corresponds to the ec in the acpi specification. this interface is referred to elsewhere in this chapter as acpi_ec . 2. the lpc host in table 10-8 and table 10-10 corresponds to the ?system host interface to os? in the acpi specification. this interface is referr ed to elsewhere in this chapter as acpi_os . 10.2 references ? advanced configuration and power interface specificat ion, revision 4.0 june 16, 2009, hewlett-packard corpo- ration intel corporation microsoft corporation phoenix technologies ltd. toshiba corporation 10.3 terminology table 10-1: terminology term definition acpi_ec the ec host corresponding to the acpi specification interface to the ec. acpi_os the lpc host corresponding to the acpi specification interface to the ?sys- tem host interface to os?. acpi_os terminology is not meant to distinguish the acpi system man- agement from operating system but merely the hardware path upstream towards the cpu.
? 2014 - 2015 microchip technology inc. ds00001719d-page 129 MEC1322 10.4 interface this block is designed to be accessed externally and internally via a register interface. 10.5 signal description there are no external signals. 10.6 host interface the registers defined for the acpi embedded controller interface (acpi-eci) are accessible by the system host and the embedded controller as indicated in section 10.12, "runtime registers" and section 10.13, "ec-only registers" . 10.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 10.7.1 power domains 10.7.2 clock inputs this block only requires the host interfac e clocks to synchroni ze registers access. 10.7.3 resets figure 10-1: i/o diagram of block table 10-2: power sources name description vcc1 the logic and registers implemented in this block reside on this single power well. table 10-3: reset signals name description vcc1_reset vcc1_reset resets all the logic and registers in acpi embedded controller interface (acpi-eci) . acpi embedded controller interface (acpi-eci) interrupts power, clocks and reset host interface signal description
MEC1322 ds00001719d-page 130 ? 2014 - 2015 microchip technology inc. 10.8 interrupts this section defines the interrupt sources generated from this block. 10.9 low power modes the acpi embedded controller interface (acpi-eci) automatically enters low power mode when no transaction targets it. 10.10 description the acpi embedded controller interface (acpi-eci) provides an apci-ec interface that adheres to the acpi specifi- cation. the acpi embedded controller interface (acpi-eci) includes two modes of operation: legacy mode and four- byte mode . the acpi embedded controller interface (acpi-eci) defaults to legacy mode which provides single byte full duplex operation. legacy mode corresponds to the acpi specific ation functionality as illustrated in figure 10-2: on page 131 . the ec interrupts in figure 10-2: on page 131 are implemented as ec_obf & ec_ibf . see section 10.8, "inter- rupts," on page 130 . in four-byte mode , the acpi embedded controller interface (acpi-eci) provides four byte full duplex operation. four- byte mode is a superset of the ac pi specification functio nality as illustrated in figure 10-2: on page 131 . both legacy mode & four-byte mode provide full duplex communications which allows data/command transfers in one direction while maintaining data from the other direction; communications can flow both ways simultaneously. in legacy mode , acpi embedded controller interface (acpi-eci) contains three registers: acpi os command reg- ister , os status os register , and os2ec data ec byte 0 register . the standard acpi embedded controller inter- face (acpi-eci) registers occupy two addresses in the acpi_os space ( table 10-9 ). the os2ec data ec byte 0 register and acpi os command register registers appear as a single 8-bit data register in the acpi_ec . the cmd bit in the os status os register is used by the acpi_ec to discriminate commands from data written by the acpi_os to the acpi_ec . cmd bit is controlled by hardware: acpi_os writes to the os2ec data ec byte 0 register register clear the cmd bit; acpi_os writes to the acpi os command register set the cmd bit. table 10-4: system interrupts source description ec_obf ec_obf interrupt is asserted when the obf in the ec status register is cleared to ?0?. table 10-5: ec interrupts source description ec_obf ec_obf interrupt is asserted when the obf in the ec status register is cleared to ?0?. ec_ibf ec_ibf interrupt is asserted when the ibf in the ec status register is set to ?1?. note: the usage model from the acpi specification requires both smi?s and sci?s. the acpi_os smi & sci interrupts are not implemented in the acpi embedded controller interface (acpi-eci). the smi_evt and sci_evt bits in the os status os register are software flags and this block do not initiate smi or sci events.
? 2014 - 2015 microchip technology inc. ds00001719d-page 131 MEC1322 figure 10-2: block diag ram corresponding to the acpi specification legacy mode control register status command system host interface to os ec interrupts host smi & sci interrupts ec processor interface data single byte legend legacy smsc proprietary data single byte full duplex data flow in each direction indipendent
MEC1322 ds00001719d-page 132 ? 2014 - 2015 microchip technology inc. four-byte mode figure 10-2: block diagram correspo nding to the acpi specification status command system host interface to os ec interrupts host smi & sci interrupts ec processor interface data 0 2 1 3 data 0 2 1 3 full duplex data flow in each direction indipendent control register legend legacy smsc proprietary
? 2014 - 2015 microchip technology inc. ds00001719d-page 133 MEC1322 10.11 register aliasing between runtime and ec-only registers table 10-6, "runtime register aliasing into ec-only registers" indicates the aliasing from runtime registers to ec-only registers. the ?host/ec access? column distinguishes the aliasing based on access type. see individual register descriptions for more details. table 10-7, "ec-only registers summary" indicates the aliasing from ec-only to runtime registers. the ?host/ec access? column distinguishes the aliasing based on access type. see individual register descriptions for more details. table 10-6: runtime register al iasing into ec-only registers host offset runtime register register name (mnemonic) host access ec offset aliased ec-only register register name (mnemonic) ec access 00h acpi os data register byte 0 register w 108h os2ec data ec byte 0 register r 00h acpi os data register byte 0 register r 100h ec2os data ec byte 0 register w 01h acpi os data register byte 1 register w 109h os2ec data ec byte 1 register r 01h acpi os data register byte 1 register r 101h ec2os data ec byte 1 register w 02h acpi os data register byte 2 register w10ah os2ec data ec byte 2 register r 02h acpi os data register byte 2 register r 102h ec2os data ec byte 2 register w 03h acpi os data register byte 3 register w10bh os2ec data ec byte 3 register r 03h acpi os data register byte 3 register r 103h ec2os data ec byte 3 register w 04h acpi os command register w 108h os2ec data ec byte 0 register r 04h os status os register r 104h ec status register w 05h os byte control register r 105h ec byte control register r/w 06h reserved 106h reserved 07h reserved 107h reserved table 10-7: ec-only registers summary ec offset ec-only registers register name (mnemonic) ec access host offset aliased runtime register register name (mnemonic) host access 108h os2ec data ec byte 0 register r00h acpi os data register byte 0 register w 108h os2ec data ec byte 0 register r04h acpi os command register w 109h os2ec data ec byte 1 register r01h acpi os data register byte 1 register w 10ah os2ec data ec byte 2 register r02h acpi os data register byte 2 register w 10bh os2ec data ec byte 3 register r03h acpi os data register byte 3 register w 104h ec status register w04h os status os register w 105h ec byte control register r/w 05h os byte control register r 106h reserved r reserved r 107h reserved r reserved r 100h ec2os data ec byte 0 register w00h acpi os data register byte 0 register r
MEC1322 ds00001719d-page 134 ? 2014 - 2015 microchip technology inc. 10.12 runtime registers the registers listed in the runtime register summary table are for two instances of the acpi embedded controller interface (acpi-eci) . the addresses of each register listed in this t able are defined as a relative offset to the host ?base address? defined in the runtime register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance 10.12.1 acpi os data register byte 0 register this register is aliased; see acpi-os data bytes[3:0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 101h ec2os data ec byte 1 register w01h acpi os data register byte 1 register r 102h ec2os data ec byte 2 register w02h acpi os data register byte 2 register r 103h ec2os data ec byte 3 register w03h acpi os data register byte 3 register r note: the runtime registers may be accessed by the ec but typically the host will access the runtime registers and the ec will access just the ec-only registers. table 10-8: runtime register base address table block instance instance number host address space base address acpi-ec 0 lpc i/o programmed bar ec 32-bit internal address space 400f_0c00h acpi-ec 1 lpc i/o programmed bar ec 32-bit internal address space 400f_1000h table 10-9: runtime register summary offset register name (mnemonic) 00h acpi os data register byte 0 register 01h acpi os data register byte 1 register 02h acpi os data register byte 2 register 03h acpi os data register byte 3 register 04h acpi os command register 04h os status os register 05h os byte control register 06h reserved 07h reserved offset 00h bits description type default reset event 7:0 acpi_os_data_byte_0 this is byte 0 of the 32-bit acpi-os data bytes[3:0] . r/w 0h vcc1_r eset table 10-7: ec-only registers summary (continued) ec offset ec-only registers register name (mnemonic) ec access host offset aliased runtime register register name (mnemonic) host access
? 2014 - 2015 microchip technology inc. ds00001719d-page 135 MEC1322 acpi-os data bytes[3:0] writes by the acpi_os to the acpi-os data bytes[3:0] are aliased to the os2ec data bytes[3:0] . reads by the acpi_os from the acpi-os data bytes[3:0] are aliased to the ec2os data bytes[3:0] . all access to the acpi-os data bytes[3:0] registers should be orderly: least signi ficant byte to most significant byte when byte access is used. writes to any of the four acpi-os data bytes[3:0] registers clears the cmd bit in the os status os register (the state of the four_byte_access bit in the os byte control register has no impact.) when the four_byte_access bit in the os byte control register is cleared to ?0?, the following access rules apply: 1. writes to the acpi os data register byte 0 register sets the ibf bit in the os status os register . 2. reads from the acpi os data register byte 0 register clears the obf bit in the os status os register . 3. all writes to acpi-os data bytes[3:1] complete without error but the data are not registered. 4. all reads from acpi-os data bytes[3:1] return 00h without error. 5. access to acpi-os data bytes[3:1] has no effect on the ibf & obf bits in the os status os register . when the four byte access bit in the os byte control register is set to ?1?, the following access rules apply: 1. writes to the acpi os data register byte 3 register sets the ibf bit in the os status os register . 2. reads from the acpi os data register byte 3 register clears the obf bit in the os status os register . 10.12.2 acpi os data register byte 1 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.12.3 acpi os data register byte 2 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.12.4 acpi os data register byte 3 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. offset 01h bits description type default reset event 7:0 acpi_os_data_byte_1 this is byte 1 of the 32-bit acpi-os data bytes[3:0] . r/w 0h vcc1_r eset offset 02h bits description type default reset event 7:0 acpi_os_data_byte_2 this is byte 2 of the 32-bit acpi-os data bytes[3:0] . r/w 0h vcc1_r eset offset 03h bits description type default reset event 7:0 acpi_os_data_byte_3 this is byte 3 of the 32-bit acpi-os data bytes[3:0] . r/w 0h vcc1_r eset
MEC1322 ds00001719d-page 136 ? 2014 - 2015 microchip technology inc. 10.12.5 acpi os command register 10.12.6 os status os register this read-only register is aliased to the ec status register on page 143 . the ec status register on page 143 has read write access. offset 04h bits description type default reset event 7:0 acpi_oss_command writes to the this register are aliased in the os2ec data ec byte 0 register . writes to the this register also set the cmd and ibf bits in the os status os register w0h vcc1_r eset offset 04h bits description type default reset event 7ud0b user defined r0b vcc1_r eset 6 smi_evt this bit is set when an smi event is pending; i.e., the acpi_ec is requesting an smi query; this bit is cleared when no smi events are pending. this bit is an acpi_ec -maintained software flag that is set when the acpi_ec has detected an internal event that requires system management interrupt handler attention. the acpi_ec sets this bit before generating an smi. note: the usage model from the acpi specification requires both smi?s and sci?s. the acpi_os smi & sci inter- rupts are not implemented in the acpi embedded con- troller interface (acpi-eci). the smi_evt and sci_evt bits in the os status os register are soft- ware flags and this block do not initiate smi or sci events. r0b vcc1_r eset 5 sci_evt this bit is set by software when an sci event is pending; i.e., the acpi_ec is requesting an sci query; sci event flag is clear when no sci events are pending. this bit is an acpi_ec -maintained software flag that is set when the embedded controller has detected an internal event that requires operating syst em attention. the acpi_ec sets this bit before generating an sci to the os. note: the usage model from the acpi specification requires both smi?s and sci?s. the acpi_os smi & sci inter- rupts are not implemented in the acpi embedded con- troller interface (acpi-eci). the smi_evt and sci_evt bits in the os status os register are soft- ware flags and this block do not initiate smi or sci events. r0b vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 137 MEC1322 4burst the burst bit is set when the acpi_ec is in burst mode for polled command processing; the burst bit is cleared when the acpi_ec is in normal mode for interrupt-driven command processing. the burst bit is an acpi_ec -maintained software flag that indi- cates the embedded controller has received the burst enable com- mand from the host, has halted normal processing, and is waiting for a series of commands to be sent from the host. burst mode allows the os or system management handler to quickly read and write several bytes of data at a time without the overhead of scis between commands. the burst bit is maintained by acpi_ec software, only. r0b vcc1_r eset 3cmd this bit is set when the os2ec data ec byte 0 register contains a command byte written into acpi os command register ; this bit is cleared when the os2ec data bytes[3:0] contains a data byte written into the acpi-os data bytes[3:0] . this bit is hardware controlled: ? acpi_os writes to any of the four acpi-os data bytes[3:0] bytes clears this bit ? acpi_os writes to the acpi os command register sets this bit. note: this bit allows the embedded controller to differentiate the start of a command sequence from a data byte write operation. r0b vcc1_r eset 2ud1b user defined r0b vcc1_r eset offset 04h bits description type default reset event
MEC1322 ds00001719d-page 138 ? 2014 - 2015 microchip technology inc. 1ibf the input buffer full bit is set to indicate that a the acpi_os has written a command or data to the acpi_ec and that data is ready. this bit is automatically cleared when data has been read by the acpi_ec . note: the setting and clearing of this ibf varies depending on the setting of the following bits: cmd bit in this register and four_byte_access bit in the os byte control register . three scenarios follow: 1. the ibf is set when the acpi_os writes to the acpi os command register . this same write autonomously sets the cmd bit in this register. the ibf is cleared if the cmd bit in this register is set and the acpi_ec reads from the os2ec data ec byte 0 register . note: when cmd bit in this register is set the four_byte_- access bit in the os byte control register has no impact on the ibf bit behavior. 2. a write by the to the acpi_os to the acpi os data register byte 0 register sets the ibf bit if the four_byte_access bit in the os byte control register is in the cleared to ?0? state prior to this write. this same write autonomously clears the cmd bit in this register. a read of the os2ec data ec byte 0 register clears the ibf bit if the four_byte_access bit in the os byte control register is in the cleared to ?0? state prior to this read. 3. a write by the to the acpi_os to the acpi os data register byte 3 register sets the ibf bit if the four_byte_access bit in the os byte control register is in the set to ?1? state prior to this write. this same write autonomously clears the cmd bit in this register. a read of the os2ec data ec byte 3 register clears the ibf bit if the four_byte_access bit in the os byte control register is in the set to ?1? state prior to this read. an ec_ibf interrupt signals the acpi_ec that there is data avail- able. the acpi specification usage model is as follows: 1. the acpi_ec reads the ec status register and sees the ibf flag set, 2. the acpi_ec reads all the data available in the os2ec data bytes[3:0] . this causes the ibf bit to be automatically cleared by hardware. 3. the acpi_ec must then generate a software interrupt (see note: on page 130 ) to alert the acpi_os that the data has been read and that the host is free to write more data to the acpi_ec as needed. r0h vcc1_r eset offset 04h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 139 MEC1322 0obf the output buffer full bit is set to indicate that a the acpi_ec has written a data to the acpi_os and that data is ready. this bit is automatically cleared when all the data has been read by the acpi_os . note: the setting and clearing of this obf varies depending on the setting four_byte_access bit in the os byte control register . two scenarios follow: 1. the obf bit is set if the four byte access bit in the os byte control register is ?0? when the acpi_ec writes to the ec2os data ec byte 0 register . the obf is cleared if the four byte access bit in the os byte con- trol register is cleared to ?0? when the acpi_os reads from the acpi os data register byte 0 register . 2. the obf is set if the four byte access bit in the os byte con- trol register is set to ?1? when the acpi_ec writes to the ec2os data ec byte 3 register . the obf is cleared if the four byte access bit in the os byte con- trol register is set to ?1? when the acpi_os reads from the acpi os data register byte 3 register . the acpi specification usage model is as follows: 1. the acpi_ec must generate a software interrupt (see note: on page 130 ) to alert the acpi_os that the data is available. 2. the acpi_os reads the os status os register and sees the obf flag set, the acpi_os reads all the data available in the acpi-os data bytes[3:0] . 3. the acpi_os reads all the data available in the acpi-os data bytes[3:0] . this causes the obf bit to be automati- cally cleared by hardware and the associated ec_obf inter- rupt to be asserted. r0h vcc1_r eset offset 04h bits description type default reset event
MEC1322 ds00001719d-page 140 ? 2014 - 2015 microchip technology inc. 10.12.7 os byte control register this register is aliased to the ec byte control register on page 144 . no behavioral differences occur due to address aliasing. 10.13 ec-only registers the registers listed in the ec-only register summary table are for two instances of the acpi embedded controller interface (acpi-eci) . the addresses of each register listed in this t able are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. offset 05 bits description type default reset event 7:1 reserved r - - 0 four_byte_access when this bit is set to ?1?, the acpi embedded controller interface (acpi-eci) accesses four bytes through the acpi-os data bytes[3:0] . when this bit is cleared to ?0?, the acpi embedded controller inter- face (acpi-eci) accesses one byte through the acpi os data reg- ister byte 0 register . the corresponds to legacy mode described in section 10.10, "description," on page 130 . note 1: this bit effects the behavior of the ibf & obf bits in the os status os register . 2: see acpi-os data bytes[3:0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed description of access rules. r0b vcc1_r eset note: the acpi_os access base address register (bar) sh ould be configured to match the access width selected by the four byte access bit in the os byte control register. this bar in not described in this chapter. table 10-10: ec-only register base address table block instance instance number host address space base address acpi-ec 0 ec 32-bit internal address space 400f_0c00h acpi-ec 1 ec 32-bit internal address space 400f_1000h table 10-11: ec-only register summary offset register name (mnemonic) 100h ec2os data ec byte 0 register 101h ec2os data ec byte 1 register 102h ec2os data ec byte 2 register 103h ec2os data ec byte 3 register 104h ec status register 105h ec byte control register 106h reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 141 MEC1322 10.13.1 os2ec data ec byte 0 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. os2ec data bytes[3:0] when the cmd bit in the os status os register is cleared to ?0?, reads by the acpi_ec from the os2ec data bytes[3:0] are aliased to the acpi-os data bytes[3:0] . all access to the os2ec data bytes[3:0] registers should be orderly: least significant byte to most significant byte when byte access is used. when the four_byte_access bit in the os byte control register is cleared to ?0?, the following access rules apply: 1. writes to the os2ec data bytes[3:0] have no effect on the obf bit in the os status os register . 2. reads from the os2ec data ec byte 0 register clears the ibf bit in the os status os register . 3. all reads from os2ec data bytes[3:1] return 00h without error. 4. access to os2ec data bytes[3:1 has no effect on the ibf & obf bits in the os status os register . when the four_byte_access bit in the os byte control register is set to ?1?, the fo llowing access rules apply: 1. writes to the os2ec data bytes[3:0] have no effect on the obf bit in the os status os register . 2. reads from the os2ec data ec byte 3 register clears the ibf bit in the os status os register . 10.13.2 os2ec data ec byte 1 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 107h reserved 108h os2ec data ec byte 0 register 109h os2ec data ec byte 1 register 10ah os2ec data ec byte 2 register 10bh os2ec data ec byte 3 register offset 108h bits description type default reset event 7:0 os_to_ec_data_byte_0 this is byte 0 of the 32-bit os2ec data bytes[3:0] . r/w 0h vcc1_r eset offset 109h bits description type default reset event 7:0 os2ec_data_ byte_1 this is byte 1 of the 32-bit os2ec data bytes[3:0] . r/w 0h vcc1_r eset table 10-11: ec-only regist er summary (continued) offset register name (mnemonic)
MEC1322 ds00001719d-page 142 ? 2014 - 2015 microchip technology inc. 10.13.3 os2ec data ec byte 2 register this register is aliased; see acpi-os data bytes[3:0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.13.4 os2ec data ec byte 3 register this register is aliased; see acpi-os data bytes[3:0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.13.5 ec2os data ec byte 0 register this register is aliased; see acpi-os data bytes[3:0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. ec2os data bytes[3:0] writes by the acpi_ec to the ec2os data bytes[3:0] are aliased to the acpi-os data bytes[3:0] all access to the ec2os data bytes[3:0] registers should be orderly: least significant byte to most significant byte when byte access is used. when the four_byte_access bit in the os byte control register is cleared to ?0?, the following access rules apply: 1. writes to the ec2os data ec byte 0 register set the obf bit in the os status os register . 2. reads from the ec2os data bytes[3:0] have no effect on the ibf bit in the os status os register . 3. all reads from ec2os data bytes[3:1] return 00h without error. 4. all writes to ec2os data bytes[3:1] complete without error but the data are not registered. 5. access to ec2os data bytes[3:1] have no effect on the ibf & obf bits in the os status os register . when the four_byte_access bit in the os byte control register is set to ?1?, the fo llowing access rules apply: 1. writes to the ec2os data ec byte 3 register set the obf bit in the os status os register . 2. reads from the ec2os data bytes[3:0] have no effect on the ibf bit in the os status os register . offset 10ah bits description type default reset event 7:0 os2ec_data_byte_2 this is byte 2 of the 32-bit os2ec data bytes[3:0] . r/w 0h vcc1_r eset offset 10bh bits description type default reset event 7:0 os2ec_data_byte_3 this is byte 3 of the 32-bit os2ec data bytes[3:0] . r/w 0h vcc1_r eset offset 100h bits description type default reset event 7:0 ec2os_data_byte_0 this is byte 0 of the 32-bit ec2os data bytes[3:0] . r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 143 MEC1322 10.13.6 ec2os data ec byte 1 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.13.7 ec2os data ec byte 2 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.13.8 ec2os data ec byte 3 register this register is aliased; see acpi-os data bytes[3: 0] on page 135 , os2ec data bytes[3:0] on page 141 , and ec2os data bytes[3:0] on page 142 for detailed descripti on of access rules. 10.13.9 ec status register this register is aliased to the os status os register on page 136 . the os status os register is a read only version of this register. offset 101h bits description type default reset event 7:0 ec2os_data_byte_1 this is byte 1 of the 32-bit ec2os data bytes[3:0] . r/w 0h vcc1_r eset offset 102h bits description type default reset event 7:0 ec2os_data_byte_2 this is byte 2 of the 32-bit ec2os data bytes[3:0] . r/w 0h vcc1_r eset offset 103h bits description type default reset event 7:0 ec2os_data_byte_3 this is byte 3 of the 32-bit ec2os data bytes[3:0] . r/w 0h vcc1_r eset offset 104h bits description type default reset event 7 ud0a user defined r/w 0b vcc1_r eset 6 smi_evt see smi_evt bit in os status os register on page 136 for bit description. r/w 0b vcc1_r eset 5 sci_evt see smi_evt bit in os status os register on page 136 for bit description. r/w 0b vcc1_r eset 4 burst see burst bit in os status os register on page 136 for bit description. r/w 0b vcc1_r eset
MEC1322 ds00001719d-page 144 ? 2014 - 2015 microchip technology inc. 10.13.10 ec byte control register this register is aliased to the os byte control register on page 140 . the os byte control register is a read only version of this register. 3cmd see cmd bit in os status os register on page 136 for bit description. r0b vcc1_r eset 2 ud1a user defined r/w 0b vcc1_r eset 1ibf see ibf bit in os status os register on page 136 for bit descrip- tion. r0h vcc1_r eset 0obf see obf bit in os status os register on page 136 for bit descrip- tion. r0h vcc1_r eset note: the ibf and obf bits are not de-asserted by hardware when t he host is powered off, or the lpc interface powers down; for example, following system state chan ges s3->s0, s5->s0, g3-> s0. for further informa- tion on how these bits are cleared, refer to ibf and obf bit descriptions in the status os-register defi- nition. offset 105h bits description type default reset event 7:1 reserved r - - 0 four_byte_access see four_byte_access bit in os byte control register on page 140 for bit description. r/w 0b vcc1_r eset offset 104h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 145 MEC1322 11.0 8042 emulated keyboard controller 11.1 introduction the MEC1322 keyboard controller uses the ec to produce a su perset of the features prov ided by the industry-standard 8042 keyboard controller. the 8042 emulated keyboard controller is a host/ec message interface with hardware assists to emulate 8042 behavior an d provide legacy gatea20 support. 11.2 references there are no references for this block. 11.3 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 11.4 signal description note: there is no vcc emulation in hardware for this interface. figure 11-1: i/o diagram of block table 11-1: signal description table name direction description kbrst output keyboard reset, routed to pin 8042 emulated keyboard controller signal description clock inputs interrupts resets host interface
MEC1322 ds00001719d-page 146 ? 2014 - 2015 microchip technology inc. 11.5 host interface the 8042 interface is accessed by host software via a registered interface, as defined in section 11.13, "configuration registers" and section 11.14, "runtime registers". 11.6 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 11.6.1 power domains 11.6.2 clock inputs 11.6.3 resets 11.7 interrupts this section defines the interrupt sources generated from this block. 11.8 low power modes the 8042 interface may be put into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. table 11-2: power sources name description vcc1 this power well is used to power the registers and logic in this block. table 11-3: clock inputs name description 1mhz clock used for the counter in the cpu_reset circuitry. table 11-4: reset signals name description vcc1_reset this reset is asserted when vcc1 is applied. pwrgd this signal is asserted when the main power rail is asserted. pci reset# this signal is asserted when lreset# is asserted. nsio_reset this signal is asserted when vcc1 is low, pwrgd is low, or lreset# is asserted. table 11-5: system interrupts source description kirq this interrupt source for the sirq logic, representing a keyboard inter- rupt, is generated when the pcobf status bit is ?1?. mirq this interrupt source for the sirq logic, representing a mouse interrupt, is generated when the auxobf status bit is ?1?. table 11-6: ec interrupts source description 8042em_ibf interrupt generated by the host writing either data or command to the data register 8042em_obf interrupt generated by the host re ading either data or aux data from the data register
? 2014 - 2015 microchip technology inc. ds00001719d-page 147 MEC1322 11.9 description 11.9.1 block diagram 11.10 ec-to-host keyboard communication the ec can write to the ec_host data / aux data register by writing to the host2ec data register at ec-only offset 0h or the ec aux data register at ec-only offset ch. a write to either of these addresses automatically sets bit 0 ( obf ) in the status register. a write to the host2ec data register may also set pcobf . a write to the ec aux data register may also set auxobf . 11.10.1 pcobf description if enabled by the bit obfen, the bit pcobf is gated onto kirq. t he kirq signal is a system interrupt which signifies that the ec has written to the host2ec data register (ec-only offset 0h). on power-u p, pcobf is reset to 0. pcobf will normally reflect the status of writes to host2ec register, if pcobfen is ?0?. pcobf is cleared by hardware on a host read of the ec_host data / aux data register . kirq is normally selected as irq1 for keyboard support. additional flexibility has been added which allows firmware to directly control the pcobf output signal, independent of data transfers to the host-interface data output register. this feature allows the MEC1322 to be operated via the host ?polled? mode. firmware control is active when pcobfen is ?1?. firmware sets pcobf high by writing a ?1? to the pcobf field of the pcobf register . firmware must also clear pcobf by writing a ?0? to the pcobf field. the pcobf register is also readable; the value read back on bit 0 of the register always reflects the present value of the pcobf output. if pcobfen = 1, then this value reflects the output of the firmware latch in the pcobf register . if pcobfen = 0, then the value read back reflects the in-process status of write cycles to the host2ec data register (i.e., if the value read back is high, the host interface output data register has just been written to). if obfen=0, then kirq is driven inactive (low). figure 11-2: block diagram of 8042 emulated keyboard controller spb offset =100h read data or cmd auxh = 1 bit [5] is auxobf auxh = 0 bit [5] is ud 2 ibf set on host write to lpc i/o index =00h or 04h ibf cleared on ec read to spb offset = 00h 3 obf set on ec write to spb offset = 100h or 10ch obf cleared by read 0f lpc i/o index 00h 4 pcobfen = 1 pcobf is contents of bit 0 spb offset = 114h pcobfen = 0 pcbobf is set on ec write of spb offset = 100 h pcobf is cleared on host read of lpc i/o index = 00h d7 d3 d4 d5 d6 d0 d1 d2 d7 ud d3 c/d d4 ud d5 auxobf / ud d6 ud d0 obf 3 d1 ibf 2 d2 ud 1 host_ec data register status register keyboard control register w lpc i/o index =00 write data r lpc i/o read index =04h r spb offset =104h r w ec access host access 1 this bit is reset by lpcreset and vtr_por d7 res d3 res d4 res d5 res d6 res d1 res d2 res pcobf register r ff_0514 w d7 auxh d3 ud d4 ud d5 obfen d6 ud d0 ud d1 saen d2 pcobfen r w d7 d3 d4 d5 d6 d0 d1 d2 r w ec_host data register spb offset =10ch write aux data spb offset =100h write data ff_0508 d0 pcobf 4 lpc i/o index =04 write cmd lpc i/o index =00 read data or aux data
MEC1322 ds00001719d-page 148 ? 2014 - 2015 microchip technology inc. 11.10.2 auxobf description if enabled by the bit obfen, the bit au xobf is multiplexed onto mirq. the au xobf/mirq signal is a system interrupt which signifies that the ec has written to the ec_host data / aux data register . on power-up, after vcc1_reset , auxobf is reset to 0. auxo bf will normally reflects the status of writes to ec ec aux data register (ec-only offset ch). auxobf is cleared by hardware on a read of the host data register. if obfen=0, then mirq is driven inactive (low). mirq is normally selected as irq12 for mouse support. firmware can also directly control the auxobf output signal, similar to the mechanism it can use to control pcobf. firmware control is active when auxh is ?0?. firmware sets auxobf high by writing a ?1? to the auxobf field of the ec keyboard status register . firmware must also clear auxobf by writing a ?0? to the auxobf field. 11.11 legacy port92/gatea20 support the MEC1322 supports lpc i/o writes to port host i/o ad dress 92h as a quick alternate mechanism for generating a cpu_reset pulse or controlling the stat e of gatea20. the port92 /gatea20 logic has a sepa rate logical device num- ber and base address register (see section 11.16, "legacy port92/gatea20 configuration registers" and section 11.17, "legacy port92/gatea20 runtime registers" . the base address register for the port92/gatea20 logical device has only one writable bit, the valid bit, sinc e the only i/o accessible register has a fixed address. the port 92 register resides at host i/o address 92h and is used to support the alternate reset (alt_rst#) and alter- nate gatea20 (alt_a20) functions. this register defaults to 00h on assertion of nsio_reset . setting the port92 enable bit ( port 92 enable register ) enables the port92h register. when port92 is disabled, by clear- ing the port92 enable bit, then access to this register is co mpletely disabled (i/o writes to host 92h are ignored and i/o reads float the system data bus sd[7:0]). 11.11.1 gate a20 speedup the MEC1322 contains on-chip logic support for the gatea 20 hardware speed-up feature. gatea20 is part of the con- trol required to mask address line a20 to emulate 8086 addressing. in addition to the ability for the host to control the gatea20 output signal directly, a configuration bit called saen in the keyboard control register is provided; when set, saen allows firmware to control the gatea20 output. when saen is set, a 1 bit register ( gatea20 control register ) controls the gatea20 output. host control and firmware control of gatea20 affect two separate register elements. read back of gatea20 through the use of ec offset 100h reflects the present state of the gatea20 output signal: if saen is set, the value read back corresponds to the last firmware-initiated control of gatea20; if saen is reset, the value read back corresponds to the last host-initiated control of gatea20. host control of the gatea20 output is provided by t he hardware interpretation of the ?gatea20 sequence? (see table 11-9, "gatea20 command/data sequence examples" ). the foregoing description assumes that the saen con- figuration bit is reset. table 11-7: obfen and pcobfen effects on kirq obfen pcobfen 0 x kirq is inactive and driven low 1 0 kirq = pcobf (status of writes to host2ec data register ) 1 1 kirq = pcobf (status of writes to pcobf register ) table 11-8: obfen and auxh effects on mirq obfen auxh 0 x mirq is inactive and driven low 1 0 mirq = auxobf (status of writes to ec aux data register ) 1 1 mirq = auxobf (status of writes to auxobf in ec keyboard status register )
? 2014 - 2015 microchip technology inc. ds00001719d-page 149 MEC1322 when the MEC1322 receives a ?d1? command followed by data (via the host interface), the on-chip hardware copies the value of data bit 1 in the received data field to the gatea20 host latch. at no time during this host-interface trans- action will pcobf or the ibf flag (bit 1) in the ec keyboard status register be activated; for example, this host control of gatea20 is transparent to fi rmware, with no consequent degradatio n of overall system performance. table 11-9 details the possible gatea20 sequences and the MEC1322 responses. an additional level of control flexibility is offered via a memory-mapped synchronous set and reset capability. any data written to the setga20l register causes the gatea20 host latch to be set; any data written to the rstga20l register causes it to be reset. this control mechanism should be us ed with caution. it was added to augment the ?normal? control flow as described above, not to replace it. since the host and the firmware have asynchronous control capability of the host latch via this mechanism, a potential conflict coul d arise. therefore, after using the setga20l and rstga20l registers, firmware should read back the gatea20 status vi a the gatea20 control register (with saen = 0) to confirm the actual gatea20 response. table 11-9: gatea20 command/data sequence examples data byte r/w d[0:7] ibf flag gatea20 comments 1 0 1 w w w d1 df ff 0 0 0 q 1 1 gatea20 turn-on sequence 1 0 1 w w w d1 dd ff 0 0 0 q 0 0 gatea20 turn-off sequence 1 1 0 1 w w w w d1 d1 df ff 0 0 0 0 q q 1 1 gatea20 turn-on sequence(*) 1 1 0 1 w w w w d1 d1 dd ff 0 0 0 0 q q 0 0 gatea20 turn-off sequence(*) 1 1 1 w w w d1 xx** ff 0 1 1 q q q invalid sequence note: the following notes apply: - all examples assume that t he saen configuration bit is 0. - ?q? indicates the bit remains set at the previous state. - *not a standard sequence. - **xx = anything except d1. - if multiple data bytes, set ibf and wait at state 0. let the software know something unusual happened. - for data bytes, only d[1] is used; all other bits are don't care. - host commands (ff, fe, & d1) do not cause ibf. the method of blocking ibf in figure 11-4 is the niow not being asserted when ff, fe, & d1 host commands are written?.
MEC1322 ds00001719d-page 150 ? 2014 - 2015 microchip technology inc. the hardware gatea20 state machine returns to state s1 from state s2 when cmd = d1, as shown in the following figures:. figure 11-3: gatea20 state machine s0 s2 s1 reset cmd !=d1 or data [ibf=1] cmd = ff [ibf=0] cmd !=d1 or cmd !=ff or data [ibf=1] cmd !=d1 [ibf=1] cmd = d1 [ibf=0] cmd = d1 [ibf=0] data [ibf=0, latch din cmd = d1 [ibf=0] notes: gatea20 changes when in s1 going to s2 clock = wrdinb cmd = [c/d=1] data = [c/d=0]
? 2014 - 2015 microchip technology inc. ds00001719d-page 151 MEC1322 11.11.2 cpu_reset hardware speed-up the alt_cpu_reset bit generates, under program control, the alt_rs t# signal, which provides an alternate, means to drive the MEC1322 cpu_reset pin whic h in turn is used to reset the host cpu. the alt_rst# signal is internally nanded together with the kbdreset# puls e from the kreset speed up logic to provide an alternate software means of resetting the host cpu. before another alt_rst# pulse ca n be generated, alt_cpu_r eset must be cleared to ?0? either by an nsio_reset or by a write to the port 92 register with bit 0 = ?0?. an alt_rst# pulse is not generated in the event that the alt_cpu_reset bit is clear ed and set before the prior alt_reset# pulse has completed. if the 8042em sleep enable is asserted, or the 8042 em activate bit is de-asserted, the 1m hz clocks source is dis- abled. figure 11-4: gatea20 im plementation diagram q q set clr d q q set clr d q q set clr d q q set clr d saen 64&aen# data aen#&60 address q q set clr d q q set clr d setga20l reg (any wr) rstga20l reg (any wr) 24mhz iow# aen#&64 gatea20 reg wr (d0) gatea20 reg rd (d0) cpu reset sd[7:0] = fe sd[7:0] = ff sd[7:0] = d1 iow# niow niow niow iow# aen#&60 kreset gen ibf enab p92 port 92 reg (d1) gatea20 vcc vcc
MEC1322 ds00001719d-page 152 ? 2014 - 2015 microchip technology inc. 11.12 instance description there are two blocks defi ned in this chapter: emulated 8042 interface and the legacy port92/gatea20 support . the MEC1322 has one instance of each block. 11.13 configuration registers the registers listed in the configuration register summary table are for a single instance of the emulated 8042 inter- face . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the configuration register base address table. each configuration register access through the host acce ss port is via its ldn and its host access port index. ec access is a relative offset to the ec base address. figure 11-5: cpu_reset implementation diagram table 11-10: conf iguration register base address table block instance instance number logical device number host address space base address emulated 8042 interface 0 1 lpc configuration port index = 00h ec 32-bit internal address space 400f_0400h table 11-11: configuration register summary offset register name (mnemonic) 30h activate register pulse generator fe command (from kreset speed-up logic) pulse generator saen enab p92 cpu_reset 6 s 14 s 6 s 14 s kreset alt_rst# port 92 reg (d0)
? 2014 - 2015 microchip technology inc. ds00001719d-page 153 MEC1322 11.13.1 activate register 11.14 runtime registers the registers listed in the runtime register summary table are for a single instance of the emulated 8042 interface . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the runtime register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 11.14.1 host_ec data / cmd register offset 30h bits description type default reset event 7:1 reserved r - - 0activate 1=the 8042 interface is powered and functional. 0=the 8042 interface is powered down and inactive. r/w 0b pwrgd and vcc1_r eset block instance instance number host address space base address emulated 8042 interface 0 lpc i/o programmed bar ec 32-bit address space 400f_0400h table 11-12: runtime register summary offset register name (mnemonic) 00h/04h host_ec data / cmd register 00h ec_host data / aux data register 04h keyboard status read register offset 00h bits description type default reset event 7:0 write_data this 8-bit register is write-only. when written, the c/d bit in the key- board status read register is cleared to ?0?, signifying data, and the ibf in the same register is set to ?1?. when the runtime register at offset 0h is read by the host, it func- tions as the ec_host data / aux data register . w0h vcc1_r eset
MEC1322 ds00001719d-page 154 ? 2014 - 2015 microchip technology inc. 11.14.2 ec_host data / aux data register 11.14.3 keyboard status read register this register is a read-only alias of the ec keyboard status register . offset 04h bits description type default reset event 7:0 write_cmd this 8-bit register is write-only and is an alias of the register at offset 0h. when written, the c/d bit in the keyboard status read register is set to ?1?, signifying a command, and the ibf in the same register is set to ?1?. when the runtime register at offset 4h is read by the host, it func- tions as the keyboard status read register . w0h vcc1_r eset offset 00h bits description type default reset event 7:0 read_data this 8-bit register is read-only. when read by the host, the pcobf and/or auxobf interrupts are cleared and the obf flag in the status register is cleared. r0h vcc1_r eset offset 04h bits description type default reset event 7:6 ud2 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. r0h vcc1_r eset 5auxobf auxiliary output buffer full. this bit is set to ?1? whenever the ec writes the ec aux data register . this flag is reset to ?0? whenever the ec writes the ec data register . r0h vcc1_r eset 4 ud1 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. r0h vcc1_r eset 3c/d command data. this bit specifies whether the input data register contains data or a command (?0? = data, ?1? = command). during a host command write operation (when the host writes the host_ec data / cmd register at offset 04h), this bit is set to ?1?. during a host data write operation (when the host writes the host_ec data / cmd register at offset 0h), this bit is set to ?0?. r0h vcc1_r eset 2 ud0 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. note: this bit is reset to ?0? when the lreset# pin signal is asserted. r0h vcc1_r eset and pci reset#
? 2014 - 2015 microchip technology inc. ds00001719d-page 155 MEC1322 11.15 emulated 8042 interface ec-only registers the registers listed in the ec-only register summary table are for a single instance of the emulated 8042 interface . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 1ibf input buffer full. this bit is set to ?1? whenever the host writes data or a command into the host_ec data / cmd register r. when this bit is set, the ec's 8042em_ibf interrupt is asserted, if enabled. when the ec reads the host_ec data/cmd register, this bit is automatically reset and the interrupt is cleared. note: this bit is not reset when pwrgd is asserted or when the lpc interface powers down. to clear this bit, firm- ware must read the ec data register in the ec-only address space. r0h vcc1_r eset 0obf output buffer full. this bit is set when the ec writes a byte of data or aux data into the ec_host data / aux data register . when the host reads the host_ec data / cmd register , this bit is auto- matically cleared by hardware and a 8042em_obf interrupt is gen- erated. note: this bit is not reset when pwrgd is asserted or when the lpc interface powers down. to clear this bit, firm- ware must read the host_ec data / cmd register in the runtime address space. r0h vcc1_r eset table 11-13: ec-only register base address table block instance instance number host address space base address emulated 8042 interface 0 ec 32-bit address space 400f_0410h table 11-14: ec-only register summary offset register name (mnemonic) 0h host2ec data register 0h ec data register 4h ec keyboard status register 8h keyboard control register ch ec aux data register 14h pcobf register offset 04h bits description type default reset event
MEC1322 ds00001719d-page 156 ? 2014 - 2015 microchip technology inc. 11.15.1 host2ec data register 11.15.2 ec data register 11.15.3 ec keyboard status register this register is an alias of the keyboard status read register . the fields c/d , ibf , and obf remain read-only. offset 0h bits description type default reset event 7:0 host2ec_data this register is an alias of the host_ec data / cmd register . when read at the ec-only offset of 0h, it returns the data written by the host to either runtime register offset 0h or runtime register offset 04h. r0h vcc1_r eset offset 0h bits description type default reset event 7:0 ec_data w 0h vcc1_r eset offset 04h bits description type default reset event 7:6 ud2 user-defined data. readable and writable by the ec. r/w 0h vcc1_r eset 5auxobf auxiliary output buffer full. this bit is set to ?1? whenever the ec writes the ec aux data register . this flag is reset to ?0? whenever the ec writes the ec data register . r/w 0h vcc1_r eset 4 ud1 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. r/w 0h vcc1_r eset 3c/d command data. this bit specifies whether the input data register contains data or a command. during a host command write opera- tion (when the host writes the host_ec data / cmd register at offset 04h), this bit is set to ?1?. during a host data write operation (when the host writes the host_ec data / cmd register at offset 0h), this bit is set to ?0?. 1=command 0=data r0h vcc1_r eset 2 ud0 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. this bit is reset to ?0? when the lreset# pin signal is asserted. r/w 0h vcc1_r eset and pci reset#
? 2014 - 2015 microchip technology inc. ds00001719d-page 157 MEC1322 11.15.4 keyboard control register 1ibf input buffer full. this bit is set to ?1? whenever the host writes data or a command into the host_ec data / cmd register r. when this bit is set, the ec's 8042em_ibf interrupt is asserted, if enabled. when the ec reads the data/cmd register, this bit is automatically reset and the interrupt is cleared. this bit is not reset when pwrgd is asserted or when the lpc interface powers down. to clear this bit, firmware must read the ec data register in the ec-only address space. r0h vcc1_r eset 0obf output buffer full. this bit is set when the ec writes a byte of data or aux data into the ec_host data / aux data register . when the host reads the host_ec data / cmd register , this bit is auto- matically cleared by hardware and a 8042em_obf interrupt is gen- erated. this bit is not reset when pwrgd is asserted or when the lpc interface powers down. to clear this bit, firmware must read the data/cmd register in the runtime address space. r0h vcc1_r eset offset 08h bits description type default reset event 7auxh aux in hardware. 1= auxobf of the keyboard status read register is set in hardware by a write to the ec aux data register 0= auxobf is not modified in hardware, but can be read and written by the ec using the ec-only alias of the ec keyboard status register r/w 0h vcc1_r eset 6 ud5 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. r/w 0h vcc1_r eset 5 obfen when this bit is ?1?, the system inte rrupt signal kirq is driven by the bit pcobf and mirq is driven by auxobf. when this bit is ?0?, kirq and mirq are driven low. this bit must not be changed when obf of the status register is equal to ?1?. r/w 0h vcc1_r eset 4:3 ud4 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. r/w 0h vcc1_r eset 2 pcobfen 1= reflects the value written to the pcobf register 0=pcobf reflects the status of writes to the ec data register r/w 0h vcc1_r eset offset 04h bits description type default reset event
MEC1322 ds00001719d-page 158 ? 2014 - 2015 microchip technology inc. 11.15.5 ec aux data register 11.15.6 pcobf register 1 saen software-assist enable. 1=this bit allows control of the gatea20 signal via firmware 0=gatea20 corresponds to either the last host-initiated control of gatea20 or the firmware write to the keyboard control register or the ec aux data register . r/w 0h vcc1_r eset 0 ud3 user-defined data. readable and writable by the ec when written by the ec at its ec-only alias. r/w 0h vcc1_r eset offset 0ch bits description type default reset event 7:0 ec_aux_data this 8-bit register is write-only. when written, the c/d in the key- board status read register is cleared to ?0?, signifying data, and the ibf in the same register is set to ?1?. when the runtime register at offset 0h is read by the host, it func- tions as the ec_host data / aux data register . w0h vcc1_r eset offset 14h bits description type default reset event 7:1 reserved r - - 0pcobf for a description of this bit, see section 11.10.1, "pcobf descrip- tion" . r/w 0h vcc1_r eset offset 08h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 159 MEC1322 11.16 legacy port92/gatea20 configuration registers the registers listed in the configuration register summary table are for a single instance of the legacy port92/gatea20 logic. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the config uration register base address table. each configuration register access through the host acce ss port is via its ldn and its host access port index. ec access is a relative offset to the ec base address. 11.16.1 port 92 enable register 11.17 legacy port92/gatea20 runtime registers the registers listed in the runtime register summary ta ble are for a single instance of the legacy port92/gatea20 logic. the addresses of each register listed in this tabl e are defined as a relative offset to the host ?base address? defined in the runtime register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. table 11-15: configuration base address table block instance instance number logical device number host address space base address port92-legacy 0 1 lpc configuration port index = 00h ec 32-bit internal address space 400f_1800h table 11-16: configuration register summary offset register name (mnemonic) 30h port 92 enable register offset 30h bits description type default reset event 7:1 reserved r - - 0 p92_en when this bit is ?1?, the port92h register is enabled. when this bit is ?0?, the port92h register is disabled, and host writes to lpc address 92h are ignored. r/w 0h pwrgd and vcc1_r eset table 11-17: runtime regi ster base address table block instance instance number host address space base address port92-legacy 0 lpc i/o 0092h ec 32-bit address space 400f_1800h table 11-18: runtime register summary offset register name (mnemonic) 0h port 92 register
MEC1322 ds00001719d-page 160 ? 2014 - 2015 microchip technology inc. 11.17.1 port 92 register 11.18 emulated 8042 interface ec-only registers the registers listed in the ec-only register summary tabl e are for a single instance of the legacy port92/gatea20 logic. the addresses of each register listed in this tabl e are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. offset 0h bits description type default reset event 7:2 reserved r - - 1 alt_gate_a20 this bit provides an alternate means for system control of the gatea20 pin. alt_a20 low drives gatea20 low, if a20 from the keyboard controller is also low. when port 92 is enabled, writing a 1 to this bit forces alt_a20 high. alt_a20 high drives gatea20 high regardless of the state of a20 from the keyboard controller. 0=alt_a20 is driven low 1=alt_a20 is driven high r/w 0h nsio_r eset 0 alt_cpu_reset this bit provides an alternate means to generate a cpu_reset pulse. the cpu_reset output prov ides a means to reset the sys- tem cpu to effect a mode switch from protected virtual address mode to the real address mode. this provides a faster means of reset than is provided through the ec keyboard controller. writing a ?1? to this bit will cause the alt_rst# internal signal to pulse (active low) for a minimum of 6 s after a delay of 14 s. before another alt_rst# pulse can be generated, this bit must be written back to ?0?. r/w 0h nsio_r eset table 11-19: ec-only register base address table block instance instance number host address space base address port92-legacy 0 ec 32-bit address space 400f_1900h table 11-20: ec-only register summary offset register name (mnemonic) 0h gatea20 control register 8h setga20l register ch rstga20l register
? 2014 - 2015 microchip technology inc. ds00001719d-page 161 MEC1322 11.18.1 gatea20 co ntrol register 11.18.2 setga20l register 11.18.3 rstga20l register offset 0h bits description type default reset event 7:1 reserved r - - 0 gatea20 0=the gatea20 output is driven low 1=the gatea20 output is driven high r/w 1h vcc1_r eset offset 08h bits description type default reset event 7:0 setga20l see section 11.11.1, "gate a20 speedup" for information on this register. a write to this register sets gatea20 in the gatea20 con- trol register. w- - offset 0ch bits description type default reset event 7:0 rstga20l see section 11.11.1, "gate a20 speedup" for information on this register. a write to this register sets gatea20 in the gatea20 con- trol register. w- -
MEC1322 ds00001719d-page 162 ? 2014 - 2015 microchip technology inc. 12.0 mailbox interface 12.1 overview the mailbox provides a standard run-time mechanism for the host to communicate with the embedded controller (ec) 12.2 references no references have been cited for this feature. 12.3 terminology there is no terminology defined for this section. 12.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 12.5 signal description 12.6 host interface the mailbox interface is accessed by host software via a registered interface, as defined in section 12.11, "runtime registers" and section 12.12, "ec-only registers". 12.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. figure 12-1: i/o diagram of block table 12-1: signal description table name direction description nsmi output smi alert signal to the host. mailbox interface interrupts power, clocks and reset host interface signal description
? 2014 - 2015 microchip technology inc. ds00001719d-page 163 MEC1322 12.7.1 power domains 12.7.2 clock inputs 12.7.3 resets 12.8 interrupts 12.9 low power modes the mailbox automatically enters a low power mode whenever it is not actively. table 12-2: power sources name description vcc1 the logic and registers implemented in this block are powered by this power well. table 12-3: clock inputs name description 48 mhz ring oscillator this is the clock source for mailbox logic. table 12-4: reset signals name description vcc1_reset this signal resets all the registers and logic in this block to their default state. pwrgd this signal is asserted when the main power rail is asserted. the host access port is reset when th is signal is de-asserted. table 12-5: system interrupts source description mbx_host_sirq this interrupt source for the sirq logic is generated when the ec_wr bit is ?1? and enabled by the ec_wr_en bit. mbx_host_smi this interrupt source for the sirq logic is generated when any of the ec_swi bits are asserted and the corresponding ec_swi_en bit are asserted as well. this event is also asserted if the ec_wr/ec_wr_en event occurs as well. this bit is also routed to the nsmi pin. table 12-6: ec interrupts source description mbx interrupt generated by the host writ ing the host-to-ec mailbox register. mbx_data interrupt generated by the host writing the mbx_data register.
MEC1322 ds00001719d-page 164 ? 2014 - 2015 microchip technology inc. 12.10 description figure 12-2: mailbox block diagram 12.10.1 host access port the mailbox includes a total of 47 index-addressable 8-bit mailbox registers and a two byte mailbox registers host access port. forty-three of the 47 index-addressable 8-bit re gisters are ec mailbox registers, which can be read and written by both the ec and the host. the remaining four re gisters are used for signaling between the host and the ec. the host access port consists of two 8-bit run-time regi sters that occupy two addresses in the host i/o space, mbx- _index register and mbx_data register . the host access port is used by the host to access the 47 index-address- able 8-bit registers. to access a mailbox register once the mailbox registers interface base address has been initialized, the mailbox reg- ister index address is first written to the mbx index port. after the index port has been written, the mailbox data byte can be read or written via the mbx data port. the host access port is intended to be accessed by the host only, however it may be accessed by the ec at the offset shown from its ec base address in table 12-7, "runtime register base address table" . 12.10.2 host interrupt generation the mailbox can generate a sirq event for ec-to-host ec events, using the ec-to-host mailbox register . this inter- rupt is routed to the sirq block. the mailbox can also generate an smi event, using smi interrupt source register . the smi event can be routed to any frame in the sirq stream as well as to the nsmi pin. the smi event can be routed to nsmi pin by selecting the nsmi signal function in the associated gpio pin control register . the smi event produces a standard active low frame on the serial irq stream and active low level on the open drain nsmi pin. routing for both the sirq logic and the nsmi pin is shown in figure 12-3 . host-to-ec ec-to-host forty-three 8-bit mailbox registers host cpu smi ec
? 2014 - 2015 microchip technology inc. ds00001719d-page 165 MEC1322 figure 12-3: mailbox sirq and smi routing 12.10.3 ec mailbox control the host-to-ec mailbox register and ec-to-host mailbox register are designed to pass commands between the host and the ec. if enabled, these registers can generate interrupts to both the host and the ec. the two registers are not dual-ported, so the host bios and keyboard bios must be designed to properly share these registers. when the host performs a write of the host-to-ec mailbox register , an interrupt will be generated and seen by the ec if unmasked. when the ec writes ffh to the mail box register, the register resets to 00h, providing a simple means for the ec to inform the host that an operation has been completed. when the ec writes the ec-to-host mailbox register , an smi may be generated and seen by the host if unmasked. when the host cpu writes ffh to the register, the register resets to 00h, providing a simple means for the host to inform that ec that an operation has been completed. note: the protocol used to pass commands back and forth thr ough the mailbox registers interface is left to the system designer. microchip can provide an application example of working code in which the host uses the mailbox registers to gain access to all of the ec registers. mailbox registers mbx_host_smi gpio n s m i pin control register sirq mapping sirq mbx_host_sirq irq0 select bit irq1 select bit irq2 select bit irqn select bit
MEC1322 ds00001719d-page 166 ? 2014 - 2015 microchip technology inc. 12.11 runtime registers the registers listed in the runtime register summary table are for a single instance of the mailbox. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the runtime reg- ister base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 12.11.1 mbx_index register 12.11.2 mbx_data register 12.12 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the mailbox. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only reg- ister base address table. the ec-only registers can be accessed by the ec at the ec offset from the base address. in addition, the registers can be accessed through the host access port, at the indexes listed in the following tables as ?mbx_index?. table 12-7: runtime register base address table block instance instance number host address space base address mailbox interface 0 lpc i/o programmed bar ec 32-bit address space 400f_2400h table 12-8: runtime register summary offset register name (mnemonic) 0h mbx_index register 1h mbx_data register offset 0h bits description type default reset event 7:0 index the index into the mailbox registers listed in table 12-10, "ec-only register summary" . r/w 0h vcc1_r eset and pwrgd = 0 offset 01h bits description type default reset event 7:0 data data port used to access the registers listed in table 12-10, "ec- only register summary" . r/w 0h vcc1_r eset and pwrgd = 0 table 12-9: ec-only register base address table block instance instance number host address space base address mailbox interface 0 ec 32-bit address space 400f_2500h
? 2014 - 2015 microchip technology inc. ds00001719d-page 167 MEC1322 table 12-10: ec-onl y register summary ec offset host i/o index (mbx_index) register name (mnemonic) 00h 82h host-to-ec mailbox register 04h 83h ec-to-host mailbox register 08h 96h smi interrupt source register 0ch 97h smi interrupt mask register 10h 84h mailbox register [0] 85h mailbox register [1] 86h mailbox register [2] 87h mailbox register [3] 14h 88h mailbox register [4] 89h mailbox register [5] 8ah mailbox register [6] 8bh mailbox register [7] 18h 8ch mailbox register [8] 8dh mailbox register [9] 8eh mailbox register [a] 8fh mailbox register [b] 1ch 90h mailbox register [c] 91h mailbox register [d] 92h mailbox register [e] 93h mailbox register [f] 20h 94h mailbox register [10] 95h mailbox register [11] 98h mailbox register [12] 99h mailbox register [13] 24h 9bh mailbox register [14] 9dh mailbox register [15] 9fh mailbox register [16] a0h mailbox register [17] 28h a1h mailbox register [18] a2h mailbox register [19] a3h mailbox register [1a] a4h mailbox register [1b] 2ch a5h mailbox register [1c] a6h mailbox register [1d] a7h mailbox register [1e] a8h mailbox register [1f] 30h a9h mailbox register [20] aah mailbox register [21] abh mailbox register [22] ach mailbox register [23]
MEC1322 ds00001719d-page 168 ? 2014 - 2015 microchip technology inc. 12.12.1 host-to-ec mailbox register 12.12.2 ec-to-host mailbox register 34h adh mailbox register [24] aeh mailbox register [25] afh mailbox register [26] b0h mailbox register [27] 38h b1h mailbox register [28] b2h mailbox register [29] b3h mailbox register [2a] note: the mailbox index addresses 9ah, 9ch and 9eh are not used in table 12-10 . these addresses are reserved. offset 0h mbx_ index 82h bits description type default reset event 7:0 host_ec_mbox if enabled, an interrupt to the ec marked by the mbx_data bit in the interrupt aggregator will be generated whenever the host writes this register. this register is clear ed when written with ffh. host access port: r/w ec: r/wc 0h vcc1_r eset offset 4h mbx_ index 83h bits description type default reset event 7:0 ec_host_mbox an ec write to this register will set bit ec_wr in the smi interrupt source register to ?1b?. if enabled, this will? generate a host smi. this register is clear ed when written with ffh. host access port: r/wc ec: r/w 0h vcc1_r eset table 12-10: ec-only regist er summary (continued) ec offset host i/o index (mbx_index) register name (mnemonic)
? 2014 - 2015 microchip technology inc. ds00001719d-page 169 MEC1322 12.12.3 smi interrupt source register 12.12.4 smi interrupt mask register offset 8h mbx_ index 96h bits description type default reset event 7:1 ec_swi ec software interrupt. an sirq to the host is generated when any bit in this register when this bit is set to ?1b? and the corresponding bit in the smi interrupt mask register register is ?1b?. this field is read/write when accessed by the ec at the ec offset. when written through the host access port, each bit in this field is cleared when written with a ?1b?. writes of ?0b? have no effect. host access port: r/wc ec: r/w 0h vcc1_r eset 0ec_wr ec mailbox write. this bit is set automatically when the ec-to-host mailbox register has been written. an smi or sirq to the host is generated when n this bit is ?1b? and the corresponding bit in the smi interrupt mask register register is ?1b?. this bit is automatically cleared by a read of the ec-to-host mailbox register through the host access port. this bit is read-only when read through the host access port. it is neither readable nor writable directly by the ec when accessed at the ec offset. host access port: r ec: - 0h vcc1_r eset offset ch mbx_ index 97h bits description type default reset event 7:1 ec_swi_en ec software interrupt enable. if this bit is ?1b?, the bit ec_wr in the smi interrupt source register is enabled for the generation of sirq or nsmi events. host access port: r/w ec: r/w 0h vcc1_r eset 0ec_wr_en ec mailbox write.interrup t enable. each bit in this field that is ?1b? enables the generation of sirq interrupts when the corresponding bit in the ec_swi field in the smi interrupt source register is ?1b?. host access port: r/w ec: r/w 0h vcc1_r eset
MEC1322 ds00001719d-page 170 ? 2014 - 2015 microchip technology inc. 13.0 acpi pm1 block interface 13.1 introduction the MEC1322 supports acpi as described in this section. these features comply with the acpi specification through a combination of hardware and ec software. 13.2 references acpi specification, revision 1.0 13.3 terminology none 13.4 interface this block is an ip block designed to be incorporated into a chip. it is designed to be accessed externally via the pin interface and internally via a registered host interface. the following diagram illustrates the various interfaces to the block. figure 13-1: i/o diagram of block acpi pm1 block interface signal description clocks interrupts resets host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 171 MEC1322 13.5 signal description table 13-1, "acpi pm1 signal description table" lists the signals that are typically routed to the pin interface. 13.6 host interface the registers defined for the acpi pm1 block interface are accessible by the various hosts as indicated in section 13.11, "runtime registers" . 13.7 power, clocks and resets this section defines the power, clock, and reset parameters of the block. 13.7.1 power domains 13.7.2 clocks this section describes all the clocks in the block, including those that are derived from the i/o interface as well as the ones that are derived or generated internally. 13.7.3 resets 13.8 interrupts this section defines the interrupt sources generated from this block. table 13-1: acpi pm1 signal description table name direction description ec_sci# output any or all of the pwrbtn_sts , slpbtn_sts , and rtc_sts bits in the power management 1 status 2 register can assert the ec_sci# pin if enabled by the associated bits in the power man- agement 1 enable 2 register register. the ec_sci_sts bit in the ec-only registers register can also be used to generate an sci on the ec_sci# pin. table 13-2: power sources name description vcc1 this power well sources the regi sters and logic in this block. table 13-3: clocks name description 48 mhz ring oscillator this clock signal drives sele cted logic (e.g., counters). table 13-4: reset signals name description vcc1_reset this reset signal resets all of the registers and logic in this block. table 13-5: ec interrupts source description acpipm1_ctl this interrupt is generated to the ec by the host writing to the power management 1 control 2 register register acpipm1_en this interrupt is generated to the ec by the host writing to the power management 1 enable 2 register register acpipm1_sts this interrupt is generated to the ec by the host writing to the power management 1 status 2 register register
MEC1322 ds00001719d-page 172 ? 2014 - 2015 microchip technology inc. 13.9 low power modes the acpi pm1 block interface may be put into a low power state by the ch ip?s power, clocks, and reset (pcr) circuitry. 13.10 description this section describes the functions of the acpi pm1 block interface in more detail. the MEC1322 implements the acpi fixed registers but includes only those bits that apply to the power button sleep button and rtc alarm events. the acpi wak_sts , slp_typ , and slp_en bits are also supported. the MEC1322 can generate sci interrupts to the host. the functions described in the following sub-sections can gen- erate a sci event on the ec_sci# pin. in the MEC1322, an sci event is considered the same as an acpi wakeup or runtime event. 13.10.1 sci event-generating functions event event bit definition power button with override pwrbtn_sts the power button has a status and an enable bit in the pm1_blk of regis- ters to provide an sci upon the button press. the status bit is software read/writable by the ec; the enable bit is read-only by the ec. it also has a status and enable bit in the pm1_blk of registers to indicate and control the power button override (fail-safe) event. these bits are not required by acpi. the pwrbtn_sts bit is set by the host to enable the generation of an sci due to the power button event. the status bit is set by the ec when it generates a power button event and is cleared by the host writing a ?1? to this bit (writing a ?0? has no effect); it can also be cleared by the ec. if the enable bit is set, the ec generates an sci power management event. pwrbtnor_sts the power button has a status and an enable bit in the pm1_blk of regis- ters to provide an sci upon the power button override.the power button override event status bit is software read/writable by the ec; the enable bit is software read-only by the ec.the enable bit for the override event is located at bit 1 in the power management 1 control register 2 (pm1_cn- trl 2).the power button bit has a status and enable bit in the runtime registers to provide an sci power management event on a button press the pwrbtnor_sts bit is set by the host to enable the generation of an sci due to the power button override event. the status bit is set by the ec when it generates a power button event and is cleared by the host writing a ?1? to this bit (writing a ?0? has no effect); it can also be cleared by the ec. if the enable bit is set, the ec generates an sci power management event. sleep button slpbtn_sts the sleep button that has a status and an enable bit in the runtime regis- ters to provide an sci power management event on a button press. the status bit is software read/writable by the ec; the enable bit is read-only by the ec. the slpbtn_sts bit is set by the host to enable the generation of an sci due to the sleep button event. the status bit is set by the ec when it gener- ates a sleep button event and is cleared by the host writing a ?1? to this bit (writing a ?0? has no effect); it can also be cleared by the ec. if the enable bit is set, the ec will generate an sci power management event.
? 2014 - 2015 microchip technology inc. ds00001719d-page 173 MEC1322 figure 13-2 describes the relationship of pm1 status and enable bits to the ec_sci# pin. 13.11 runtime registers the registers listed in the runtime register summary table are for a single instance of the acpi pm1 interface . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the runtime register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. rtc alarm rtc_sts the acpi specification requires that the rtc alarm generate a hardware wake-up event from the sleeping stat e. the rtc alarm can be enabled as an sci event and its status can be determined through bits in the runtime registers . the status bit is software read/writable by the ec; the enable bit is read-only by the ec. the rtc_sts bit is set by the host to enable the generation of an sci due to the rtc alarm event. the status bit is set by the ec when the rtc gen- erates an alarm event and is cleared by the host writing a ?1? to this bit (writ- ing a ?0? has no effect); it can also be cleared by the ec. if the enable bit is set, the ec will generate an sci power management event. figure 13-2: ec_sci# interface table 13-6: runtime regi ster base address table block instance instance number host address space base address acpi pm1 block interface 0 lpc i/o programmed bar 0 ec 32-bit internal address space 400f_1400h table 13-7: runtime registers summary offset register name 00h power management 1 status 1 register 01h power management 1 status 2 register 02h power management 1 enable 1 register 03h power management 1 enable 2 register 04h power management 1 control 1 register 05h power management 1 control 2 register event event bit definition pm1_en 2 register pm1_sts 2 register pwrbtn_sts slpbtn_sts rtc_sts ec_sci_sts ec _ pm_sts register ec_sci#
MEC1322 ds00001719d-page 174 ? 2014 - 2015 microchip technology inc. 13.11.1 power management 1 status 1 register 13.11.2 power management 1 status 2 register note 13-1 these bits are set/cleared by the ec directly i.e., wr iting ?1? sets the bit and writing ?0? clears it. these bits can also be cleared by the host software writing a one to this bit position and by vcc1_reset . writing a 0 by the host has no effect. 13.11.3 power management 1 enable 1 register 06h power management 2 control 1 register 07h power management 2 control 2 register offset 00h bits description type default reset event 7:0 reserved r - - offset 01h bits description type default reset event 7 wak_sts this bit can be set or cleared by the ec. the host writing a one to this bit can also clear this bit. r/wc ( note 13 -1 ) 00h vcc1_r eset 6:4 reserved r - - 3 pwrbtnor_sts this bit can be set or cleared by the ec to simulate a power button override event status if the power is controlled by the ec. the host writing a one to this bit can also clear this bit. the ec must generate the associated hardware event under software control. r/wc ( note 13 -1 ) 00h vcc1_r eset 2 rtc_sts this bit can be set or cleared by the ec to simulate a rtc status. the host writing a one to this bit can also clear this bit. the ec must generate the associated sci interrupt under software control. r/wc ( note 13 -1 ) 00h vcc1_r eset 1 slpbtn_sts this bit can be set or cleared by the ec to simulate a sleep button status if the sleep state is controlled by the ec. the host writing a one to this bit can also clear this bit. the ec must generate the associated sci interrupt under software control. r/wc ( note 13 -1 ) 00h vcc1_r eset 0 pwrbtn_sts this bit can be set or cleared by the ec to simulate a power button status if the power is controlled by the ec. the host writing a one to this bit can also clear this bit. the ec must generate the associated sci interrupt under software control. r/wc ( note 13 -1 ) 00h vcc1_r eset offset 02h bits description type default reset event 7:0 reserved r - - table 13-7: runtime registers summary (continued) offset register name
? 2014 - 2015 microchip technology inc. ds00001719d-page 175 MEC1322 13.11.4 power management 1 enable 2 register note 13-2 these bits are read-only by the ec. 13.11.5 power management 1 control 1 register 13.11.6 power management 1 control 2 register note 13-3 these bits are read-only by the ec. offset 03h bits description type default reset event 7:3 reserved r - - 2rtc_en this bit can be read or written by the host. it can be read by the ec. r/w ( note 13 -2 ) 00h vcc1_r eset 1 slpbtn_en this bit can be read or written by the host. it can be read by the ec. r/w ( note 13 -2 ) 00h vcc1_r eset 0 pwrbtn_en this bit can be read or written by the host. it can be read by the ec. r/w ( note 13 -2 ) 00h vcc1_r eset offset 04h bits description type default reset event 7:0 reserved r 0h vcc1_r eset offset 05h bits description type default reset event 7:6 reserved r - - 5 slp_en see table 13-8 . see table 13 -8 . 00h vcc1_r eset 4:2 slp_typ these bits can be set or cleared by the host, read by the ec. r/w ( note 13 -3 ) 00h vcc1_r eset 1 pwrbtnor_en this bit can be set or cleared by the host, read by the ec. r/w ( note 13 -3 ) 00h vcc1_r eset 0 reserved r - - table 13-8: slp_en definition host / ec r/w description host read always reads 0 write writing a 0 has no effect, writing a 1 sets this bit ec read reads the value of the bit write writing a 0 has no effect, writing a 1 clears this bit
MEC1322 ds00001719d-page 176 ? 2014 - 2015 microchip technology inc. 13.11.7 power management 2 control 1 register 13.11.8 power management 2 control 2 register 13.12 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the acpi pm1 interface . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. offset 06h bits description type default reset event 7:0 reserved r - - offset 07h bits description type default reset event 7:0 reserved r - - table 13-9: ec-only register base address table block instance instance number host address space base address acpi pm1 block inter- face 0 ec 32-bit address space 400f_1500h table 13-10: ec-only registers summary offset register name 00h power management 1 status 1 register 01h power management 1 status 2 register 02h power management 1 enable 1 register 03h power management 1 enable 2 register 04h power management 1 control 1 register 05h power management 1 control 2 register 06h power management 2 control 1 register 07h power management 2 control 2 register 10h ec_pm_sts register note: the power management status, enable and control registers in table 13-10, "ec-only registers sum- mary" are described in section 13.11, "runtime registers," on page 173 .
? 2014 - 2015 microchip technology inc. ds00001719d-page 177 MEC1322 13.12.1 ec_pm_sts register offset 10h bits description type default reset event 7:1 ud r/w 00h vcc1_r eset 0 ec_sci_sts if the ec_sci_sts bit is ?1?, an interrupt is generated on the ec_sci# pin. r/w 00h vcc1_r eset note: this register is only accessed by the ec. there is no host access to this register.
MEC1322 ds00001719d-page 178 ? 2014 - 2015 microchip technology inc. 14.0 uart 14.1 introduction the 16550 uart (universal asynchronous re ceiver/transmitter) is a full-function two pin serial port that supports the standard rs-232 interface. 14.2 references 1. eia standard rs-232-c specification 14.3 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 14.4 signal description 14.5 host interface the uart is accessed by host software via a registered interface, as defined in section 14.10, "configuration regis- ters"and section 14.11, "runtime registers". figure 14-1: i/o diagram of block table 14-1: signal description table name direction description txd output transmit serial data output. rxd input receiver serial data input. signal description uart interrupts power, clocks and reset host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 179 MEC1322 14.6 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 14.6.1 power domains 14.6.2 clock inputs 14.6.3 resets 14.7 interrupts this section defines the interrupt sources generated from this block. 14.8 low power modes the uart may be put into a low power state by the chip ?s power, clocks, and reset (pcr) circuitry. 14.9 description the uart is compatible with the 16450, the 16450 ace registers and the 16c550a. the uart performs serial-to-par- allel conversions on received characters and parallel-to-se rial conversions on transmit characters. two sets of baud rates are provided. when the 1.8432 mhz source clock is selected, standard baud rates from 50 to 115.2k are available. when the source clock is 32.26 mhz, baud rates from 126k to 2,016k are available. the character options are program- mable for 1 start; 1, 1.5 or 2 stop bits ; even, odd, sticky or no parity; and prio ritized interrupts. the uart contains a programmable baud rate generator that is capable of dividing the input clock signal by 1 to 65535. the uart is also table 14-2: power sources name description vcc1 this power well is used to power the registers and logic in this block. table 14-3: clock inputs name description 1.8432mhz_clk the uart requires a 1.8432 mhz 2% clock input for baud rate generation. 24mhz_clk 24 mhz 2% clock input. this clock may be enabled to generate the baud rate, which requires a 1.8432 mhz 2% clock input. table 14-4: reset signals name description vcc1_reset this reset is asserted when vcc1 is applied. nsio_reset this is an alternate reset condition, typically asserted when the main power rail is asserted. reset this reset is determined by the power bit signal. when the power bit signal is 1, this signal is equal to nsio_reset . when the power bit signal is 0, this signal is equal to vcc1_reset . table 14-5: system interrupts source description uart the uart interrupt event output indicates if an interrupt is pending. see table 14-13, ?interrupt control table,? on page 186 . table 14-6: ec interrupts source description uart the uart interrupt event output indicates if an interrupt is pending. see table 14-13, ?interrupt control table,? on page 186 .
MEC1322 ds00001719d-page 180 ? 2014 - 2015 microchip technology inc. capable of supporting the midi data rate. refer to the configuration registers for information on disabling, powering down and changing the base address of the uart. the uart interrupt is enabled by programming out2 of the uart to logic ?1.? because out2 is logic ?0,? it disables the uart's interrupt. the uart is accessible by both the host and the ec. 14.9.1 programmable baud rate the serial port contains a programmable baud rate generator that is capable of dividing the internal clock source by any divisor from 1 to 65535. the clock source is either the 1.8432mhz_clk clock source or the 24mhz_clk clock source. the output frequency of the baud rate generator is 16x the baud rate. two eight bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to ensure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16 bit baud counter is immediately loaded. this prevents long counts on initial load. if a 0 is loaded into the brg registers, the output divides the clock by the number 3. if a 1 is loaded, the output is the inverse of the input oscillator. if a two is loaded, the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded, the output is low for 2 bits and high for the remainder of the count. the following tables show possible baud rates. table 14-7: uart baud rates using clock source 1.8432mhz_clk desired baud rate baud_clock_sel divisor used to generate 16x clock 50 0 2304 75 0 1536 110 0 1047 134.5 0 857 150 0 768 300 0 384 600 0 192 1200 0 96 1800 0 64 2000 0 58 2400 0 48 3600 0 32 4800 0 24 7200 0 16 9600 0 12 19200 0 6 38400 0 3 57600 0 2 115200 0 1 table 14-8: uart baud rates using clock source 24mhz_clk desired baud rate baud_clock_sel divisor used to generate 16x clock 125000 1 12 136400 1 11 150000 1 10 166700 1 9 187500 1 8 214300 1 7 250000 1 6
? 2014 - 2015 microchip technology inc. ds00001719d-page 181 MEC1322 14.10 configuration registers the registers listed in the configuration register summary table are for a single instance of the uart . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the configuration register base address table. each configuration register access through the host acce ss port is via its ldn and its host access port index. ec access is a relative offset to the ec base address. 14.10.1 activate register 300000 1 5 375000 1 4 500000 1 3 750000 1 2 1500000 1 1 figure 14-2: config uration register base address table block instance instance number logical device number host address space base address uart 0 7 lpc configuration port index = 00h uart 0 ec 32-bit internal address space 400f_1f00h table 14-9: configuration register summary offset register name (mnemonic) 30h activate register f0h configuration select register offset 30h bits description type default reset event 7:1 reserved r - - 0 activate when this bit is 1, the uart logical device is powered and func- tional. when this bit is 0, the uart logical device is powered down and inactive. r/w 0b reset table 14-8: uart baud rates using clock source 24mhz_clk (continued) desired baud rate baud_clock_sel divisor used to generate 16x clock
MEC1322 ds00001719d-page 182 ? 2014 - 2015 microchip technology inc. 14.10.2 configuration select register 14.11 runtime registers the registers listed in the runtime register summary table are for a single instance of the uart . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in runtime register base address table. note 14-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. note 14-2 dlab is bit 7 of the line control register. offset f0h bits description type default reset event 7:3 reserved r - - 2polarity 1=the uart_tx and uart_rx pins functions are inverted 0=the uart_tx and uart_rx pins functions are not inverted r/w 0b reset 1power 1=the reset reset signal is derived from nsio_reset 0=the reset reset signal is derived from vcc1_reset r/w 1b reset 0 clk_src 1=the uart baud clock is derived from an external clock source 0=the uart baud clock is derived from one of the two internal clock sources r/w 0b reset table 14-10: runtime register base address table block instance instance number host address space base address ( note 14-1 ) uart 0 lpc i/o programmed bar ec 32-bit internal address space 400f_1c00h table 14-11: runtime register summary dlab ( note 14-2 ) offset register name (mnemonic) 00h receive buffer register 00h transmit buffer register 10h programmable baud rate generator lsb register 11h programmable baud rate generator msb register 01h interrupt enable register x02h fifo control register x02h interrupt identification register x03h line control register x04h modem control register x05h line status register x06h modem status register x07h scratchpad register
? 2014 - 2015 microchip technology inc. ds00001719d-page 183 MEC1322 14.11.1 receive buffer register 14.11.2 transmit buffer register 14.11.3 programmable baud rate generator lsb register 14.11.4 programmable baud rate generator msb register offset 0h (dlab=0) bits description type default reset event 7:0 received_data this register holds the received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an addi tional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the shift register is not accessible. r0h reset offset 0h (dlab=0) bits description type default reset event 7:0 transmit_data this register contains the data byte to be transmitted. the transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. w0h reset offset 00h (dlab=1) bits description type default reset event 7:0 baud_rate_divisor_lsb see section 14.9.1, "programmable baud rate" . r/w 0h reset offset 01h (dlab=1) bits description type default reset event 7 baud_clk_sel 1=if clk_src is ?0?, the baud clock is derived from the 1.8432mhz_- clk . if clk_src is ?1?, this bit has no effect 1=if clk_src is ?0?, the baud clock is derived from the 24mhz_clk . if clk_src is ?1?, this bit has no effect r/w 0h reset 6:0 baud_rate_divisor_msb see section 14.9.1, "programmable baud rate" . r/w 0h reset
MEC1322 ds00001719d-page 184 ? 2014 - 2015 microchip technology inc. 14.11.5 interrupt enable register the lower four bits of this register control the enables of th e five interrupt sources of the serial port interrupt. it is poss ible to totally disable the interrupt system by resetting bits 0 thr ough 3 of this register. simila rly, setting the appropriate bits of this register to a high, selected interrupts can be enabl ed. disabling the interrupt system inhibits the interrupt identi- fication register and disa bles any serial port interrupt out of the mec132 2. all other system func tions operate in their normal manner, including the line status and modem status registers. the contents of the interrupt enable register are described below. 14.11.6 fifo control register this is a write only register at the same location as the interrupt identification register . offset 01h (dlab=0) bits description type default reset event 7:4 reserved r - - 3emsi this bit enables the modem status interrupt when set to logic ?1?. this is caused when one of the modem status register bits changes state. r/w 0h reset 2elsi this bit enables the received line status interrupt when set to logic ?1?. the error sources causing the interrupt are overrun, parity, framing and break. the line status register must be read to deter- mine the source. r/w 0h reset 1ethrei this bit enables the transmitter holding register empty interrupt when set to logic ?1?. r/w 0h reset 0 erdai this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic ?1?. r/w 0h reset note: dma is not supported. offset 02h bits description type default reset event 7:6 recv_fifo _trigger_level these bits are used to set the trigger level for the rcvr fifo inter- rupt. w0h reset 5:4 reserved r - - 3 dma_mode_select writing to this bit has no effect on the operation of the uart. the rxrdy and txrdy pins are no t available on this chip. w0h reset 2 clear_xmit_fifo setting this bit to a logic ?1? clears all bytes in the xmit fifo and resets its counter logic to ?0?. the shift register is not cleared. this bit is self-clearing. w0h reset 1 clear_recv_fifo setting this bit to a logic ?1? clears all bytes in the rcvr fifo and resets its counter logic to ?0?. the shift register is not cleared. this bit is self-clearing. w0h reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 185 MEC1322 14.11.7 interrupt identification register by accessing this register, the host cpu can determine the highes t priority interrupt and its so urce. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the interrupt iden - tification register (refer to table 14-13 ). when the cpu accesses the iir, the serial port freezes all interrupts and indi- cates the highest priority pending interrupt to the cpu. during this cpu access, even if the serial port records new interrupts, the current indication does not change until access is completed. the contents of the iir are described below. 0 exrf enable xmit and recv fifo. setting this bit to a logic ?1? enables both the xmit and rcvr fifos. clearing this bit to a logic ?0? dis- ables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fifo mode to non-fifo (16450) mode, data is automatically cleared from the fifos. this bit must be a 1 when other bits in this register are written to or they will not be prop- erly programmed. w0h reset table 14-12: recv fifo trigger levels bit 7 bit 6 recv fifo trigger level (bytes) 00 1 14 10 8 114 offset 02h bits description type default reset event 7:6 fifo_en these two bits are set when the fifo control register bit 0 equals 1. r0h reset 5:4 reserved r - - 3:1 intid these bits identify the highest priority interrupt pending as indicated by table 14-13, "interrupt control table" . in non-fifo mode, bit[3] is a logic ?0?. in fifo mode bit[3] is set along with bit[2] when a time- out interrupt is pending. r0h reset offset 02h bits description type default reset event
MEC1322 ds00001719d-page 186 ? 2014 - 2015 microchip technology inc. 0 ipend this bit can be used in either a hardwired prioritized or polled envi- ronment to indicate whether an inte rrupt is pending. when bit 0 is a logic ?0? an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic ?1? no interrupt is pending. r1h reset table 14-13: interrupt control table fifo mode only interrupt iden tification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 1 1 0 highest receiver line sta- tus overrun error, par- ity error, framing error or break interrupt reading the line status register 0 second received data available receiver data available read receiver buf- fer or the fifo drops below the trigger level. 1 character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0 0 1 third transmitter hold- ing register empty transmitter hold- ing register empty reading the iir register (if source of interrupt) or writ- ing the transmitter holding register 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register offset 02h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 187 MEC1322 14.11.8 line control register offset 03h bits description type default reset event 7dlab divisor latch access bit (dlab). it must be set high (logic ?1?) to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic ?0?) to access the receiver buffer register, the transmitter holding register, or the interrupt enable register. r/w 0h reset 6 break_control set break control bit. when bit 6 is a logic ?1?, the transmit data out- put (txd) is forced to the spacing or logic ?0? state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. this feature enables the serial port to alert a terminal in a communications system. r/w 0h reset 5stick_parity stick parity bit. when parity is enabled it is used in conjunction with bit 4 to select mark or space parity. when lcr bits 3, 4 and 5 are 1 the parity bit is transmitted and checked as a 0 (space parity). if bits 3 and 5 are 1 and bit 4 is a 0, then the parity bit is transmitted and checked as 1 (mark parity). if bit 5 is 0 stick parity is disabled. bit 3 is a logic ?1? and bit 5 is a logic ?1?, the parity bit is transmitted and then detected by the receiver in the opposite state indicated by bit 4. r/w 0h reset 4 parity_select even parity select bit. when bit 3 is a logic ?1? and bit 4 is a logic ?0?, an odd number of logic ?1?'s is transmitted or checked in the data word bits and the parity bit. when bit 3 is a logic ?1? and bit 4 is a logic ?1? an even number of bits is transmitted and checked. r/w 0h reset 3 enable_parity parity enable bit. when bit 3 is a logic ?1?, a parity bit is gener- ated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). r/w 0h reset 2 stop_bits this bit specifies the number of stop bits in each transmitted or received serial character. table 14-14 summarizes the information. r/w 0h reset 1:0 word_length these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: r/w 0h reset table 14-14: stop bits bit 2 word length number of stop bits 0-- 1 15 bits 1.5 6 bits 2 7 bits 8 bits
MEC1322 ds00001719d-page 188 ? 2014 - 2015 microchip technology inc. the start, stop and parity bits are not included in the word length. 14.11.9 modem control register note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. table 14-15: serial character bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits offset 04h bits description type default reset event 7:5 reserved r - - 4 loopback this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic ?1?, the following occur: 1. the txd is set to the marking state (logic ?1?). 2. the receiver serial input (rxd) is disconnected. 3. the output of the transmitter shift register is ?looped back? into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem control outputs (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd). 6. the modem control output pins are forced inactive high. 7. data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter interrupts are fully operational. the modem control interrupts are also operational but the interrupts' sources are now the lower four bits of the modem control register instead of the modem control inputs. the interrupts are still controlled by the interrupt enable register. r/w 0h reset 3out2 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic ?0?, the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic ?1?, the serial port interrupt outputs are enabled. r/w 0h reset 2out1 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. r/w 0h reset 1rts this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. r/w 0h reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 189 MEC1322 14.11.10 line status register 0dtr this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic ?1?, the ndtr output is forced to a logic ?0?. when bit 0 is a logic ?0?, the ndtr output is forced to a logic ?1?. r/w 0h reset offset 05h bits description type default reset event 7 fifo_error this bit is permanently set to logic ?0? in the 450 mode. in the fifo mode, this bit is set to a logic ?1? when there is at least one parity error, framing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. r0h reset 6 transmit_error transmitter empty. bit 6 is set to a logic ?1? whenever the trans- mitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic ?0? whenever either the thr or tsr contains a data character. bit 6 is a read only bit. in the fifo mode this bit is set whenever the thr and tsr are both empty, r0h reset 5 transmit_empty transmitter holding register empty bit 5 indicates that the serial port is ready to accept a new character for transmission. in addi- tion, this bit causes the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic ?1? when a character is transferred from the transmitter holding register into the transmitter shift regis- ter. the bit is reset to logic ?0? whenever the cpu loads the trans- mitter holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. r0h reset 4 break_interrupt break interrupt. bit 4 is set to a logic ?1? whenever the received data input is held in the spacing state (logic ?0?) for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarti ng after a break is received, requires the serial data (rxd) to be logic ?1? for at least 1/2 bit time. bits 1 through 4 are the error conditions that produce a receiver line status interrupt bit 3 whenever any of the corresponding conditions are detected and the interrupt is enabled r0h reset offset 04h bits description type default reset event
MEC1322 ds00001719d-page 190 ? 2014 - 2015 microchip technology inc. 14.11.11 modem status register 3 frame_error framing error. bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic ?1? whenever the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). this bit is reset to a logic ?0? whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. r0h reset 2 parity error parity error. bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. this bit is set to a logic ?1? upon detection of a parity error and is reset to a logic ?0? whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. r0h reset 1 overrun_error overrun error. bit 1 indicates that data in the receiver buffer reg- ister was not read before the next character was transferred into the register, thereby destroying the previous character. in fifo mode, an overrun error will occur only when the fifo is full and the next character has been completely received in the shift regis- ter, the character in the shift register is overwritten but not trans- ferred to the fifo. this bit is set to a logic ?1? immediately upon detection of an overrun condition, and reset whenever the line status register is read. r0h reset 0 data_ready data ready. it is set to a logic ?1? whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic ?0? by reading all of the data in the receive buffer register or the fifo. r0h reset offset 06h bits description type default reset event 7 dcd this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to out2 in the mcr. r0h reset 6ri# this bit is the complement of the ring indicator (nri) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to out1 in the mcr. r0h reset offset 05h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 191 MEC1322 14.11.12 scratc hpad register 5dsr this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to dtr in the mcr. r0h reset 4cts this bit is the complement of the clear to send (ncts) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to nrts in the mcr. r0h reset 3 dcd delta data carrier detect (ddcd). bit 3 indicates that the ndcd input to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logic ?1?, a modem sta- tus interrupt is generated. r0h reset 2ri trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic ?0? to logic ?1?. r0h reset 1dsr delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read. r0h reset 0cts delta clear to send (dcts). bit 0 indicates that the ncts input to the chip has changed state since the last time the msr was read. r0h reset note: the modem status register (msr) only provides the current state of the uart modem control lines in loopback mode. the MEC1322 does not support external connections for the modem control inputs (ncts, ndsr, nri and ndcd) or for the four modem control outputs (ndtr, nrts, out1 and out2). offset 07h bits description type default reset event 7:0 scratch this 8 bit read/write register has no effect on the operation of the serial port. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. r/w 0h reset offset 06h bits description type default reset event
MEC1322 ds00001719d-page 192 ? 2014 - 2015 microchip technology inc. 15.0 ec interrupt aggregator 15.1 introduction the ec interrupt aggregator works in conjunction with the processor?s in terrupt interface to handle hardware interrupts and exceptions. exceptions are synchronous to instructions, are not maskable, and have higher priority than interrupts. all three excep- tions - reset, memory error, and instruction error - are hardwir ed directly to the processor. interrupts are typically asyn- chronous and are maskable. interrupts classified as wake events can be recognized without a running clock, e.g., while the MEC1322 is in sleep state. this chapter focuses on the ec interrupt aggregator . please refer to embedded controller?s documentation for more information on interrupt and exception handling. 15.2 references none 15.3 terminology none 15.4 interface figure 15-1: block diagram of ec interrupt aggregator girq8 source register girq9 source register girq10 source register girq23 source register 31 31 31 interrupt sources aoi aoi aoi aoi masking bits masking bits masking bits masking bits processor 16 31
? 2014 - 2015 microchip technology inc. ds00001719d-page 193 MEC1322 15.4.1 signal interface this block is not accessible from the pin interface. 15.4.2 host interface the registers defined for the ec interrupt aggregator are only accessible by the embedded controller via the ec-only registers . 15.5 power, clocks and reset 15.5.1 block power domain 15.5.2 block clocks none 15.5.3 block reset 15.6 interrupts this block aggregates all the interrupts targeted for the embedded controller into the source registers defined in sec- tion 15.9, "ec-only registers," on page 202 . the unmasked bits of each source register are then or?d together and routed to the embedded controller?s interrupt interface. the na me of each source register identifies the irq number of the interrupt port on the embedded controller. 15.7 low power modes this block always automatically adjusts to operate in the lowest power mode. 15.8 description the interrupt generation logic is made of 16 groups of signals, each of which cons ist of a status register, a enable reg- ister and a result register. the status and enable are latched registers. the result regi ster is a bit by bit and function of the source and enable registers. all the bits of the result r egister are or?ed together and and?ed with the corresponding bit in the block select register to form the interrupt signal that is routed to the arm interrupt controller. the result register bits may also be enabled to the nvic block via the nvic_en bit in the interrupt control register. see chapter 35.0, "ec subsystem registers" section 15.8.1 shows a representation of the interrupt structure. table 15-1: block power power well source effect on block vcc1 the ec interrupt aggregator block and registers operate on this single power well. table 15-2: block resets reset name reset description vcc1_reset this signal is used to indicate when the vcc1 logic and regis- ters in this block are reset.
MEC1322 ds00001719d-page 194 ? 2014 - 2015 microchip technology inc. figure 15-2: interrupt structure 15.8.1 wake generation the ec interrupt aggregator notifies t he chip power management fe atures to wake the system when it detects a wake capable event has occurred. this logic requires no clocks. the interrupt sources and?ed with the corresponding enable bit will be or?ed to produce a wake event the wake up sources are identified with a ?y? in the ?wake? column of the bit definitions table for each irq?s source register. 15.8.1.1 configuri ng wake interrupts all gpio inputs are wake-capable. in order for a gpio input to wake the MEC1322 from a sleep state, the interrupt detection field of the gpio pin control register must be se t to rising edge triggered, falling edge triggered, or either edge triggered. if the interrupt detection field is set to any other value, a gpio input will not trigger a wake interrupt. some of the wake capable interrupts are triggered by activity on pins that are shared with a gpio. these interrupts will only trigger a wake if the interrupt detection field of the corresponding gpio pin control register is set to rising edge triggered, falling edge triggered, or either edge triggered. application note: neither lpc accesses nor jtag debug accesses are wake capable. in order to enable lpc transactions to MEC1322 logical devices while the MEC1322 is in a sleep mode in which the main oscillator is shut off, just before entering sleep ec firmware must enable an interrupt on the falling edge of the gpio associated with the lframe# input. when responding to this lframe/gpio interrupt ec firmware s hould disable the lframe/gpio interrupt until firmware determines that it is again appropriate to enter a deep sleep mode. similarly, ec source0 enable0 int source int enable source1 sourcen . . . enable1 enablen . . . . . . . . . . . . interrupt from block nvic inputs for blocks girqx block enable nvic input for girqx bit x . . . interrupt from block interrupt from block nvic_en result to wake interface . . . . . .
? 2014 - 2015 microchip technology inc. ds00001719d-page 195 MEC1322 firmware must enable an interrupt on the falling edge of the gpio associated with jtag_clk if jtag debug accesses are required while the MEC1322 is in a sleep mode in which the main clock is turned off. 15.8.2 interrupt summary table 15-3, "interrupt event aggregator routing summary" summarizes the interrupts, wa ke capabilities and nvic vec- tor locations. table 15-4, "ec interrupt structure" summarizes the interrupts, priorities and vector locations. table 15-3: interrupt event aggregator routing summary interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt gpio140 girq8 0 yes 57 n/a gpio141 girq8 1 gpio142 girq8 2 gpio143 girq8 3 gpio144 girq8 4 gpio145 girq8 5 gpio146 girq8 6 gpio147 girq8 7 gpio150 girq8 8 gpio151 girq8 9 gpio152 girq8 10 gpio153 girq8 11 gpio154 girq8 12 gpio155 girq8 13 gpio156 girq8 14 gpio157 girq8 15 gpio160 girq8 16 gpio161 girq8 17 gpio162 girq8 18 gpio163 girq8 19 gpio164 girq8 20 gpio165 girq8 21
MEC1322 ds00001719d-page 196 ? 2014 - 2015 microchip technology inc. gpio100 girq9 0 yes 58 n/a gpio101 girq9 1 gpio102 girq9 2 gpio103 girq9 3 gpio104 girq9 4 gpio105 girq9 5 gpio106 girq9 6 gpio107 girq9 7 gpio110 girq9 8 gpio111 girq9 9 gpio112 girq9 10 gpio113 girq9 11 gpio114 girq9 12 gpio115 girq9 13 gpio116 girq9 14 gpio117 girq9 15 gpio120 girq9 16 gpio121 girq9 17 gpio122 girq9 18 gpio123 girq9 19 gpio124 girq9 20 gpio125 girq9 21 gpio126 girq9 22 gpio127 girq9 23 gpio130 girq9 24 gpio131 girq9 25 gpio132 girq9 26 gpio133 girq9 27 gpio134 girq9 28 gpio135 girq9 29 gpio136 girq9 30 table 15-3: interrupt event aggregator routing summary (continued) interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt
? 2014 - 2015 microchip technology inc. ds00001719d-page 197 MEC1322 gpio040 girq10 0 yes 59 n/a gpio041 girq10 1 gpio042 girq10 2 gpio043 girq10 3 gpio044 girq10 4 gpio045 girq10 5 gpio046 girq10 6 gpio047 girq10 7 gpio050 girq10 8 gpio051 girq10 9 gpio052 girq10 10 gpio053 girq10 11 gpio054 girq10 12 gpio055 girq10 13 gpio056 girq10 14 gpio057 girq10 15 gpio060 girq10 16 gpio061 girq10 17 gpio062 girq10 18 gpio063 girq10 19 gpio064 girq10 20 gpio065 girq10 21 gpio066 girq10 22 gpio067 girq10 23 table 15-3: interrupt event aggregator routing summary (continued) interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt
MEC1322 ds00001719d-page 198 ? 2014 - 2015 microchip technology inc. gpio000 girq11 0 yes 60 n/a gpio001 girq11 1 gpio002 girq11 2 gpio003 girq11 3 gpio004 girq11 4 gpio005 girq11 5 gpio006 girq11 6 gpio007 girq11 7 gpio010 girq11 8 gpio011 girq11 9 gpio012 girq11 10 gpio013 girq11 11 gpio014 girq11 12 gpio015 girq11 13 gpio016 girq11 14 gpio017 girq11 15 gpio020 girq11 16 gpio021 girq11 17 gpio022 girq11 18 gpio023 girq11 19 gpio024 girq11 20 gpio025 girq11 21 gpio026 girq11 22 gpio027 girq11 23 gpio030 girq11 24 gpio031 girq11 25 gpio032 girq11 26 gpio033 girq11 27 gpio034 girq11 28 gpio035 girq11 29 gpio036 girq11 30 i2c0 / smb0 girq12 0 no 61 0 i2c1 / smb1 girq12 1 1 i2c2 / smb2 girq12 2 2 i2c3 / smb3 girq12 3 3 i2c0_0_wk girq12 4 yes n/a i2c0_1_wk girq12 5 i2c2_0_wk girq12 6 i2c1_0_wk girq12 7 i2c3_0_wk girq12 8 table 15-3: interrupt event aggregator routing summary (continued) interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt
? 2014 - 2015 microchip technology inc. ds00001719d-page 199 MEC1322 dma0 girq13 16 no 62 4 dma1 girq13 17 5 dma2 girq13 18 6 dma3 girq13 19 7 dma4 girq13 20 8 dma5 girq13 21 9 dma6 girq13 22 10 dma7 girq13 23 11 dma8 girq13 24 81 dma9 girq13 25 82 dma10 girq13 26 83 dma11 girq13 27 84 lpc girq14 2 no 63 12 uart_0 girq15 0 no 64 13 reserved girq15 1 n/a emi_0 (imap) girq15 2 14 reserved girq15 3 n/a reserved girq15 4 n/a reserved girq15 5 n/a acpiec[0] ibf girq15 6 15 acpiec[0] obf girq15 7 16 acpiec[1] ibf girq15 8 17 acpiec[1] obf girq15 9 18 acpipm1 ctl girq15 10 19 acpipm1 en girq15 11 20 acpipm1 sts girq15 12 21 8042em obf girq15 13 22 8042em ibf girq15 14 23 mailbox girq15 15 24 mailbox data girq15 16 40 pecihost girq16 3 no 65 25 table 15-3: interrupt event aggregator routing summary (continued) interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt
MEC1322 ds00001719d-page 200 ? 2014 - 2015 microchip technology inc. tach_0 girq17 0 no 66 26 tach_1 girq17 1 no 27 ps2_0_wk girq17 2 yes n/a ps2_1_wk girq17 3 yes ps2_2_wk girq17 4 yes ps2_3_wk girq17 5 yes bc_int_n_wk girq17 6 yes adc_sngl girq17 10 no 28 adc_rpt girq17 11 no 29 mchp reserved girq17 12 no 30 mchp reserved girq17 13 no 31 ps2_0 girq17 14 no 32 ps2_1 girq17 15 no 33 ps2_2 girq17 16 no 34 ps2_3 girq17 17 no 35 rtc girq17 18 yes 91 rtc alarm girq17 19 yes 92 htimer girq17 20 yes 38 ksc_int girq17 21 no 39 ksc_int wake girq17 22 yes n/a rpm_int stall girq17 23 no 41 rpm_int spin girq17 24 no 42 pfr_sts girq17 25 no 43 pwm_wdt0 girq17 26 no 44 pwm_wdt1 girq17 27 no 45 pwm_wdt2 girq17 28 no 46 bcm_int err girq17 29 no 47 bcm_int busy girq17 30 no 48 spi0 tx girq18 0 no 67 36 spi0 rx girq18 1 37 spi1 tx girq18 2 55 spi1 rx girq18 3 56 pwm_wdt3 girq18 4 85 mchp reserved girq18 5 86 mchp reserved girq18 6 87 mchp reserved girq18 7 88 mchp reserved girq18 8 89 mchp reserved girq18 9 90 vcc_pwrgd girq19 0 yes 68 n/a lreset# girq19 1 gpio200 girq20 0 yes 69 n/a gpio201 girq20 1 gpio202 girq20 2 gpio203 girq20 3 table 15-3: interrupt event aggregator routing summary (continued) interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt
? 2014 - 2015 microchip technology inc. ds00001719d-page 201 MEC1322 gpio204 girq20 4 n/a girq20 5 gpio206 girq20 6 n/a girq20 7 gpio210 girq20 8 gpio211 girq20 9 timer_16_0 girq23 0 no 72 49 timer_16_1 girq23 1 50 timer_16_2 girq23 2 51 timer_16_3 girq23 3 52 timer_32_0 girq23 4 53 timer_32_1 girq23 5 54 table 15-4: ec interrupt structure vector name link register priority (default) relative priority byte offset 0 reset - high h1 00h 1 memory error ilink2 high h2 08h 2 instruction error ilink2 high h3 10h 3 irq3-reserved ilink1 level 1 (low) l27 18h 4 irq4-reserved ilink1 level 1 (low) l26 20h 5 irq5-reserved ilink1 level 1 (low) l25 28h 6 irq6-reserved ilink2 level 2 (mid) m2 30h 7 irq7-reserved ilink2 level 2 (mid) m1 38h 8 irq8 ilink1 level 1 (low) l24 40h 9 irq9 ilink1 level 1 (low) l23 48h 10 irq10 ilink1 level 1 (low) l22 50h 11 irq11 ilink1 level 1 (low) l21 58h 12 irq12 ilink1 level 1 (low) l20 60h 13 irq13 ilink1 level 1 (low) l19 68h 14 irq14 ilink1 level 1 (low) l18 70h 15 irq15 ilink1 level 1 (low) l17 78h 16 irq16 ilink1 level 1 (low) l16 80h 17 irq17 ilink1 level 1 (low) l15 88h 18 irq18 ilink1 level 1 (low) l14 90h 19 irq19 ilink1 level 1 (low) l13 98h 20 irq20 ilink1 level 1 (low) l12 a0h 21 irq21 ilink1 level 1 (low) l11 a8h 22 irq22 ilink1 level 1 (low) l10 b0h 23 irq23 ilink1 level 1 (low) l9 b8h 24 irq24 ilink1 level 1 (low) l8 c0h 25 irq25 ilink1 level 1 (low) l7 c8h 26 irq26 ilink1 level 1 (low) l6 d0h table 15-3: interrupt event aggregator routing summary (continued) interrupt aggregator irq aggregator bit wake event aggregated nvic direct nvic interrupt
MEC1322 ds00001719d-page 202 ? 2014 - 2015 microchip technology inc. 15.8.3 disabling interrupts the block enable clear register and block enable set register should not be used for disabling and enabling interrupts for software operations i.e., critical sections. the arm enable disable mechanisms should be used. 15.9 ec-only registers the configuration registers listed in ec-only register summary table are for a single instance of the ec interrupt aggre- gator. the addresses of each register list ed in the summary table are defined as a relative offset to the host ?begin address? defined in the ec-only register base address table. note 15-1 the begin address indicates the location of the first register accessable at offset 00h in the interrupt aggregator ec-only address space. 27 irq27 ilink1 level 1 (low) l5 d8h 28 irq28 ilink1 level 1 (low) l4 e0h 29 irq29 ilink1 level 1 (low) l3 e8h 30 irq30 ilink1 level 1 (low) l2 f0h 31 irq31 ilink1 level 1 (low) l1 f8h note: irq vector 31 is the highest l1 priority table 15-5: ec-only regi ster address range table instance name instance number host address space begin address ( note 15-1 ) interrupt aggregator 0 ec 32-bit internal address space 4000_c000h table 15-6: ec-only register summary offset register name 00h girq8 source register 04h girq8 enable set register 08h girq8 result register 0ch girq8 enable clear register 14h girq9 source register 18h girq9 enable set register 1ch girq9 result register 20h girq9 enable clear register 28h girq10 source register 2ch girq10 enable set register 30h girq10 result register 34h girq10 enable clear register 3ch girq11 source register 40h girq11 enable set register 44h girq11 result register 48h girq11 enable clear register table 15-4: ec interrupt structure (continued) vector name link register priority (default) relative priority byte offset
? 2014 - 2015 microchip technology inc. ds00001719d-page 203 MEC1322 50h girq12 source register 54h girq12 enable set register 58h girq12 result register 5ch girq12 enable clear register 64h girq13 source register 68h girq13 enable set register 6ch girq13 result register 70h girq13 enable clear register 78h girq14 source register 7ch girq14 enable set register 80h girq14 result register 84h girq14 enable clear register 8ch girq15 source register 90h girq15 enable set register 94h girq15 result register 98h girq15 enable clear register a0h girq16 source register a4h girq16 enable set register a8h girq16 result register ach girq16 enable clear register b4h girq17 source register b8h girq17 enable set register bch girq17 result register c0h girq17 enable clear register c8h girq18 source register cch girq18 enable set register d0h girq18 result register d4h girq18 enable clear register dch girq19 source register e0h girq19 enable set register e4h girq19 result register e8h girq19 enable clear register f0h girq20 source register f4h girq20 enable set register f8h girq20 result register fch girq20 enable clear register 104h girq21 source register 108h girq21 enable set register 10ch girq21 result register 110h girq21 enable clear register 118h girq22 source register 11ch girq22 enable set register 120h girq22 result register 124h girq22 enable clear register table 15-6: ec-only regist er summary (continued) offset register name
MEC1322 ds00001719d-page 204 ? 2014 - 2015 microchip technology inc. all of the girqx source, enable, and result registers have the same format. the following tables define the generic format for each of these registers. the bit definitions are defined in the sections that follow. the r/wc bits are sticky status bits indicating the state of interrupt source before the interrupt enable bit. girq enable set [31:0] each girqx bit can be individually enabled to assert an interrupt event. 0= writing a zero has no effect. 1= writing a one will enable respective girqx. reading always returns the current value of the girqx enable bit. the state of the girqx enable bit is determined by the corresponding girqx enable set bit and the girqx enable clear bit. (0=disabled, 1-enabled) 12ch girq23 source register 130h girq23 enable set register 134h girq23 result register 138h girq23 enable clear register 200h block enable set register 204h block enable clear register 208h block irq vector register note: the behavior of the enable bit controlled by the girqx enable set and girqx enable clear registers, the girqx source bit, and the girqx result bit are illustrated in section 15.8.1, "wake generation," on page 194 . table 15-7: girqx source register offset - 32-bit size power vcc1 0000_0000h vcc1_reset default bit d31 d30 d29 ? ? ? d2 d1 d0 type r r/wc except for reserved bits, which are r bit name reserved see tables in the following subsections table 15-8: girqx enable set register offset - 32-bit size power vcc1 0000_0000h vcc1_reset default bit d31 d30 d29 ? ? ? d2 d1 d0 type r r/ws except for reserved bits, which are r bit name reserved see tables in the following subsections table 15-6: ec-only register summary (continued) offset register name
? 2014 - 2015 microchip technology inc. ds00001719d-page 205 MEC1322 girqx interrupt result bits d30 down to d0 are defined in the following subsections reflect the state of the girqx interrupt source after the enable bit. the girqx result bits are or?d together to generate the irqx vector. bit d31 bit d31 is hard-coded to ?1?. girqx enable clear[31:0] each girqx bit can be individually disabled to assert an interrupt event. 0= writing a zero has no effect. 1= writing a one will disable respective girqx. reading always returns the current value of the girqx enable bit. the state of the girqx enable bit is determined by the corresponding girqx enable set bit and the girqx enable clear bit. (0=disabled, 1-enabled) 15.9.1 girq8 table 15-9: girqx result register offset - 32-bit ec size power vcc1 8000_0000h vcc1_reset default bit d31 d30 d29 ? ? ? d2 d1 d0 type rr bit name ?1? see tables in the following subsections table 15-10: girqx enable clear register offset - 32-bit size power vcc1 0000_0000h vcc1_reset default bit d31 d30 d29 ? ? ? d2 d1 d0 type r r/wc except for reserved bits, which are r bit name reserved see tables in the following subsections table 15-11: bit definitions for girq8 source, enable, and result registers bit block instance name source name wake source description [7:0] gpio[147:140] gpio_event y bits[0:7] are controlled by the gpio_event s gener- ated by gpio140 through gpio147, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and fall- ing edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function.
MEC1322 ds00001719d-page 206 ? 2014 - 2015 microchip technology inc. 15.9.2 girq9 [15:8] gpio[157:150] gpio_event y bits[8:15] are controlled by the gpio_event s gener- ated by gpio150 through gpio157, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and fall- ing edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [21:16] gpio[165:160] gpio_event y bits[16:21] are controlled by the gpio_event s gen- erated by gpio160 through gpio165, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and fall- ing edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [30:22] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15- 8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-12: bit definitions for girq9 source, enable, and result registers bit block instance name source name wake source description [7:0] gpio[107:100] gpio_event y bits[0:7] are controlled by the gpio_event s generated by gpio100 through gpio107, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [15:8] gpio[117:110] gpio_event y bits[8:15] are controlled by the gpio_event s gener- ated by gpio110 through gpio117, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [23:16] gpio[127:120] gpio_event y bits[16:23] are controlled by the gpio_event s gener- ated by gpio120 through gpio127, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. table 15-11: bit definitions for girq8 source, enable, and result registers bit block instance name source name wake source description
? 2014 - 2015 microchip technology inc. ds00001719d-page 207 MEC1322 15.9.3 girq10 [30:24] gpio[136:130] gpio_event y bits[24:30] are controlled by the gpio_event s gener- ated by gpio130 through gpio136, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-13: bit definitions for girq10 source, enable, and result registers bit block instance name source name wake source description [7:0] gpio[047:040] gpio_event y bits[0:7] are controlled by the gpio_event s generated by gpio040 through gpio047, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [15:8] gpio[057:050] gpio_event y bits[8:15] are controlled by the gpio_event s generated by gpio050 through gpio057, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [23:16] gpio[067:060] gpio_event y bits[16:23] are controlled by the gpio_event s generated by gpio060 through gpio067, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [30:24] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-12: bit definitions for girq9 source, enable, and result registers bit block instance name source name wake source description
MEC1322 ds00001719d-page 208 ? 2014 - 2015 microchip technology inc. 15.9.4 girq11 15.9.5 girq12 table 15-14: bit definitions for girq11 source, enable, and result registers bit block instance name source name wake source description [7:0] gpio[007:000] gpio_event y bits[0:7] are controlled by the gpio_event s generated by gpio000 through gpio007, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [15:8] gpio[017:010] gpio_event y bits[8:15] are controlled by the gpio_event s generated by gpio010 through gpio017, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [23:16] gpio[027:020] gpio_event y bits[16:23] are controlled by the gpio_event s generated by gpio020 through gpio027, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [30:24] gpio[036:030] gpio_event y bits[24:30] are controlled by the gpio_event s generated by gpio030 through gpio036, respectively. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-15: bit definitions for girq12 source, enable, and result registers bit block instance name source name wake source description 0 i2c0 / smb0 smb n i2c/smbus controller 0 interrupt. this interrupt is signaled when the i2c/smbus controller 0 asserts its interrupt request. 1 i2c1 / smb1 smb n i2c/smbus controller 1 interrupt. this interrupt is signaled when the i2c/smbus controller 1 asserts its interrupt request. 2 i2c2 / smb2 smb n i2c/smbus controller 2 interrupt. this interrupt is signaled when the i2c/smbus controller 2 asserts its interrupt request.
? 2014 - 2015 microchip technology inc. ds00001719d-page 209 MEC1322 15.9.6 girq13 3 i2c3 / smb3 smb n i2c/smbus controller 3 interrupt. this interrupt is signaled when the i2c/smbus controlle r 3 asserts its interrupt request. 4 i2c0_0_wk smb y i2c/smbus controller 0 (port 0) wake interrupt. this inter- rupt is signaled when there is activity on the i2c/smbus controller 0 port 0 data pin, i2c0_dat0 (see note 15-2 on page 215 ). 5 i2c0_1_wk smb y i2c/smbus controller 0 (port 1) wake interrupt. this inter- rupt is signaled when there is activity on the i2c/smbus controller 0 port 1 data pin, i2c0_dat1 (see note 15-2 on page 215 ). 6 i2c2_0_wk smb y i2c/smbus controller 2 (port 0) wake interrupt. this inter- rupt is signaled when there is activity on the i2c/smbus controller 2 (port 0) data pin, i2c2_dat0 (see note 15-2 on page 215 ). 7 i2c1_0_wk smb y i2c/smbus controller 1 (port 0) wake interrupt. this inter- rupt is signaled when there is activity on the i2c/smbus controller 1 port 0 data pin, i2c1_dat0 (see note 15-2 on page 215 ). 8 i2c3_0_wk smb y i2c/smbus controller 3 (port 0) wake interrupt. this inter- rupt is signaled when there is activity on the i2c/smbus controller 3 port 0 data pin, i2c3_dat0 (see note 15-2 on page 215 ). [30:9] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-16: bit definitions for girq13 source, enable, and result registers bit block instance name source name wake source description [15:0] reserved reserved n reserved 16 irq_dma0 dma0 n direct memory access channel 0 17 irq_dma1 dma1 n direct memory access channel 1 18 irq_dma2 dma2 n direct memory access channel 2 19 irq_dma3 dma3 n direct memory access channel 3 20 irq_dma4 dma4 n direct memory access channel 4 21 irq_dma5 dma5 n direct memory access channel 5 22 irq_dma6 dma6 n direct memory access channel 6 23 irq_dma7 dma7 n direct memory access channel 7 24 irq_dma8 dma8 n direct memory access channel 8 25 irq_dma9 dma9 n direct memory access channel 9 26 irq_dma10 dma10 n direct memory access channel 10 27 irq_dma11 dma11 n direct memory access channel 11 [30:28] reserved reserved n reserved table 15-15: bit definitions for girq12 source, enable, and result registers bit block instance name source name wake source description
MEC1322 ds00001719d-page 210 ? 2014 - 2015 microchip technology inc. 15.9.7 girq14 15.9.8 girq15 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-17: bit definitions for girq14 source, enable, and result registers bit block instance name source name wake source description [1:0] reserved reserved n reserved 2 irq_lpc lpc_inter- nal_err n the lpc_internal_err event is sourced by bit d0 of the host bus error register. [30:3] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-18: bit definitions for girq15 source, enable, and result registers bit block instance name source name wake source description 0uart_0 uart n the uart interrupt event output indicates if an interrupt is pending. see table 14-13, ?interrupt control table,? on page 186. 1 reserved reserved n reserved 2emi_0 host-to-ec n communication event notifying the embedded controller that the host has written to the host-to-ec register. 5:3 reserved reserved n reserved 6 acpi_ec[0] ibf ec_ibf n ec_ibf interrupt is asserted when the ibf in the status ec-register is set to ?1?. 7 acpi_ec[0] obf ec_obf n ec_obf interrupt is asserted when the obf in the sta- tus ec-register is cleared to ?0?. 8 acpi_ec[1] ibf ec_ibf n ec_ibf interrupt is asserted when the ibf in the status ec-register is set to ?1?. 9 acpi_ec[1] obf ec_obf n ec_obf interrupt is asserted when the obf in the sta- tus ec-register is cleared to ?0?. 10 acpi_pm1_ctl acpipm1_ctl n pm1_ctl2 written by host 11 acpipm1 en acpipm1_en n pm1_en2 written by host 12 acpipm1 sts acpipm1_sts n pm1_sts2 written by host 13 8042em obf 8042em_obf n interrupt generated by the host reading either data or aux data from the data register 14 8042em ibf 8042em_ibf n interrupt generated by the host writing either data or com- mand to the data register 15 mbx mbx host-to-ec n interrupt generated for host-to-ec events for writes to the host-to-ec mailbox register table 15-16: bit definitions for girq13 source, enable, and result registers bit block instance name source name wake source description
? 2014 - 2015 microchip technology inc. ds00001719d-page 211 MEC1322 15.9.9 girq16 15.9.10 girq17 16 mbx_data mbx_data n interrupt generated for host writes to mailbox data regis- ter [30:17] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-19: bit definitions for girq16 source, enable, and result registers bit block instance name source name wake source description [2:0] reserved reserved n reserved 3 pecihost pecihost npeci host [30:4] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-20: bit definitions for girq17 source, enable, and result registers bit block instance name source name wake source description 0 irq_tach0 tach n this internal signal is generated from the or?d result of the status events, as defined in the tachx status regis- ter. . 1 irq_tach1 tach n this internal signal is generated from the or?d result of the status events, as defined in the tachx status regis- ter. 2 ps2_0_wk ps2_dat0 pin y ps2_0 start detect from pin signal ps2_dat0 (see note 15-2 on page 215 ). 3 ps2_1_wk ps2_dat1 pin y ps2_1 start detect from pin signal ps2_dat1 (see note 15-2 on page 215 ). 4 ps2_2_wk ps2_dat2 pin y ps2_2 start detect from pin signal ps2_dat2 (see note 15-2 on page 215 ). 5 ps2_3_wk ps2_dat3 pin y ps2_3 start detect from pin signal ps2_dat3 (see note 15-2 on page 215 ). 6 bc_int_n_wk bc_link y interrupt from the bc_link companion bc_int# pin (see note 15-2 on page 215 ). [9:7] reserved reserved n reserved 10 adc_sngl adc_single_int n interrupt signal from adc controller to ec for single- sample adc conversion 11 adc_rpt adc_repeat_int n interrupt signal from adc controller to ec for repeated adc conversion 12 mchp reserved mchp reserved n mchp reserved table 15-18: bit definitions for girq15 source, enable, and result registers bit block instance name source name wake source description
MEC1322 ds00001719d-page 212 ? 2014 - 2015 microchip technology inc. 15.9.11 girq18 13 mchp reserved mchp reserved n mchp reserved 14 ps2_0 ps2 act n ps2_0 activity interrupt from ps/2 block 15 ps2_1 ps2 act n ps2_1 activity interrupt from ps/2 block 16 ps2_2 ps2 act n ps2_2 activity interrupt from ps/2 block 17 ps2_3 ps2 act n ps2_3 activity interrupt from ps/2 block 18 rtc rtc y rtc interrupt 19 rtc alarm rtc alarm y rtc alarm interrupt 20 htimer htimer y signal indicating that the hibernation timer is enabled and has expired. 21 keyscan ksc_int n keyboard scan interface runtime interrupt 22 keyscan wake ksc_int_wake y keyboard scan interface wake interrupt 23 rpm_int stall fan stall status interrupt n rpm-pwm interface drive_fail & fan_spin indica- tion 24 rpm_int spin fan fail/spin sta- tus interrupt n rpm-pwm interface spin indication 25 pfr_status pfr_status n power-fail and reset status register events (vbat por and wdt). 26 pwm_wdt[0] pwm_wdt n pwm watchdog time out interrupt from blinking/breathing pwm block 27 pwm_wdt[1] pwm_wdt n pwm watchdog time out interrupt from blinking/breathing pwm block 28 pwm_wdt[2] pwm_wdt n pwm watchdog time out interrupt from blinking/breathing pwm block 29 bcm_err bcm_int err n bc_link master error flag interrupt 30 bcm_busy_- clr bcm_int busy n bc_link master busy clear flag interrupt 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-21: bit definitions for girq18 source, enable, and result registers bit block instance name source name wake source description 0 spi0 tx txbe_sts n spi controller 0 interrupt output to ec driven by txbe status bit 1spi0 rx rxbf_sts n spi controller 0 interrupt output to ec driven by rxbe status bit 2 spi1 tx txbe_sts n spi controller 1 interrupt output to ec driven by txbe status bit 3spi1 rx rxbf_sts n spi controller 1 interrupt output to ec driven by rxbe status bit 4 pwm_wdt[3] pwm_wdt n pwm watchdog time out interrupt from blinking/breathing pwm block 5 mchp reserved mchp reserved n mchp reserved table 15-20: bit definitions for girq17 source, enable, and result registers bit block instance name source name wake source description
? 2014 - 2015 microchip technology inc. ds00001719d-page 213 MEC1322 15.9.12 girq19 15.9.13 girq20 6 mchp reserved mchp reserved n mchp reserved 7 mchp reserved mchp reserved n mchp reserved 8 mchp reserved mchp reserved n mchp reserved 9 mchp reserved mchp reserved n mchp reserved [30:10] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-22: bit definitions for girq19 source, enable, and result registers bit block instance name source name wake source description 0 vcc_pwrgd vcc_pwrgd y vcc_pwrgd interrupt from pin (see note 15-2 on page 215 ). 1 lreset# lreset# y lreset# in terrupt from pin (see note 15-2 on page 215 ). [30:2] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-23: bit definitions for girq20 source, enable, and result registers bit block instance name source name wake source description [4:0] gpio[204:200] gpio_event y bits[0:4] are controlled by the gpio_event s generated by gpio200 through gpio204, respectively. the gpio interface can generate an interrupt source event on a high level, low le vel, rising e dge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. 5 reserved reserved n reserved 6 gpio206 gpio_event y bit 6 is controlled by the gpio_event s generated by gpio206. the gpio interface can generate an interrupt source event on a high level, low le vel, rising e dge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. 7 reserved reserved n reserved table 15-21: bit definitions for girq18 source, enable, and result registers bit block instance name source name wake source description
MEC1322 ds00001719d-page 214 ? 2014 - 2015 microchip technology inc. 15.9.14 girq21 15.9.15 girq22 15.9.16 girq23 [9:8] gpio[211:210] gpio_event y bits[8:9] are controlled by the gpio_event s generated by gpio210 through gpio211, respectively. the gpio interface can generate an interrupt source event on a high level, low le vel, rising e dge and falling edge, as configured by the interrupt detection (int_det) bits in the pin control register associated with the gpio signal function. [11:10] mchp reserved mchp reserved n/a mchp reserved [30:12] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-24: bit definitions for girq21 source, enable, and result registers bit block instance name source name wake source description [1:0] mchp reserved n/a n/a n/a [30:2] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-25: bit definitions for girq22 source, enable, and result registers bit block instance name source name wake source description [30:0] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. table 15-26: bit definitions for girq23 source, enable, and result registers bit block instance name source name wake source description 0 16-bit timer_0 timer_32_x n this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourc ed by the tevent_interrupt status bit if enabled. table 15-23: bit definitions for girq20 source, enable, and result registers bit block instance name source name wake source description
? 2014 - 2015 microchip technology inc. ds00001719d-page 215 MEC1322 note 15-2 all wakeup interrupts associated with pins must be configured as falling edge interrupts through the associated gpio control register. 15.9.17 block enable set register irq vector enable set [31:0] each irq vector can be individually enabled to assert an interrupt event to the ec. 0= writing a zero has no effect. 1 16-bit timer_1 timer_32_x n this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourc ed by the tevent_interrupt status bit if enabled. 2 16-bit timer_2 timer_32_x n this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourc ed by the tevent_interrupt status bit if enabled. 3 16-bit timer_3 timer_32_x n this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourc ed by the tevent_interrupt status bit if enabled. 4 32-bit timer_0 timer_32_x n this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourc ed by the tevent_interrupt status bit if enabled. 5 32-bit timer_1 timer_32_x n this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourc ed by the tevent_interrupt status bit if enabled. [30:6] reserved reserved n reserved 31 n/a n/a n see table 15-7, "girqx source register" , table 15-8, "girqx enable set register" , table 15-10, "girqx enable clear register" , and table 15-9, "girqx result register" for a definition of this bit for the source, enable, and result registers. offset 200h 32-bit size power vcc1 0000_0000h vcc1_reset default bit d31 d30 d29 d28 d27 d26 d25 d24 type r rrrrr r r bit name reserved bit d23 d22 d21 d20 d19 d18 d17 d16 type r/ws r/ws r/ws r/ws r/ws r/ws r/ws r/ws bit name irq vector enable set [23:16] bit d15 d14 d13 d12 d11 d10 d9 d8 type r/ws r/ws r/ws r/ws r/ws r/ws r/ws r/ws bit name irq vector enable set [15:8] bit d7 d6d5d4d3d2 d1 d0 type r rrrrr r r bit name reserved table 15-26: bit definitions for girq23 source, enable, and result registers bit block instance name source name wake source description
MEC1322 ds00001719d-page 216 ? 2014 - 2015 microchip technology inc. 1= writing a one will enable respective irq i . reading always returns the current value of the irq i vector enable bit. the state of the irq i vector enable bit is determined by the corresponding irq i vector enable set bit and the irq i vector enable clear bit. (0=disabled, 1-enabled) 15.9.18 block enable clear register irq vector enable clear[31:0] each irq vector can be individually disabled to assert an interrupt event to the ec. 0= writing a zero has no effect. 1= writing a one will disable respective irq i vector. reading always returns the current value of the irq i vector enable bit. the state of the irq i vector enable bit is determined by the corresponding irq i vector enable set bit and the irq i vector enable clear bit. (0=disabled, 1-enabled) 15.9.19 block irq vector register offset 204h 32-bit size power vcc1 0000_0000h vcc1_reset default bit d31 d30 d29 d28 d27 d26 d25 d24 type r rrrrr r r bit name reserved bit d23 d22 d21 d20 d19 d18 d17 d16 type r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name irq vector enable clear [23:16] bit d15 d14 d13 d12 d11 d10 d9 d8 type r/wc r/wc r/wc r/wc r/wc r/wc r/wc r/wc bit name irq vector enable clear [15:8] bit d7 d6d5d4d3d2 d1 d0 type r rrrrr r r bit name reserved offset 208h 32-bit size power vcc1 0000_0000h vcc1_reset default bit d31 d30 d29 d28 d27 d26 d25 d24 type r rrrrr r r bit name reserved bit d23 d22 d21 d20 d19 d18 d17 d16 type r rrrrr r r
? 2014 - 2015 microchip technology inc. ds00001719d-page 217 MEC1322 irq vector [31:0] each read only bit reflects the current state of the irq i vector to the ec. bit name irq vector [23:16] bit d15 d14 d13 d12 d11 d10 d9 d8 type r rrrrr r r bit name irq vector [15:8] bit d7 d6d5d4d3d2 d1 d0 type r rrrrr r r bit name reserved note: if the irq i vector is disabled via the block enable clear register the corresponding irq i vector to the ec is forced to 0. if the irq i vector is enabled, the corresponding irq i vector to the ec represents the current status of the irq event.
MEC1322 ds00001719d-page 218 ? 2014 - 2015 microchip technology inc. 16.0 watchdog timer (wdt) 16.1 introduction the function of the watchdog timer is to provide a mechanism to detect if the internal embedded controller has failed. when enabled, the watchdog timer (wdt) circuit will generate a wdt event if the user program fails to reload the wdt within a specified length of time known as the wdt interval. 16.2 references no references have been cited for this chapter. 16.3 terminology there is no terminology defined for this chapter. 16.4 interface this block is designed to be accessed inte rnally via a registered host interface or externally via the signal interface. 16.5 host interface the registers defined for the watchdog timer (wdt) are accessible by the embedded controller as indicated in section 16.8, "ec-only registers" . all registers accesses are synchronized to t he host clock and complete immediately. regis- ter reads/writes are not delayed by the 32khz_clk . figure 16-1: i/o diagram of block watchdog timer (wdt) clock inputs wdt event resets host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 219 MEC1322 16.6 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 16.6.1 power domains 16.6.2 clock inputs 16.6.3 resets 16.7 description 16.7.1 wdt operation 16.7.1.1 wdt activation mechanism the wdt is activated by the following sequen ce of operations during normal operation: 1. load the wdt load register with the count value. 2. set the wdt enable bit in the wdt control register . the wdt activation mechanism starts the wdt decrementing counter. 16.7.1.2 wdt deactivation mechanism the wdt is deactivated by the clearing the wdt enable bit in the wdt control register . the wdt deactivation mech- anism places the wdt in a low power state in which clock are gated and the counter stops decrementing. 16.7.1.3 wdt reload mechanism the wdt must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise, the wdt will underflow and a wdt event will be generated and the wdt status bit will be set in the wdt control register . it is the responsibility of the user program to continually execut e code which reloads the watchdog timer, causing the counter to be reloaded there are three methods of reloading the wdt: a write to the wdt load register , a write to the wdt kick register , or wdt event. table 16-1: power sources name description vcc1 the logic and registers implemented in this block reside on this single power well. table 16-2: clock inputs name description 32khz_clk the 32khz_clk clock input is the clock so urce to the watchdog timer functional logic, including the counter. table 16-3: reset signals name description vcc1_reset power on reset to the block. this signal resets all the register and logic in this block to its default state. table 16-4: reset output event source description wdt event pulse generated when wdt expires. this signal is used to reset the embedded controller and its subsystem. the event is cleared after an vcc1_reset .
MEC1322 ds00001719d-page 220 ? 2014 - 2015 microchip technology inc. 16.7.1.4 wdt interval the wdt interval is the time it takes for the wdt to decrements from the wdt load register value to 0000h. the wdt count register value takes 33/ 32khz_clk seconds (ex. 33/32.768 khz = 1.007ms) to decrement by 1 count. 16.8 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the watchdog timer (wdt) . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 16.8.1 wdt load register 16.8.2 wdt control register table 16-5: ec-only register base address table block instance instance number host address space base address wdt 0 ec 32-bit internal address space 4000_0400h table 16-6: ec-only register summary offset register name (mnemonic) 00h wdt load register 04h wdt control register 08h wdt kick register 0ch wdt count register offset 00h bits description type default reset event 15:0 wdt load writing this field reloads the watch dog timer counter. r/w fh vcc1_r eset offset 04h bits description type default reset event 7:2 reserved r - - 1 wdt status wdt_rst is set by hardware if the last reset of MEC1322 was caused by an underflow of the wdt. see section 16.7.1.3, "wdt reload mechanism," on page 219 for more information. this bit must be cleared by the ec firmware writing a ?1? to this bit. writing a ?0? to this bit has no effect. r/wc 0b vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 221 MEC1322 16.8.3 wdt kick register 16.8.4 wdt count register 0 wdt enable in wdt operation , the wdt is activated by the sequence of opera- tions defined in section 16.7.1.1, "wdt activation mechanism" and deactivated by the sequence of operations defined in section 16.7.1.2, "wdt deactivation mechanism" . 0 = block disabled 1 = block enabled note: the default of the wdt is inactive. r/w 0b vcc1_r eset offset 08h bits description type default reset event 7:0 kick the wdt kick register is a strobe. reads of the wdt kick register return 0. writes to the wdt kick register cause the wdt to reload the wdt load register value and start decrementing when the wdt enable bit in the wdt control register is set to ?1?. when the wdt enable bit in the wdt control register is cleared to ?0?, writes to the wdt kick register have no effect. wn/a vcc1_r eset offset 0ch bits description type default reset event 15:0 wdt count this read-only register provide the current wdt count. rfh vcc1_r eset offset 04h bits description type default reset event
MEC1322 ds00001719d-page 222 ? 2014 - 2015 microchip technology inc. 17.0 basic timer 17.1 introduction this timer block offers a simple mechanism for firmware to maintain a time base. this timer may be instantiated as 16 bits or 32 bits. the name of the timer instance indicates the size of the timer. 17.2 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 17.3 signal description there are no external signals for this block. 17.4 host interface the embedded controller may access this block via the registers defined in section 17.9, "ec-only registers," on page 224 . 17.5 power, clocks and reset this section defines the power, clock, and reset parameters of the block. figure 17-1: i/o diagram of block basic timer signal description interrupts host interface clock inputs resets
? 2014 - 2015 microchip technology inc. ds00001719d-page 223 MEC1322 17.5.1 power domains 17.5.2 clock inputs 17.5.3 resets 17.6 interrupts 17.7 low power modes the basic timer may be put into a low pow er state by the chip?s po wer, clocks, and reset (pcr) circuitry. this block is only be permitted to enter low power modes when the block is not active. the sleep state of this timer is as follows: ? asleep while the block is not enabled ? asleep while the block is not running (start inactive). ? asleep while the block is halted (even if running). the block is active while start is active. table 17-1: power sources name description vcc1 the timer control logic and registers are all implemented on this single power domain. table 17-2: clock inputs name description 48 mhz ring oscillator this is the clock source to the time r logic. the pre-scaler may be used to adjust the minimum resolution per bit of the counter. table 17-3: reset signals name description vcc1_reset this reset signal, which is an input to this block, resets all the logic and registers to their initial default state. soft reset this reset signal, which is created by this block, resets all the logic and registers to their initial default state. this reset is generated by the block when the soft_reset bit is set in the timer control register register. timer_reset this reset signal, which is created by this block, is asserted when either the vcc1_reset or the soft reset signal is asserted. the vcc1_re- set and soft reset signals are or?d together to create this signal. table 17-4: ec interrupts source description timer_16_ x this interrupt event fires when a 16-bit timer x reaches its limit. this event is sourced by the event_interrupt status bit if enabled. timer_32_ x this interrupt event fires when a 32-bit timer x reaches its limit. this event is sourced by the t event_interrupt status bit if enabled.
MEC1322 ds00001719d-page 224 ? 2014 - 2015 microchip technology inc. 17.8 description this timer block offers a simple mechanism for firmware to maintain a time base in the design. the timer may be enabled to execute the following features: ? programmable resolution per lsb of the counter vi a the pre-scale bits in the timer control register ? programmable as either an up or down counter ? one-shot or continuous modes ? in one-shot mode the auto restart feature stops the counter when it reaches its limit and generates a level event. ? in continuous mode the auto restart feature restarts th at counter from the programmed preload value and gener- ates a pulse event. ? counter may be reloaded, halted, or started via the timer control register ? block may be reset by either a power on reset (por) or via a soft reset. 17.9 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the basic timer. the addresses of each register listed in this table are defined as a rela tive offset to the host ?base address? defined in the ec-only register base address table. figure 17-2: block diagram table 17-5: ec-only register base address table block instance instance number host address space base address timer16 (16-bit timer) 0 ec 32-bit internal address space 4000_0c00h timer16 (16-bit timer) 1 ec 32-bit internal address space 4000_0c20h timer16 (16-bit timer) 2 ec 32-bit internal address space 4000_0c40h timer16 (16-bit timer) 3 ec 32-bit internal address space 4000_0c60h timer32 (32-bit timer) 0 ec 32-bit internal address space 4000_0c80h timer32 (32-bit timer) 1 ec 32-bit internal address space 4000_0ca0h host interface basic timer regs timer logic pre-scaler 48 mhz
? 2014 - 2015 microchip technology inc. ds00001719d-page 225 MEC1322 the base address indicates where the first register can be accessed in a particular address space for a block instance. 17.9.1 timer count register 17.9.2 timer preload register 17.9.3 timer status register table 17-6: runtime register summary offset register name 00h timer count register 04h timer preload register 08h timer status register 0ch timer int enable register 10h timer control register offset 00h bits description type default reset event 31:0 counter this is the value of the timer counter. this is updated by hardware but may be set by firmware. if it is set while the hardware timer is operating, functionality can not be maintained. when read, it is buff- ered so single byte reads will be able to catch the full 4 byte register without it changing. the size of the counter is indicated by the instance name. bits 0 to (size-1) are r/w counter bits. bits 31 down to size are reserved. reads return 0 and writes have no effect. r/w 0h tim- er_reset offset 04h bits description type default reset event 31:0 pre_load this is the value of the timer pre-load for the counter. this is used by h/w when the counter is to be restarted automati cally; this will become the new value of the counter upon restart. the size of the pre-load value is the same as the size of the counter. the size of the counter is indicated by the instance name. bits 0 to (size-1) ar e r/w pre-load bits. bits 31 down to size are reserved. reads return 0 and writes have no effect. r/w 0h tim- er_reset offset 08h bits description type default reset event 31:0 reserved r - - 0 event_interrupt this is the interrupt status that fires when the timer reaches its limit. this may be level or a self clear ing signal cycle pulse, based on the auto_restart bit in the timer control register . if the timer is set to automatically restart, it will pr ovide a pulse, otherwise a level is provided. r/wc 0h tim- er_reset
MEC1322 ds00001719d-page 226 ? 2014 - 2015 microchip technology inc. 17.9.4 timer int enable register 17.9.5 timer control register offset 0ch bits description type default reset event 31:0 reserved r - - 0 event_interrupt_enable this is the interrupt enable for the status event_interrupt bit in the timer status register r/w 0h tim- er_reset offset 10h bits description type default reset event 31:16 pre_scale this is used to divide down the system clock through clock enables to lower the power consumption of the block and allow slow timers. updating this value during operation may result in erroneous clock enable pulses until the clock divider restarts. the number of clocks per clock enable pulse is (value + 1); a setting of 0 runs at the full clock speed, while a setting of 1 runs at half speed. r/w 0h tim- er_reset 15:8 reserved r - - 7halt this is a halt bit. this will halt the timer as long as it is active. once the halt is inactive, the timer will start from where it left off. 1=timer is halted. it stops counting. the clock divider will also be reset. 0=timer runs normally r/w 0h tim- er_reset 6reload this bit reloads the counter without interrupting it operation. this will not function if the timer has already completed (when the start bit in this register is ?0?). this is used to periodically prevent the timer from firing when an event occurs. usage while the timer is off may result in erroneous behavior. r/w 0h tim- er_reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 227 MEC1322 5start this bit triggers the timer counter. the counter will operate until it hits its terminating condition. this will clear this bit. it should be noted that when operating in restart mode, there is no terminating condition for the counter, so this bit will never clear. clearing this bit will halt the timer counter. setting this bit will: ? reset the clock divider counter. ? enable the clock divider counter. ? start the timer counter. ? clear all interrupts. clearing this bit will: ? disable the clock divider counter. ? stop the timer counter. r/w 0h tim- er_reset 4 soft_reset this is a soft reset. this is self clearing 1 cycle after it is written. wo 0h tim- er_reset 3 auto_restart this will select the action taken upon completing a count. 1=the counter will automatically restart the count, using the contents of the timer preload register to load the timer count register the interrupt will be set in edge mode 0=the counter will simply enter a done state and wait for further con- trol inputs. the interrupt will be set in level mode. r/w 0h tim- er_reset 2 count_up this selects the counter direction. when the counter in incrementing the counter will saturate and trig- ger the event when it reaches all f?s. when the counter is decre- menting the counter will saturate when it reaches 0h. 1=the counter will increment 0=the counter will decrement r/w 0h tim- er_reset 1 reserved r - - 0 enable this enables the block for operation. 1=this block will function normally 0=this block will gate its clock a nd go into its lowest power state r/w 0h tim- er_reset offset 10h bits description type default reset event
MEC1322 ds00001719d-page 228 ? 2014 - 2015 microchip technology inc. 18.0 hibernation timer 18.1 introduction the hibernation timer can generate a wake event to the em bedded controller (ec) when it is in a hibernation mode. this block supports wake events up to 2 hours in durati on. the timer is a 16-bit binary count-down timer that can be programmed in 30.5s and 0.125 second increments for period ranges of 30.5s to 2s or 0.125s to 136.5 minutes, respectively. writing a non-zero value to this register starts the counter from that value. a wake-up interrupt is generated when the count reaches zero. 18.2 references no references have been cited for this chapter 18.3 terminology no terms have been cited for this chapter. 18.4 interface this block is an ip block designed to be incorporated into a chip. it is designed to be accessed externally via the pin interface and internally via a registered host interface. the following diagram illustrates the various interfaces to the block. 18.5 signal description there are no external signals for this block. figure 18-1: hibernation timer interface diagram hibernation timer signal description clock inputs interrupts resets host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 229 MEC1322 18.6 host interface the registers defined for the hibernation timer are accessible by the various hosts as indicated in section 18.10, "ec- only registers" . 18.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 18.7.1 power domains 18.7.2 clock inputs 18.7.3 resets 18.8 interrupts this section defines the interrupt interface signals routed to the chip interrupt aggregator. each instance of the hibernation timer in the MEC1322 can be used to generate interrupts and wake-up events when the timer decrements to zero. the hibernation timer interrupt is are routed to the htimer bit in the girq17 source register . 18.9 low power modes the hibernation timer may be put into a low power state by the chip power, clocks, and reset (pcr) circuitry. the timer operates off of the 32khz_clk , and therefore will operate normally when 48 mhz ring oscillator is stopped. the sleep enable inputs have no effect on the hibernation timer and the clock required outputs are only asserted during register read/write cycles for as long as neces sary to propagate updat es to the block core. 18.10 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the hibernation timer. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. table 18-1: power sources name description vcc1 the timer control logic and registers are all implemented on this single power domain. table 18-2: clock inputs name description 32khz_clk this is the clock source to the time r logic. the pre-scaler may be used to adjust the minimum resolution per bit of the counter. if the main oscillator is stopped then an external 32.768khz clock source must be active for the hibernation timer to continue to operate. table 18-3: reset signals name description vcc1_reset this reset signal, which is an input to this block, resets all the logic and registers to their initial default state. table 18-4: interrupt interface signal description table name direction description htimer output signal indicating that the timer is enabled and decrements to 0. this signal is used to generate an hibernation timer interrupt event.
MEC1322 ds00001719d-page 230 ? 2014 - 2015 microchip technology inc. the base address indicates where the first register can be accessed in a particular address space for a block instance. 18.10.1 htimer preload register 18.10.2 htimer control register 18.10.3 htimer count register table 18-5: ec-only register base address table block instance instance number host address space base address hibernation timer 0 ec 32-bit internal address space 4000_9800h table 18-6: hibernation timer summary offset register name 00h htimer preload register 04h htimer control register 08h htimer count register offset 00h bits description type default reset event 15:0 ht_preload this register is used to set the hibernation timer preload value. writing this register to a non-zero value resets the down counter to start counting down from this programmed value. writing this regis- ter to 0000h disables the hibernation counter. the resolution of this timer is determined by the ctrl bit in the htimer control register . writes to the htimer control register are completed with an ec bus cycle. r/w 000h vcc1_r eset offset 04h bits description type default reset event 15:1 reserved r - - 0ctrl 1= the hibernation timer has a resolution of 0.125s per lsb, which yields a maximum time in excess of 2 hours. 0= the hibernation timer has a resolution of 30.5s per lsb, which yields a maximum time of ~2seconds. r 0000h vcc1_r eset offset 08h bits description type default reset event 15:0 count the current state of the hibernation timer. r 0000h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 231 MEC1322 19.0 rtc with date and dst adjustment 19.1 introduction this block provides the capabilities of an industry-standard 146818b real-time clock module, without cmos ram. enhancements to this architecture include: ? industry standard day of month alarm field, allowing for monthly alarms ? configurable, automatic daylight savings adjustment ? week alarm for periodic interrupts and wakes based on day of week ? system wake capability on interrupts. 19.2 references 1. motorola 146818b data sheet, available on-line 2. intel lynx point pch eds specification 19.3 terminology time and date registers: this is the set of registers that are automatically counted by hardware every 1 second while the block is enabled to run and to update. these registers are: seconds , minutes , hours , day of week , day of month , month , and year . 19.4 interface this block?s connections are entirely internal to the chip. figure 19-1: i/o diagram of block rtc with date and dst adjust- ment signal description clocks interrupts host interface resets
MEC1322 ds00001719d-page 232 ? 2014 - 2015 microchip technology inc. 19.5 signal description there are no external signals. 19.6 host interface the registers defined for the rtc with date and dst adjustment are accessible by the host and ec. 19.7 power, clocks and resets this section defines the power, clock, and reset parameters of the block. 19.7.1 power domains 19.7.2 clocks 19.7.3 resets 19.8 interrupts table 19-1: power sources name description vbat this power well sources all of the internal registers and logic in this block. vcc1 this power well sources only bus communication. the block continues to operate internally while this rail is down. table 19-2: clocks name description 32khz_clk this 32khz clock input drives all internal logic, and will be present at all times that the vbat well is powered. table 19-3: reset signals name description vbat_por this reset signal is used in the rtc_rst signal to reset all of the registers and logic in this block. it directly resets the soft reset bit in the rtc control register. rtc_rst this reset signal resets all of the registers and logic in this block, except for the soft reset bit in the rtc control register. it is triggered by vbat_por , but can also be triggered by a soft reset from the rtc control register. vcc1_reset this reset signal is used to inhibit the bus communication logic, and isolates this block from vcc1 powered circuitry on-chip. otherwise it has no effect on the internal state. table 19-4: system interrupts source description rtc this interrupt source for the sirq logic is generated when any of the fol- lowing events occur: ? update complete. this is triggered, at 1-second intervals, when the time register updates have completed ? alarm. this is triggered when the alarm value matches the current time (and date, if used) ? periodic. this is triggered at the chosen programmable rate
? 2014 - 2015 microchip technology inc. ds00001719d-page 233 MEC1322 19.9 low power modes the rtc has no low-power modes. it runs continuously while the vbat well is powered. 19.10 description this block provides the capabilities of an industry-s tandard 146818b real-time clock module, excluding the cmos ram and the sqw output. see the following registers, wh ich represent enhancements to this architecture. these enhancements are listed below. see the date alarm field of register d for a day of month qualifier for alarms. see the week alarm register for a day of week qualifier for alarms. see the registers daylight savings forward register and daylight savings backward register for setting up hands-off daylight savings adjustments. see the rtc control register for enhanced control over the block?s operations. 19.11 runtime registers the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in runtime register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. add the register?s offset to this value to obtain the direct address of the register. table 19-5: ec interrupts source description rtc this interrupt is signaled to the interrupt aggregator when any of the fol- lowing events occur: ? update complete. this is triggered, at 1-second intervals, when the time register updates have completed ? alarm. this is triggered when the alarm value matches the current time (and date, if used) ? periodic. this is triggered at the chosen programmable rate rtc alarm this wake interrupt is signaled to the interrupt aggregator when an alarm event occurs. table 19-6: runtime register base address table block instance instance number host address space base address rtc 0 lpc i/o programmed bar 0 ec 32-bit internal address space 400f_2c00h table 19-7: runtime register summary offset register name (mnemonic) 00h seconds register 01h seconds alarm register 02h minutes register 03h minutes alarm register 04h hours register 05h hours alarm register 06h day of week register 07h day of month register 08h month register
MEC1322 ds00001719d-page 234 ? 2014 - 2015 microchip technology inc. 19.11.1 seconds register 19.11.2 seconds alarm register 09h year register 0ah register a 0bh register b 0ch register c 0dh register d 0eh (reserved) 0fh (reserved) 10h rtc control register 14h week alarm register 18h daylight savings forward register 1ch daylight savings backward register 20h mchp reserved note: this extended register set occupies offsets that have historically been used as cmos ram. code ported to use this block should be examined to ensure that it does not assume that ram exists in this block. offset 00h bits description type default reset event 7:0 seconds displays the number of seconds past the current minute, in the range 0--59. presentation may be selected as binary or bcd, depending on the dm bit in register b. values written must also use the format defined by the current setting of the dm bit. r/w 00h rtc_r st offset 01h bits description type default reset event 7:0 seconds_alarm holds a match value, compared against the seconds register to trig- ger the alarm event. values written to this register must use the for- mat defined by the current setting of the dm bit in register b. a value of 11xxxxxxb written to this regi ster makes it don?t-care (always matching). r/w 00h rtc_r st table 19-7: runtime register summary (continued) offset register name (mnemonic)
? 2014 - 2015 microchip technology inc. ds00001719d-page 235 MEC1322 19.11.3 minutes register 19.11.4 minutes alarm register 19.11.5 hours register offset 02h bits description type default reset event 7:0 minutes displays the number of minutes past the current hour, in the range 0- -59. presentation may be selected as binary or bcd, depending on the dm bit in register b. values written must also use the format defined by the current setting of the dm bit. r/w 00h rtc_rs t offset 03h bits description type default reset event 7:0 minutes_alarm holds a match value, compared against the minutes register to trig- ger the alarm event. values written to this register must use the for- mat defined by the current setting of the dm bit in register b. a value of 11xxxxxxb written to this regi ster makes it don?t-care (always matching). r/w 00h rtc_r st offset 04h bits description type default reset event 7 hours_am_pm in 12-hour mode (see bit ?24/12? in r egister b), this bit indicates am or pm. 1=pm 0=am r/w 0b rtc_r st 6:0 hours displays the number of the hour, in the range 1--12 for 12-hour mode (see bit ?24/12? in register b), or in the range 0--23 for 24-hour mode. presentation may be selected as binary or bcd, depending on the dm bit in register b. values written must also use the format defined by the current setting of the dm bit. r/w 00h rtc_r st
MEC1322 ds00001719d-page 236 ? 2014 - 2015 microchip technology inc. 19.11.6 hours alarm register 19.11.7 day of week register 19.11.8 day of month register 19.11.9 month register offset 05h bits description type default reset event 7:0 hours_alarm holds a match value, compared against the hours register to trigger the alarm event. values written to th is register must use the format defined by the current settings of the dm bit and the 24/12 bit in reg- ister b. a value of 11xxxxxxb written to this register makes it don?t- care (always matching). r/w 00h rtc_r st offset 06h bits description type default reset event 7:0 day_of_week displays the day of the week, in the range 1 (sunday) through 7 (sat- urday). numbers in this range ar e identical in both binary and bcd notation, so this register?s format is unaffected by the dm bit. r/w 00h rtc_r st offset 07h bits description type default reset event 7:0 day_of_month displays the day of the current month, in the range 1--31. presenta- tion may be selected as binary or bcd, depending on the dm bit in register b. values written must also use the format defined by the current setting of the dm bit. r/w 00h rtc_r st offset 08h bits description type default reset event 7:0 month displays the month, in the range 1--12. presentation may be selected as binary or bcd, depending on the dm bit in register b. values writ- ten must also use the format defined by the current setting of the dm bit. r/w 00h rtc_r st
? 2014 - 2015 microchip technology inc. ds00001719d-page 237 MEC1322 19.11.10 year register 19.11.11 register a offset 09h bits description type default reset event 7:0 year displays the number of the year in the current century, in the range 0 (year 2000) through 99 (year 2099) . presentation may be selected as binary or bcd, depending on the dm bit in register b. values written must also use the format defined by the current setting of the dm bit. r/w 00h rtc_r st offset 0ah bits description type default reset event 7 update_in_progress ?0? indicates that the time and date registers are stable and will not be altered by hardware soon. ?1? indicates that a hardware update of the time and date registers may be in progress, and those registers should not be accessed by the host program. this bit is set to ?1? at a point 488us (16 cycles of the 32k clock) before the update occurs, and is cleared immediately after the update. see also the update-ended interrupt, which provides more useful status. r0b rtc_r st 6:4 division_chain_select this field provides general control for the time and date register updating logic. 11xb=halt counting. the next time that 010b is written, updates will begin 500ms later. 010b=required setting for normal operation. it is also necessary to set the block enable bit in the rtc control register to ?1? for counting to begin 000b=reserved. this field should be initialized to another value before enabling the block in the rtc control register other values reserved r/w 000b rtc_r st 3:0 rate_select this field selects the rate of the periodic interrupt source. see table 19-8 r/w 0h rtc_r st table 19-8: register a field rs: periodic interrupt settings rs (hex) interr upt period 0 never triggered 1 3.90625 ms 2 7.8125 ms 3 122.070 us 4 244.141 us 5 488.281 us 6 976.5625 us
MEC1322 ds00001719d-page 238 ? 2014 - 2015 microchip technology inc. 19.11.12 register b 7 1.953125 ms 8 3.90625 ms 9 7.8125 ms a 15.625 ms b 31.25 ms c 62.5 ms d 125 ms e 250 ms f 500 ms offset 0bh bits description type default reset event 7 update_cycle_inhibit in its default state ?0?, this bit allows hardware updates to the time and date registers, which occur at 1-second intervals. a ?1? written to this field inhibits updates, allowing these registers to be cleanly writ- ten to different values. writing ?0? to this bit allows updates to con- tinue. r/w 0b rtc_r st 6 periodic_interrupt_enable 1=alows the periodic interrupt events to be propagated as interrupts 0=periodic events are not propagates as interrupts r/w 0b rtc_r st 5 alarm_interrupt_enable 1=alows the alarm interrupt events to be propagated as interrupts 0=alarm events are not propagates as interrupts r/w 0b rtc_r st 4 update_ended_interrupt_enable 1=alows the update ended interrupt events to be propagated as inter- rupts 0=update ended events are not propagates as interrupts r/w 0b rtc_r st 3reserved r - - 2data_mode 1=binary mode for dates and times 0=bcd mode for dates and times r/w 0b rtc_r st 1 hour_format_24_12 1=24-hour format for hours and hours alarm registers. 24-hour for- mat keeps the am/pm bit off, with value range 0--23 0=12-hour format for hours and hours alarm registers. 12-hour for- mat has an am/pm bit, and value range 1--12 r/w 0b rtc_r st table 19-8: register a field rs: period ic interrupt settings (continued) rs (hex) interrupt period
? 2014 - 2015 microchip technology inc. ds00001719d-page 239 MEC1322 19.11.13 register c 0 daylight_savings_enable 1=enables automatic hardware updating of the hour, using the regis- ters daylight savings forward and daylight savings backward to select the yearly date and hour for each update 0=automatic daylight savings updates disabled r/w 0b rtc_r st note: the data_mode and hour_format_24_12 bits affect only how values are presented as they are being read and how they are interpreted as they are being written. they do not affect the internal contents or interpretations of registers that have already been written, nor do they affect how those registers are represented or counted internally. this mode bits may be set and cleared dynamically, for whatever i/o data representation is desired by the host program. offset 0ch bits description type default reset event 7 interrupt_request_flag 1=any of bits[6:4] below is active after masking by their respective enable bits in register b. 0=no bits in this register are active this bit is automatically cleared by every read access to this register. rc 0b rtc_r st 6 periodic_interrupt_flag 1=a periodic interrupt event has occurred since the last time this reg- ister was read. this bit displays status regardless of the periodic interrupt enable bit in register b 0=a periodic interrupt event has not occurred this bit is automatically cleared by every read access to this register. rc 0b rtc_r st 5 alarm_flag 1=an alarm event has occurred since the last time this register was read. this bit displays status regardless of the alarm interrupt enable bit in register b. 0=an alarm event has not occurred this bit is automatically cleared by every read access to this register. rc 0b rtc_r st offset 0bh bits description type default reset event
MEC1322 ds00001719d-page 240 ? 2014 - 2015 microchip technology inc. 19.11.14 register d 19.11.15 rtc control register 4 update_ended_interrupt_flag 1=a time and date update has completed since the last time this reg- ister was read. this bit displays status regardless of the update- ended interrupt enable bit in register b. presentation of this sta- tus indicates that the time and date register s will be valid and sta- ble for over 999ms 0=a time and data update has not completed since the last time this register was read this bit is automatically cleared by every read access to this register. rc 0b rtc_r st 3:0 reserved r - - offset 0dh bits description type default reset event 7:6 reserved r - - 5:0 date_alarm this field, if set to a non-zero value, will inhibit the alarm interrupt unless this field matches the contents of the month register also. if this field contains 00h (default), it represents a don?t-care, allowing more frequent alarms. r/w 00h rtc_r st offset 10h bits description type default reset event 7:4 reserved r - - 3 alarm_enable 1=enables the alarm features 0=disables the alarm features r/w 0b rtc_r st 2 microchip reserved r/w 0b rtc_r st 1 soft_reset a ?1? written to this bit position will trigger the rtc_rst reset, reset- ting the block and all registers except this one and the test register. this bit is self-clearing at the end of the reset, one cycle of lpc bus clock later, and so requires no waiting. r/w 0b vbat_ por 0 block_enable this bit must be ?1? in order for the block to function internally. regis- ters may be initialized first, before setting this bit to ?1? to start opera- tion. r/w 0b rtc_r st offset 0ch bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 241 MEC1322 19.11.16 week alarm register 19.11.17 daylight savings forward register this is a 32-bit register, accessible also as individual bytes. when writing as individual bytes, ensure that the dse bit (in register b) is off first, or that the block is disabled or stopped (set bit), to prevent a time update while this register may have incomplete ly-updated contents. when enabled by the dse bit in register b, this register defin es an hour and day of the ye ar at which the hours register will be automatically incremented by 1 additional hour. there are no don?t-care fields recognized. all fields must be already initialized to valid settings whenever the dse bit is ?1?. fields other than week and day of week use the current setting of the dm bit (binary vs. bcd) to interpret the informa- tion as it is written to them. their values, as held inter nally, are not changed by later changes to the dm bit, without subsequently writing to this register as well. offset 14h bits description type default reset event 7:0 alarm_day_of_week this register, if written to a value in the range 1--7, will inhibit the alarm interrupt unless this field matches the contents of the day of week register also. if this field is written to any value 11xxxxxxb (like the default ffh), it represents a don?t-care, allowing more frequent alarms, and will read back as ffh until another value is written. r/w ffh rtc_r st offset 18h bits description type default reset event 31 dst_forward_am_pm this bit selects am vs. pm, to match bit[7] of the hours register if 12- hour mode is selected in register b at the time of writing. r/w 0b rtc_r st 30:24 dst_forward_hour this field holds the matching value for bits[6:0] of the hours register. the written value will be interpreted according to the 24/12 hour mode and dm mode settings at the time of writing. r/w 00h rtc_r st 23:19 reserved r - - 18:16 dst_forward_week this value matches an internally-maintained week number within the current month. valid values for this field are: 5=last week of month 4 =fourth week of month 3=third week of month 2=second week of month 1=first week of month r/w 0h rtc_r st 15:11 reserved r - - 10:8 dst_forward_day_of_week this field matches the day of week register bits[2:0]. r/w 0h rtc_r st 7:0 dst_forward_month this field matches the month register. r/w 00h rtc_r st
MEC1322 ds00001719d-page 242 ? 2014 - 2015 microchip technology inc. 19.11.18 daylight savin gs backward register this is a 32-bit register, accessible also as individual bytes. when writing as individual bytes, ensure that the dse bit (in register b) is off first, or that the block is disabled or stopped (set bit), to prevent a time update while this register may have incomplete ly-updated contents. when enabled by the dse bit in register b, this register defin es an hour and day of the ye ar at which the hours register increment will be inhibited from occurring. after triggering, this feature is automatically disabled for long enough to ensure that it will not retrigger the second time this ho urs value appears, and then this feature is re-enabled automati- cally. there are no don?t-care fields recognized. all fields must be already initialized to valid settings whenever the dse bit is ?1?. fields other than week and day of week use the current setting of the dm bit (binary vs. bcd) to interpret the informa- tion as it is written to them. their values, as held inter nally, are not changed by later changes to the dm bit, without subsequently writing to this register as well. note: an alarm that is set inside the hour after the time spec ified in this register will not be triggered, because that one-hour period is skipped. this period includes the exact time (0 minutes: 0 seconds) given by this register, through the 59 minutes: 59 seconds point afterward. offset 1ch bits description type default reset event 31 dst_backward_am_pm this bit selects am vs. pm, to match bit[7] of the hours register if 12- hour mode is selected in register b at the time of writing. r/w 0b rtc_r st 30:24 dst_bac kward_hour this field holds the matching value for bits[6:0] of the hours register. the written value will be interpreted according to the 24/12 hour mode and dm mode settings at the time of writing. r/w 00h rtc_r st 23:19 reserved r - - 18:16 dst_backward_week this value matches an internally-maintained week number within the current month. valid values for this field are: 5=last week of month 4 =fourth week of month 3=third week of month 2=second week of month 1=first week of month r/w 0h rtc_r st 15:11 reserved r - - 10:8 dst_backward_day_of_week this field matches the day of week register bits[2:0]. r/w 0h rtc_r st 7:0 dst_backward_month this field matches the month register. r/w 00h rtc_r st note: an alarm that is set inside the hour before the time spec ified in this register will be triggered twice, because that one-hour period is repeated. this period will include the exact time (0 minutes: 0 seconds) given by this register, through the 59 minutes: 59 seconds point afterward.
? 2014 - 2015 microchip technology inc. ds00001719d-page 243 MEC1322 20.0 gpio interface 20.1 general description the MEC1322 gpio interface provides general purpose input monitoring and output control, as well as managing many aspects of pin functionality; including, multi-function pin multiplexing control, gpio direction control, pu/pd (pu_pd) resistors, asynchronous wakeup and synchronous interrupt detection (int_det) , gpio direction , and polarity control, as well as control of pin drive strength and slew rate. features of the gpio interface include: ? inputs: - asynchronous rising and falling edge wakeup detection - interrupt high or low level ? on output: - push pull or open drain output ? pull up or pull down resistor control ? interrupt and wake capability available for all gpios ? programmable pin drive strength and slew rate limiting ? group- or individual control of gpio data. ? multiplexing of all multi-function pins are controlled by the gpio interface 20.2 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 20.2.1 power domains 20.2.2 clock inputs 20.2.3 resets table 20-1: power sources name description vcc1 the registers and logic in this block are powered by vcc1 . table 20-2: clock inputs name description 48 mhz ring oscillator the 48 mhz ring oscillator is used for synchronizing the gpio inputs. table 20-3: reset signals name description vcc1_reset this reset is asserted when vcc1 is applied. nsio_reset this is an alternate reset condition, typically asserted when the main power rail is asserted. this reset is used for vcc power well emulation.
MEC1322 ds00001719d-page 244 ? 2014 - 2015 microchip technology inc. 20.3 interrupts this section defines the interrupt sources generated from this block. 20.4 accessing gpios there are two ways to access gpio output data. bit [10] is used to determine which gpio output data bit affects the gpio output pin. ? output gpio data - outputs to individual gpio ports are grouped into 32-bit gpio output registers . ? alternative gpio data - alternatively, each gpio output port is indivi dually accessible via bit [16] in the port?s pin control register . on reads, bit [16] returns the programmed value, not the value on the pin. there are two ways to access gpio input data. ? input gpio data - inputs from individual gpio ports are grouped into 32-bit gpio input registers and always reflect the current state of the gpio input from the pad. ? gpio input from pad - alternatively, each gpio input port is indivi dually accessible via bit [24] in the port?s pin control register . bit [24] always reflects the current state of gpio input from the pad. 20.5 gpio indexing each gpio signal function name consists of a 4-characte r prefix (?gpio?) followed by a 3-digit octal-encoded index number. in the MEC1322 gpio indexing is done sequentially starting from ?gpio000.? 20.6 gpio multiplexing control pin multiplexing depends upon the mux control bits in the pin control register. there are two pin control registers for each gpio signal function. the MEC1322 pin control register address offsets shown in the following tables depends on the gpio index number. pin control register defaults are also shown in these tables. note 1: pin control register 2 default values are not shown in these tables. 2: the gpio143/rsmrst# pin operates as described in section 1.6, "notes for tables in this chapter," on page 39 when it is configured as a gpio; the rsmrst# func tion is not a true alternate function. for proper rsmrst# operation on the pin, the gpio143 control register must not be changed from the gpio default function. 3: the vcc1_rst#/gpio131 pin cannot be used as a gpio pin. the input path to the vcc1_rst# logic is always active and will cause a reset if this pin is set low in gpio mode. 4: the ksi[7:0] pins have the internal pullups enabled by rom boot code. therefore the pin control reg. por value is as follows after the rom boot code runs: gpio043 = 00003001h gpio042 = 00003001h table 20-4: interrupts source description gpio_event each pin in the gpio interface has the ability to generate an interrupt event. this event may be used as a wake event. the gpio interface can generate an interrupt source event on a high level, low level, rising edge and falling edge, as configured by the inter- rupt detection (int_det) bits in the pin control register associated with the gpio signal function. note: the minimum pulse width ensured to generate an inter- rupt/wakeup event is 5ns.
? 2014 - 2015 microchip technology inc. ds00001719d-page 245 MEC1322 gpio040 = 00003001h gpio142 = 00003001h gpio032 = 00003001h gpio144 = 00003001h gpio126 = 00002001h gpio125 = 00002001h table 20-5: pin control registers gpio na me (octal) pin control re g. offse t (hex) pin control reg. por value (hex) por default signal function mux control = 00 mux control = 01 mux control = 10 mux control = 11 gpio000 0000 00003000 kso00 gpio000 reserved reserved kso00 gpio001 0004 00003000 kso06 gpio001 reserved reserved kso06 gpio002 0008 00003000 kso07 gpio002 reserved reserved kso07 gpio003 000c 00003000 kso08 gpio003 reserved reserved kso08 gpio004 0010 00003000 kso10 gpio004 reserved reserved kso10 gpio005 0014 00003002 kso12 gpio005 reserved reserved kso12 gpio006 0018 00003000 kso13 gpio006 reserved reserved kso13 gpio007 001c 00000000 gpio007 gpio007 reserved reserved kso14 gpio010 0020 00000000 gpio010 gpio010 reserved reserved kso15 gpio011 0024 00000002 gpio011 gpio011 reserved reserved kso16 gpio012 0028 00000000 gpio012 gpio012 reserved reserved kso17 gpio013 002c 00002000 32khz_out gpio013 reserved 32khz_out reserved gpio014 0030 00001000 clkrun# gpio014 clkrun# reserved reserved gpio015 0034 00002100 i2c0_clk0 gpio015 reserved i2c0_clk0 reserved gpio016 0038 00002100 i2c0_dat0 gpio016 reserved i2c0_dat0 reserved gpio017 003c 00002100 i2c0_dat1 gpio017 reserved i2c0_dat1 reserved gpio020 0040 00000000 gpio020 gpio020 reserved i2c2_clk0 reserved gpio021 0044 00000000 gpio021 gpio021 reserved i2c2_dat0 reserved gpio022 0048 00000000 gpio022 gpio022 reserved i2c1_clk0 reserved gpio023 004c 00000000 gpio023 gpio023 reserved i2c1_dat0 reserved gpio024 0050 00000001 gpio024 gpio024 reserved i2c3_clk0 reserved gpio025 0054 00000000 gpio025 gpio025 reserved i2c3_dat0 reserved gpio026 0058 00002100 nec_sci gpio026 reserved nec_sci reserved gpio027 005c 00000001 gpio027 gpio027 reserved reserved reserved gpio030 0060 00000000 gpio030 gpio030 reserved reserved reserved gpio031 0064 00000001 gpio031 gpio031 reserved reserved reserved gpio032 0068 00003000 ksi3 gpio032 reserved reserved ksi3 gpio033 006c 00000001 gpio033 gpio033 reserved reserved reserved gpio034 0070 00000000 gpio034 gpio034 pwm2 reserved tach2pwm_out gpio035 0074 00000001 gpio035 gpio035 reserved reserved reserved gpio036 0078 00000001 gpio036 gpio036 reserved reserved reserved gpio040 0080 00003000 ksi5 gpio040 reserved reserved ksi5
MEC1322 ds00001719d-page 246 ? 2014 - 2015 microchip technology inc. gpio na me (octal) pin control re g. offse t (hex) pin control reg. por value (hex) por default signal function mux control = 00 mux control = 01 mux control = 10 mux control = 11 gpio041 0084 00001002 reserved gpio041 reserved reserved reserved gpio042 0088 00003000 ksi6 gpio042 reserved reserved ksi6 gpio043 008c 00003000 ksi7 gpio043 reserved reserved ksi7 gpio044 0090 00000000 gpio044 gpio044 nsmi reserved reserved gpio045 0094 00000000 gpio045 gpio045 a20m pvt_cs1# reserved gpio046 0098 00002100 ps2_clk0 gpio046 reserved ps2_clk0 reserved gpio047 009c 00002100 ps2_dat0 gpio047 reserved ps2_dat0 reserved gpio050 00a0 00002100 ps2_clk1 gpio050 reserved ps2_clk1 reserved gpio051 00a4 00002100 ps2_clk2 gpio051 reserved ps2_clk2 reserved gpio052 00a8 00002100 ps2_dat2 gpio052 reserved ps2_dat2 reserved gpio053 00ac 00000000 gpio053 gpio053 reserved ps2_clk3 reserved gpio054 00b0 00000000 gpio054 gpio054 pvt_mosi reserved reserved gpio055 00b4 0000000c gpio055 gpio055 reserved reserved reserved gpio056 00b8 00003000 adc0 gpio056 adc0 reserved reserved gpio057 00bc 00001000 adc1 gpio057 adc1 reserved reserved gpio060 00c0 00001001 adc2 gpio060 adc2 reserved reserved gpio061 00c4 00001000 adc3 gpio061 adc3 reserved reserved gpio062 00c8 00001000 adc4 gpio062 adc4 reserved reserved gpio063 00cc 00001000 vcc_pwrgd gpio063 vcc_pwrgd reserved reserved gpio064 00d0 00000000 gpio064 gpio064 shd_mosi reserved reserved gpio065 00d4 00002100 ps2_dat1 gpio065 reserved ps2_dat1 reserved gpio066 00d8 00000000 gpio066 gpio066 reserved reserved reserved gpio067 00dc 0000000c gpio067 gpio067 reserved reserved reserved gpio100 0100 00003000 kso01 gpio100 reserved reserved kso01 gpio101 0104 00003000 kso02 gpio101 reserved reserved kso02 gpio102 0108 00003000 kso03 gpio102 reserved reserved kso03 gpio103 010c 00003000 kso04 gpio103 tfdp_data reserved kso04 gpio104 0110 00003000 kso05 gpio104 tfdp_clk reserved kso05 gpio105 0114 00000000 gpio105 gpio105 tach1 reserved reserved gpio106 0118 00003000 kso09 gpio106 reserved reserved kso09 gpio107 011c 00003000 kso11 gpio107 reserved reserved kso11 gpio110 0120 00000000 gpio110 gpio110 reserved reserved reserved
? 2014 - 2015 microchip technology inc. ds00001719d-page 247 MEC1322 gpio na me (octal) pin control re g. offse t (hex) pin control reg. por value (hex) por default signal function mux control = 00 mux control = 01 mux control = 10 mux control = 11 gpio111 0124 00001000 lad3 gpio111 lad3 reserved reserved gpio112 0128 00001000 lad0 gpio112 lad0 reserved reserved gpio113 012c 00001000 lad2 gpio113 lad2 reserved reserved gpio114 0130 00001000 lad1 gpio114 lad1 reserved reserved gpio115 0134 00001000 ser_irq gpio115 ser_irq reserved reserved gpio116 0138 00001000 lreset# gpio116 lreset# reserved reserved gpio117 013c 00001000 pci_clk gpio117 pci_clk reserved reserved gpio120 0140 00001000 lframe# gpio120 lframe# reserved reserved gpio121 0144 00001000 nreset_out gpio121 nreset_out reserved reserved gpio122 0148 00000000 gpio122 gpio122 shd_sclk reserved reserved gpio123 014c 0000000c gpio123 gpio123 reserved reserved reserved gpio124 0150 00000000 gpio124 gpio124 shd_miso reserved reserved gpio125 0154 00002000 ksi0 gpio125 reserved ksi0 reserved gpio126 0158 00002000 ksi1 gpio126 reserved ksi1 reserved gpio127 015c 00000000 gpio127 gpio127 peci_rdy reserved reserved gpio130 0160 00000000 gpio130 gpio130 reserved reserved reserved gpio131 0164 00001100 vcc1_rst# gpio131 vcc1_rst# reserved reserved gpio132 0168 00000000 gpio132 gpio132 peci_dat reserved reserved gpio133 016c 00000000 gpio133 gpio133 pwm0 reserved reserved gpio134 0170 00002100 i2c0_clk1 gpio134 reserved i2c0_clk1 reserved gpio135 0174 00000000 gpio135 gpio135 kbrst reserved reserved gpio136 0178 00000000 gpio136 gpio136 pwm1 reserved reserved gpio140 0180 00000000 gpio140 gpio140 tach2 reserved tach2pwm_in gpio141 0184 00000000 gpio141 gpio141 pwm3 led3 reserved gpio142 0188 00003000 ksi4 gpio142 reserved reserved ksi4 gpio143 018c 00000200 gpio143 gpio143 rsmrst# reserved reserved gpio144 0190 00003000 ksi2 gpio144 reserved reserved ksi2 gpio145 0194 00000001 gpio145 gpio145 reserved reserved reserved gpio146 0198 00000000 gpio146 gpio146 pvt_cs0# reserved reserved gpio147 019c 00000001 gpio147 gpio147 reserved reserved reserved gpio150 01a0 00000000 gpio150 gpio150 shd_cs0# reserved reserved gpio151 01a4 00000001 gpio151 gpio151 reserved reserved reserved gpio na me (octal) pin control re g. offse t (hex) pin control reg. por value (hex) por default signal function mux control = 00 mux control = 01 mux control = 10 mux control = 11 gpio152 01a8 00000000 gpio152 gpio152 reserved ps2_dat3 reserved gpio153 01ac 00000000 gpio153 gpio153 pvt_sclk reserved reserved gpio154 01b0 00002000 led0 gpio154 reserved led0 reserved gpio155 01b4 00002000 led1 gpio155 reserved led1 reserved gpio156 01b8 00002000 led2 gpio156 reserved led2 reserved gpio157 01bc 00000001 gpio157 gpio157 bc_clk reserved reserved gpio160 01c0 00000001 gpio160 gpio160 bc_dat reserved reserved gpio161 01c4 00000001 gpio161 gpio161 bc_int# reserved reserved gpio162 01c8 00000000 gpio162 gpio162 rxd reserved reserved gpio163 01cc 00000000 gpio163 gpio163 reserved reserved reserved gpio164 01d0 00000000 gpio164 gpio164 pvt_miso reserved reserved gpio165 01d4 00000000 gpio165 gpio165 txd shd_cs1# reserved gpio200 0200 0000000c gpio200 gpio200 reserved reserved reserved gpio201 0204 0000000c gpio201 gpio201 reserved reserved reserved gpio202 0208 0000000c gpio202 gpio202 reserved reserved reserved gpio203 020c 0000000c gpio203 gpio203 reserved reserved reserved gpio204 0210 0000000c gpio204 gpio204 reserved reserved reserved gpio206 0218 00000000 gpio206 gpio206 reserved reserved reserved gpio210 0220 0000000c gpio210 gpio210 reserved reserved reserved gpio211 0224 0000000c gpio211 gpio211 reserved reserved reserved
MEC1322 ds00001719d-page 248 ? 2014 - 2015 microchip technology inc. note 1: the value of the pin control register 2 for each pin is not shown in the tables above. the default value can be determined by the current value shown in the ?default operation? column of the multiplexing tables in section 1.5.2, "multiplexing tables," on page 20 as follows: 2ma: 00000000h 4ma: 00000010h 8ma: 00000020h 12ma: 00000030h 2: the default slew rate is slow. 3: the gpio041 pin defaults to output low. this pin must be reprogrammed to the gpio function upon power- up. 20.7 pin multiplexing control pin multiplexing depends upon the mux control bits in the pin control register . there is a pin control register for each gpio signal function. table 20-5: shows default of the register for each gpio pin. the registers listed in the register summary table are for a single instance of the MEC1322. the addresses of each register listed in this table are defined as a relative of fset to the host ?base address? defined in the register base address table. note 20-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. note 20-2 the gpio registers may be accessed by the lpc host via the emi block via gpio commands or by direct access if enabled by firmware. see the firmware documentation for a description of this access method. table 20-6: register base address table instance name instance number host address space base address ( note 20-1 ) gpio 0 lpc i/o note 20-2 0 ec 32-bit internal address space 4008_1000h table 20-7: register summary offset register name 000h - 01ch gpio000-gpio007 pin control register 020h - 03ch gpio010-gpio017 pin control register 040h - 05ch gpio020-gpio027 pin control register 060h - 078h gpio030-gpio036 pin control register 080h - 09ch gpio040-gpio047 pin control register 0a0h - 0bch gpio050-gpio057 pin control register 0c0h - 0dch gpio060-gpio067 pin control register 100h - 11ch gpio100-gpio107 pin control register 120h - 13ch gpio110-gpio117 pin control register 140h - 15ch gpio120-gpio127 pin control register 160h - 178h gpio130-gpio136 pin control register 180h - 19ch gpio140-gpio147 pin control register 1a0h - 1bch gpio150-gpio157 pin control register 1c0h - 1d4h gpio160-gpio165 pin control register 200h - 210h gpio200-gpio204 pin control register 218h gpio206 pin control register 220h - 224h gpio210-gpio211 pin control register 280h ( note 20-3 ) output gpio[000:036]
? 2014 - 2015 microchip technology inc. ds00001719d-page 249 MEC1322 note 20-3 the gpio input and output registers are lpc i/o accessible via region 0 of the emi block. this access is defined in the emi protocols chapter of the firmware specification. note 20-4 there is no pin control register 2 for gpio111-gpio117 and gpio120, which are pci_pio buffer type pins. the drive strength and slew rate are not configurable on these pins. 284h ( note 20-3 ) output gpio[040:076] 288h ( note 20-3 ) output gpio[100:127] 28ch ( note 20-3 ) output gpio[140:176] 290h ( note 20-3 ) output gpio[200:236] 300h ( note 20-3 ) input gpio[000:036] 304h ( note 20-3 ) input gpio[040:076] 308h ( note 20-3 ) input gpio[100:127] 30ch ( note 20-3 ) input gpio[140:176] 310h ( note 20-3 ) input gpio[200:236] 500h - 51ch gpio000-gpio007 pin control register 2 520h - 53ch gpio010-gpio017 pin control register 2 540h - 55ch gpio020-gpio027 pin control register 2 560h - 578h gpio030-gpio036 pin control register 2 580h - 59ch gpio040-gpio047 pin control register 2 5a0h - 5bch gpio050-gpio057 pin control register 2 5c0h - 5dch gpio060-gpio067 pin control register 2 5e0h - 5fch gpio100-gpio107 pin control register 2 600h gpio110 pin control register 2 604h - 623h mchp reserved ( note 20-4 ) 624h - 63ch gpio121-gpio127 pin control register 2 640h - 658h gpio130-gpio136 pin control register 2 660h - 67ch gpio140-gpio147 pin control register 2 680h - 69ch gpio150-gpio157 pin control register 2 6a0h - 6b4h gpio160-gpio165 pin control register 2 720h - 730h gpio200-gpio204 pin control register 2 738h gpio206 pin control register 2 740h - 744h gpio210-gpio211 pin control register 2 table 20-7: register summary (continued) offset register name
MEC1322 ds00001719d-page 250 ? 2014 - 2015 microchip technology inc. 20.8 pin control registers two pin control registers are implemented for each gpio. the pin control register format is described in section 20.8.1, "pin control register," on page 250 . the pin control register 2 format is described in section 20.8.2, "pin control register 2," on page 253 . pin control register address offsets and defaults are defined in table 20-5, ?pin control registers,? on page 245 . 20.8.1 pin control register note: the following gpios that do not exist in the 128-pin package are configured as inputs and grounded in the package. firmware should not attempt to turn those gpios into outputs and drive them high, or excessive current will be consumed. ? gpio067 ? gpio055 ? gpio210 ? gpio200 ? gpio202 ? gpio201 ? gpio203 ? gpio204 the following gpios that do not exist in the 128-pin package are not connected (nc) in the package. these gpios should be configured as inputs and the internal pull-down should be enabled. ? gpio211 ? gpio123 offset see note 20-5 bits description type default reset event 31:25 reserved res - - 24 gpio input from pad on reads, bit [24] reflects the state of gpio input from the pad regardless of setting of bit [10]. note: this bit is forced high when the selected power well is off as selected by the power gating signal bits. see bits[3:2]. r note 20-5 vcc1_r eset 23:17 reserved res - - 16 alternative gpio data if enabled by the output gpio write enable bit, the alternative gpio data bit determines the level on the gpio pin when the pin is config- ured for the gpio output function. on writes: if enabled via the output gpio write enable 0: gpio[x] out = ?0? 1: gpio[x] out = ?1? note: if disabled via the output gpio write enable then the gpio[x] out pin is unaffected by writing this bit. on reads: bit [16] returns the last programmed value, not the value on the pin. r/w note 20-5 vcc1_r eset 15:14 reserved res - -
? 2014 - 2015 microchip technology inc. ds00001719d-page 251 MEC1322 13:12 mux control the mux control field determines the active signal function for a pin. 00 = gpio function selected 01 = signal function 1 selected 10 = signal function 2 selected 11 = signal function 3 selected r/w note 20-5 vcc1_r eset 11 polarity 0 = non-inverted 1 = inverted when the polarity bit is set to ?1? and the mux control bits are greater than ?00,? the selected signal function outputs are inverted and inter- rupt detection (int_det) sense defined in table 20-8, "edge enable and interrupt detection bits definition" is inverted. when the mux control field selects the gpio signal function (mux = ?00?), the polar- ity bit does not effect the output. regardless of the state of the mux control field and the polarity bit, the state of the pin is always reported without inversion in the gpio input register. r/w note 20-5 vcc1_r eset 10 output gpio write enable every gpio has two mechanisms to set a gpio data output: output gpio bit located in the gpio output registers and the alternative gpio data bit located in bit 16 of this register. this control bit determines the source of the gpio output. 0 = alternative gpio data write enabled when this bit is zero the alternative gpio data write is enabled and the output gpio is disabled. 1 = output gpio enable when this bit is one the alternative gpio data write is disabled and the output gpio is enabled. note: see description in section 20.4, "accessing gpios" . r/w note 20-5 vcc1_r eset 9gpio direction 0 = input 1 = output the gpio direction bit controls the buffer direction only when the mux control field is ?00? selecting the pin signal function to be gpio. when the mux control field is greater than ?00? (i.e., a non- gpio signal function is selected) the gpio direction bit has no affect and the selected signal function logic directly controls the pin direc- tion. r/w note 20-5 vcc1_r eset offset see note 20-5 bits description type default reset event
MEC1322 ds00001719d-page 252 ? 2014 - 2015 microchip technology inc. note 20-5 see section 20.7, "pin multiplexing control," on page 248 for the offset and default values for each gpio pin control register. note 20-6 the pin control registers for gpio111-gpio117 and gpio120, which are pci_pio buffer type pins, do not have an internal pull-down. this configuration option has no effect on the pin. 8 output buffer type 0 = push-pull 1 = open drain note: unless explicitly stated otherwise, pins with (i/o/od) or (o/od) in their buffer type column in the tables in are compliant with the following programmable od/pp multi- plexing design rule: each compliant pin has a program- mable open drain/push-pull buffer controlled by the output buffer type bit in the associated pin control register . the state of this bit controls the mode of the interface buffer for all selected functions, including the gpio function. r/w note 20-5 vcc1_r eset 7 edge enable (edge_en) 0 = edge detection disabled 1 = edge detection enabled note: see table 20-8, "edge enable and interrupt detection bits definition" . r/w note 20-5 vcc1_r eset 6:4 interrupt detection (int_det) the interrupt detection bits determine the event that generates a gpio_event . note: see table 20-8, "edge enable and interrupt detection bits definition" . r/w note 20-5 vcc1_r eset 3:2 power gating signals the power gating signals provide the gpio pin power emulation options. the pin will be tristated when the sele cted power well is off (i.e., gated) as indicated. the emulated power well column defined in the multiplexing tables in section 1.5, "pin multiplexing," on page 19 indicates the emulation options supported for each signal. the signal power well column defines the actual buffer power supply per function. 00 = vcc1 power rail the output buffer is tristated when vcc1gd = 0. 01 = vcc2 power rail the output buffer is tristated when pwrgd = 0. 10 = reserved 11 = reserved r/w note 20-5 vcc1_r eset 1:0 pu/pd (pu_pd) these bits are used to ena ble an internal pull-up. 00 = none 01 = pull up enabled 10 = pull down enabled ( note 20-6 ) 11 = none r/w note 20-5 vcc1_r eset offset see note 20-5 bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 253 MEC1322 application note: all gpio interrupt detection configurations de fault to '0000', which is low level interrupt. having interrupt detection enabled will un-gated the clock to the gpio module whenever the interrupt is active, which increases power consumption. interrupt detection should be disabled when not required to save power; this is especially true for pin interfaces (i.e., lpc). 20.8.2 pin control register 2 20.8.3 gpio output registers if enabled by the output gpio write enable bit, the gpio output bits determine the level on the gpio pin when the pin is configured for the gpio output function. on writes: if enabled via the output gpio write enable 0: gpio[x] out = ?0? 1: gpio[x] out = ?1? if disabled via the output gpio write enable then the gpio[x] out pin is unaffected by writing this bit. table 20-8: edge enable and interrupt detection bits definition edge enable interrupt detection bits selected function d7 d6 d5 d4 0000low level sensitive 0001high level sensitive 0010reserved 0011reserved 0100interrupt events are disabled 0101reserved 0110reserved 0111reserved 1101rising edge triggered 1110falling edge triggered 1111either edge triggered note: only edge triggered interrupts can wake up the main ring oscillator. the gpio must be enabled for edge- triggered interrupts and the gpio interrupt must be enabl ed in the interrupt aggregator in order to wake up the ring when the ring is shut down. offset see note 20-5 bits description type default reset event 31:6 reserved res - - 5:4 drive strength these bits are used to select the drive strength on the pin. 00 = 2ma 01 = 4ma 10 = 8ma 11 = 12ma r/w note 1: on page 248 vcc1_r eset 3:1 reserved res - - 0 slew rate this bit is used to select the slew rate on the pin. 0 = slow (half frequency) 1 = fast r/w 0 vcc1_r eset
MEC1322 ds00001719d-page 254 ? 2014 - 2015 microchip technology inc. on reads: bit [16] returns the last programmed value, not the value on the pin. 20.8.3.1 output gpio[000:036] 20.8.3.2 output gpio[040:076] 20.8.3.3 output gpio[100:127] note: bits associated with gpios that are not implemented are shown as reserved. offset 280h ( note 20-3 ) bits description type default reset event 31 reserved res - - 30:24 gpio[036:030] output r/w 00h vcc1_r eset 23:16 gpio[027:020] output r/w 00h vcc1_r eset 15:8 gpio[017:010] output r/w 00h vcc1_r eset 7:0 gpio[007:000] output r/w 00h vcc1_r eset offset 284h ( note 20-3 ) bits description type default reset event 31:24 reserved res - - 23:16 gpio[067:060] output r/w 00h vcc1_r eset 15:8 gpio[057:050] output r/w 00h vcc1_r eset 7:0 gpio[047:040] output r/w 00h vcc1_r eset offset 288h ( note 20-3 ) bits description type default reset event 31 reserved res - - 30:24 gpio[136:130] output r/w 00h vcc1_r eset 23:16 gpio[127:120] output r/w 00h vcc1_r eset 15:8 gpio[117:110] output r/w 00h vcc1_r eset 7:0 gpio[107:100] output r/w 00h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 255 MEC1322 20.8.3.4 output gpio[140:176] 20.8.3.5 output gpio[200:236] 20.8.4 gpio input registers the gpio input registers can always be used to read the state of a pin, even when the pin is in an output mode and/or when a signal function other than the gpio signal function is selected; i.e., the pin control register mux control bits are not equal to ?00.? the msbit of the input gpio registers have been implemented as a read/write scratch pad bit to support processor spe- cific instructions. offset 28ch ( note 20-3 ) bits description type default reset event 31:22 reserved res - - 21:16 gpio[165:160] output r/w 00h vcc1_r eset 15:8 gpio[157:150] output r/w 00h vcc1_r eset 7:0 gpio[147:140] output r/w 00h vcc1_r eset offset 290h ( note 20-3 ) bits description type default reset event 31 reserved res - - 30:24 reserved res - - 23:12 reserved res - - 11:10 mchp reserved r/w 00h vcc1_r eset 9:8 gpio[211:210] output r/w 00h vcc1_r eset 7 reserved res - - 6 gpio206 output r/w 00h vcc1_r eset 5 reserved res - - 4:0 gpio[204:200] output r/w 00h vcc1_r eset note: bits associated with gpios that are not implemented are shown as reserved.
MEC1322 ds00001719d-page 256 ? 2014 - 2015 microchip technology inc. 20.8.4.1 input gpio[000:036] 20.8.4.2 input gpio[040:076] 20.8.4.3 input gpio[100:127] offset 300h ( note 20-3 ) bits description type default reset event 31 scratchpad bit r/w 0b vcc1_r eset 30:24 gpio[036:030] input r 00h vcc1_r eset 23:16 gpio[027:020] input r 00h vcc1_r eset 15:8 gpio[017:010] input r 00h vcc1_r eset 7:0 gpio[007:000] input r 00h vcc1_r eset offset 304h ( note 20-3 ) bits description type default reset event 31 scratchpad bit r/w 0b vcc1_r eset 30:24 reserved r - - 23:16 gpio[067:060] input r 00h vcc1_r eset 15:8 gpio[057:050] input r 00h vcc1_r eset 7:0 gpio[047:040] input r 00h vcc1_r eset offset 308h ( note 20-3 ) bits description type default reset event 31 scratchpad bit r/w 0b vcc1_r eset 30:24 gpio[136:130] input r 00h vcc1_r eset 23:16 gpio[127:120] input r 00h vcc1_r eset 15:8 gpio[117:110] input r 00h vcc1_r eset 7:0 gpio[107:100] input r 00h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 257 MEC1322 20.8.4.4 input gpio[140:176] 20.8.4.5 input gpio[200:236] offset 30ch( note 20-3 ) bits description type default reset event 31 scratchpad bit r/w 0b vcc1_r eset 30:22 reserved r 00h vcc1_r eset 21:16 gpio[165:160] input r 00h vcc1_r eset 15:8 gpio[157:150] input r 00h vcc1_r eset 7:0 gpio[147:140] input r 00h vcc1_r eset offset 310h( note 20-3 ) bits description type default reset event 31 scratchpad bit r/w 0b vcc1_r eset 30:24 scratchpad bits r/w 00h vcc1_r eset 23:16 scratchpad bits r/w 00h vcc1_r eset 15:12 reserved res - - 11:10 mchp reserved r/w 00h vcc1_r eset 9:8 gpio[211:210] input r/w 00h vcc1_r eset 7 reserved res - - 6 gpio206 input r/w 00h vcc1_r eset 5 reserved res - - 4:0 gpio[204:200] input r/w 00h vcc1_r eset
MEC1322 ds00001719d-page 258 ? 2014 - 2015 microchip technology inc. 21.0 internal dma controller 21.1 introduction the internal dma controller transfers data to/from the source from/to the destination. the firmware is responsible for setting up each channel. afterwards either the firmware or the hardware may perform the flow control. the hardware flow control exists entirely inside the source device. each tr ansfer may be 1, 2, or 4 bytes in size, so long as the device supports a transfer of that size. every device must be on the internal 32-bit address space. 21.2 references no references have been cited for this chapter 21.3 terminology table 21-1: terminology term definition dma transfer this is a complete dma transfer which is done after the master device terminates the transfer, the firmware aborts the transfer or the dma reaches its transfer limit. a dma transfer may consist of one or more data packets. data packet each data packet may be composed of 1, 2, or 4 bytes. the size of the data packet is limited by the max size supported by both the source and the des- tination. both source an d destination will transfer the same number of bytes per packet. channel the channel is responsible for end-to-end (source-to-destination) data packet delivery. device a device may refer to a master or slave connected to the dma channel. each dma channel may be assigned one or more devices. master device this is the master of the dma, which determines when it is active. the firmware is the master while operating in firmware flow control. the hardware is the master while operating in hardware flow control. the master device in hardwa re mode is selected by dma channel con- trol:hardware flow control device . it is the index of the flow control port. slave device the slave device is defined as the device associated with the targeted memory address. source the dma controller moves data from the source to the destination. the source provides the data. the source may be either the master or slave controller. destination the dma controller moves data from the source to the destination. the destination receives the data. the destination may be either the master or slave controller.
? 2014 - 2015 microchip technology inc. ds00001719d-page 259 MEC1322 21.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 21.4.1 signal description this block doesn?t have any external signals that may be rout ed to the pin interface. this dma controller is intended to be used internally to transfer large amounts of data without the embedded controller being actively involved in the trans- fer. 21.4.2 host interface the registers defined for the internal dma controller are accessible by the vari ous hosts as indicated in section 21.9, "ec-only registers" . 21.4.3 dma interface each dma master device that may engage in a dma transfer must have a compliant dma interface. the following table lists the dma devices in the MEC1322. note 21-1 the device number is programmed into field hardware_flow_control_device of the dma channel n control register. figure 21-1: internal dm a controller i/o diagram table 21-2: dma contro ller device selection device name device number ( note 21-1 ) controller source smbus 0 controller 0 slave 1master smbus 1 controller 2 slave 3master smbus 2 controller 4 slave 5master smbus 3 controller 6 slave 7master spi 0 controller 8 transmit 9receive spi 1 controller 10 transmit 11 receive internal dma controller power, clocks and reset interrupts dma interface host interface
MEC1322 ds00001719d-page 260 ? 2014 - 2015 microchip technology inc. table 21-3: dma controller ma ster devices signal list device name dev num ( 21.5 ) device signal name direction description smbus 0 controller 0 smb_sdma_req input dma request control from smbus slave channel. smb_sdma_term input dma termination control from smbus slave channel. smb_sdma_done output dma termination control from dma con- troller to slave channel. 1 smb_mdma_req input dma request control from smbus master channel. smb_mdma_term input dma termination control from smbus mas- ter channel. smb_mdma_done output dma termination control from dma con- troller to master channel. smbus 1 controller 2 smb_sdma_req input dma request control from smbus slave channel. smb_sdma_term input dma termination control from smbus slave channel. smb_sdma_done output dma termination control from dma con- troller to slave channel. 3 smb_mdma_req input dma request control from smbus master channel. smb_mdma_term input dma termination control from smbus mas- ter channel. smb_mdma_done output dma termination control from dma con- troller to master channel. smbus 2 controller 4 smb_sdma_req input dma request control from smbus slave channel. smb_sdma_term input dma termination control from smbus slave channel. smb_sdma_done output dma termination control from dma con- troller to slave channel. 5 smb_mdma_req input dma request control from smbus master channel. smb_mdma_term input dma termination control from smbus mas- ter channel. smb_mdma_done output dma termination control from dma con- troller to master channel.
? 2014 - 2015 microchip technology inc. ds00001719d-page 261 MEC1322 21.5 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 21.5.1 power domains 21.5.2 clock inputs smbus 3 controller 6 smb_sdma_req input dma request control from smbus slave channel. smb_sdma_term input dma termination control from smbus slave channel. smb_sdma_done output dma termination control from dma con- troller to slave channel. 7 smb_mdma_req input dma request control from smbus master channel. smb_mdma_term input dma termination control from smbus mas- ter channel. smb_mdma_done output dma termination control from dma con- troller to master channel. spi 0 controller 8 spi_sdma_req input dma request control from spi tx channel. spi_sdma_term input dma termination control from spi tx channel. not supported. spi_sdma_done output dma termination control from dma con- troller to tx channel. not supported. 9 spi_mdma_req input dma request control from spi rx channel. spi_mdma_term input dma termin ation control from spi rx channel. not supported. spi_mdma_done output dma termination control from dma con- troller to rx channel. not supported. spi 1 controller 10 spi_sdma_req input dma request control from spi tx channel. spi_sdma_term input dma termination control from spi tx channel. not supported. spi_sdma_done output dma termination control from dma con- troller to tx channel. not supported. 11 spi_mdma_req input dma request control from spi rx channel. spi_mdma_term input dma termin ation control from spi rx channel. not supported. spi_mdma_done output dma termination control from dma con- troller to rx channel. not supported. table 21-4: power sources name description vcc1 this power well sources the registers and logic in this block. table 21-5: clock inputs name description 48 mhz ring oscillator this clock signal drives sele cted logic (e.g., counters). table 21-3: dma controller master devices signal list (continued) device name dev num ( 21.5 ) device signal name direction description
MEC1322 ds00001719d-page 262 ? 2014 - 2015 microchip technology inc. 21.5.3 resets 21.6 interrupts this section defines the interrupt sources generated from this block. 21.7 low power modes the internal dma controller may be put into a low power state by the ch ip?s power, clocks, an d reset (pcr) circuitry. when the block is commanded to go to sleep it will place the dma block into sleep mode only after all transactions on the dma have been completed. for firmware flow controlled transactions, the dma will wait until it hits its terminal count and clears the go control bit. for hardware flow control, the dma will go to sleep after either the terminal count is hit, or the master device flags the terminate signal. 21.8 description the MEC1322 features a 12 channel dma controller. th e dma controller can autonomously move data from/to any dma capable master device to/from any populated memory locati on. this mechanism allows hardware ip blocks to transfer large amounts of data into or out of memory without ec intervention. the dma has the following characteristics: ? data is only moved 1 data packet at a time ? data only moves between devices on the accessible via the internal 32-bit address space table 21-6: reset signals name description vcc1_reset this reset signal resets all of the registers and logic in this block. reset this reset is gen erated if either the vcc1_reset is asserted or the soft_reset is asserted. table 21-7: interrupts source description dma0 direct memory access channel 0 this signal is generated by the status_done bit. dma1 direct memory access channel 1 this signal is generated by the status_done bit. dma2 direct memory access channel 2 this signal is generated by the status_done bit. dma3 direct memory access channel 3 this signal is generated by the status_done bit. dma4 direct memory access channel 4 this signal is generated by the status_done bit. dma5 direct memory access channel 5 this signal is generated by the status_done bit. dma6 direct memory access channel 6 this signal is generated by the status_done bit. dma7 direct memory access channel 7 this signal is generated by the status_done bit. dma8 direct memory access channel 8 this signal is generated by the status_done bit. dma9 direct memory access channel 9 this signal is generated by the status_done bit. dma10 direct memory access channel 10 this signal is generated by the status_done bit. dma11 direct memory access channel 11 this signal is generated by the status_done bit.
? 2014 - 2015 microchip technology inc. ds00001719d-page 263 MEC1322 ? the dma controller has 12 dma channels ? each dma channel may be configured to communicate with any dma capable device on the 32-bit internal address space. each device has been assigned a device number. see section 21.4.3, "dma interface," on page 259 . the controller will accesses sram buffers only with incrementing addresses (that is, it cannot start at the top of a buffer, nor does it handle circular buffers autom atically). the controller does not handle chaining (that is, automatically starting a new dma transfer when one finishes). 21.8.1 configuration the dma controller is enabled via the activate bit in dma main control register. each dma channel must also be individually enabled via the channel_activate bit in the dma channel n activate to be operational. before starting a dma transaction on a dma channel the host must assign a dma master to the channel via hard- ware_flow_control_device . the host must not configure two different channels to the same dma master at the same time. data will be transfered between the dm a master, starting at the programmed device_address , and the targeted memory location, starting at the memory_start_address . the address for either the dma master or the targeted memory location may remain static or it may increment. to enable the dma master to increment its address set the increment_device_address bit. to enable the targeted memory location to increment its addresses set the increment_memory_address . the dma transfer will continue as long as the target memory address being accessed is less than the memory_end_address . if the dma controller detects that the memory location it is attempting to access on the target is equal to the memory_end_address it will notify the dma master that the transaction is done. otherwise the data will be transferred in packets. the size of the packet is determined by the transfer_size . 21.8.2 operation the dma controller is designed to move data from one memory location to another. 21.8.2.1 establishing a connection a dma master will initiate a dma transaction by reques ting access to a channel. the dma arbiter, which evaluates each channel request using a basic round robin algorithm, will grant access to the dma master. once granted, the chan- nel will hold the grant until it decides to release it, by notifying the dma controller that it is done. 21.8.2.2 initiating a transfer once a connection is established the dma master will issue a dma request to start a dma transfer. if firmware wants to have a transfer request serviced it must set the run bit to have its transfer requests serviced. firmware can initiate a transaction by setting the transfer_go bit. the dma transfer w ill remain active until either the master issues a terminate or the dma controller signals that the transfer is done . firmware may terminate a trans- action by setting the transfer_abort bit. data may be moved from the dma master to the targeted me mory address or from the targeted memory address to the dma master. the direction of the transfer is determined by the transfer_direction bit. once a transaction has been initiated firmware can use the status_done bit to determine when the transaction is completed. this status bit is routed to the interrupt interface. in the same register there are additional status bits that indicate if the transaction completed successfully or with errors. this bits are or?d together with the status_done bit to generate the interrupt event. each status be may be individually enabled/disabled from generating this event. note: if firmware wants to prevent any other channels from being granted while it is active it can set the lock_channel bit. note: before initiating a dma transaction via firmware the hardware flow control mus be disabled via the dis- able_hardware_flow_control bit.
MEC1322 ds00001719d-page 264 ? 2014 - 2015 microchip technology inc. 21.9 ec-only registers the dma controller consists of a main block and a number of channels. table 21-9, "main ec-only register summary" lists the registers in the main block and table 21-10, "channel ec-only register summary" lists the registers in each channel. the addresses of each register listed in these tabl es are defined as a relative offset to the ?base address? defined in the ec-only register base address table. the base address for the main block and each channel is defined in the table: the base address indicates where the first register can be accessed in a particular address space for a block instance. table 21-8: ec-only register base address table instance name channel number host address space base address dma controller main block ec 32-bit internal address space 4000_2400h dma controller 0 ec 32-bit internal address space 4000_2410h dma controller 1 ec 32-bit internal address space 4000_2430h dma controller 2 ec 32-bit internal address space 4000_2450h dma controller 3 ec 32-bit internal address space 4000_2470h dma controller 4 ec 32-bit internal address space 4000_2490h dma controller 5 ec 32-bit internal address space 4000_24b0h dma controller 6 ec 32-bit internal address space 4000_24d0h dma controller 7 ec 32-bit internal address space 4000_24f0h dma controller 8 ec 32-bit internal address space 4000_2510h dma controller 9 ec 32-bit internal address space 4000_2530h dma controller 10 ec 32-bit internal address space 4000_2550h dma controller 11 ec 32-bit internal address space 4000_2570h table 21-9: main ec-onl y register summary offset register name (mnemonic) 00h dma main control 04h dma data packet
? 2014 - 2015 microchip technology inc. ds00001719d-page 265 MEC1322 21.9.1 dma main control 21.9.2 dma data packet note 21-2 the letter ?n? following dma channel indicates the channel number. each channel implemented will have these registers to determine that channel?s operation. 21.9.3 dma channel n activate offset 00h bits description type default reset event 7:2 reserved r - - 1 soft_reset soft reset the entire module. this bit is self-clearing. w0b - 0 activate enable the blocks operation. 1=enable block. each individual channel must be enabled separately. 0=disable all channels. r/ws 0b reset offset 04h bits description type default reset event 31:0 data_packet debug register that has the data that is stored in the data packet. this data is read data from the currently active transfer source. r 0000h - table 21-10: channel ec-only register summary offset register name (mnemonic) ( note 21-2 ) 00h dma channel n activate 04h dma channel n memory start address 08h dma channel n memory end address 0ch dma channel n device address 10h dma channel n control 14h dma channel n interrupt status 18h dma channel n interrupt enable offset 00h bits description type default reset event 7:1 reserved r - - 0 channel_activate enable this channel for operation. the dma main control:activate must also be enabled for this chan- nel to be operational. r/w 0h reset
MEC1322 ds00001719d-page 266 ? 2014 - 2015 microchip technology inc. 21.9.4 dma channel n memory start address 21.9.5 dma channel n memory end address offset 04h bits description type default reset event 31:0 memory_start_address this is the starting address for the memory device. this field is updated by hardware after every packet transfer by the size of the transfer, as defined by dma channel control:channel transfer size while the dma channel control:increment memory address is enabled. the memory device is defined as the device that is the slave device in the transfer. ex. with hardware flow control, the memory device is the device that is not connected to the hardware flow controlling device. note: this field is only as larg e as the maximum allowed ahb address size in the system. if the haddr size is 24 bits, then bits [31:24] will be reserved. r/w 0000h reset offset 08h bits description type default reset event 31:0 memory_end_address this is the ending address for the memory device. this will define the lim it of the transfer, so long as dma channel control:increment memory address is enabled. when the memory start address is equal to this val ue, the dma will te rminate the trans- fer and flag the status dma channel interrupt:status done. note: this field is only as larg e as the maximum allowed ahb address size in the system. if the haddr size is 24 bits, then bits [31:24] will be reserved. r/w 0000h reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 267 MEC1322 21.9.6 dma channel n device address 21.9.7 dma channel n control offset 0ch bits description type default reset event 31:0 device_address this is the master device address. this is used as the address that will access the device on the dma. the device is defined as the master of the dma transfer; as in the device that is controlling the hardware flow control. this field is updated by hardware after every data packet transfer by the size of the transfer, as defined by dma channel con- trol:transfer size while the dma channel control:increment device address is enabled. note: this field is only as larg e as the maximum allowed ahb address size in the system. if the haddr size is 24 bits, then bits [31:24] will be reserved. r/w 0000h reset offset 10h bits description type default reset event 31:26 reserved r - - 25 transfer_abort this is used to abort the current transfer on this dma channel. the aborted transfer will be forced to terminate immediately. r/w 0h reset 24 transfer_go this is used for the firmware flow control dma transfer. this is used to start a transfer under the firmware flow control . do not use this in conjunction with the hardware flow control ; dma channel control:disabl e hardware flow control must be set in order for this field to function correctly. r/w 0h reset 23 reserved r - - 22:20 transfer_size this is the transfer size in bytes of each data packet transfer. note: the transfer size must be a legal transfer size. valid sizes are 1, 2 and 4 bytes. r/w 0h reset 19 disable_hardware_flow_control this will disable the hardware flow control . when disabled, any dma master device attempting to communicate to the dma over the dma flow control interface (p orts: dma_req, dma_term, and dma_done) will be ignored. this should be set before using the dma channel in firmware flow control mode. rw 0h reset
MEC1322 ds00001719d-page 268 ? 2014 - 2015 microchip technology inc. 18 lock_channel this is used to lock the arbitration of the channel arbiter on this channel once this channel is granted. once this is locked, it will remain on the arbiter until it has completed it transfer (either the transfer aborted, transfer done or transfer terminated conditions). note: this setting may starve other channels if the locked chan- nel takes an excessive period of time to complete. rw 0h reset 17 increment_device_address this will enable an auto-increment to the dma channel device address. 1: increment the dma channel device address by dma channel control:transfer size after every data packet transfer 0: do nothing rw 0h reset 16 increment_memory_address this will enable an auto-increment to the dma channel memory address. 1=increment the dma channel memory address by dma channel control:transfer size afte r every data packet transfer 0=do nothing note: if this is not set, the dma will never terminate the transfer on its own. it will have to be terminated through the hard- ware flow control or through a dma channel con- trol:transfer abort . rw 0h reset 15:9 hardware_flow_control_device this is the device that is connected to this channel as its hardware flow control master. the flow control interface is a bus with each master concatenated onto it. this selects which bus index of the concatenated flow con- trol interface bus is targeted towards this channel. the flow control interface port list is dma_req, dma_term, and dma_done . rw 0h reset 8 transfer_direction this determines the direction of the dma transfer. 1=data packet read from memory start address followed by data packet write to device address 0=data packet read from device address followed by data packet write to memory start address rw 0h reset 7:6 reserved r - - 5busy this is a status signal. 1=the dma channel is busy (fsm is not idle) 0=the dma channel is not busy (fsm is idle) ro 0h reset offset 10h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 269 MEC1322 4:3 status this is a status signal. the status decode is listed in priority order with the highest priority first. 3: error detected by the dma 2: the dma channel is externally done, in that the device has termi- nated the transfer over the hardware flow control through the port dma_term 1: the dma channel is locally done, in that memory start address equals memory end address 0: dma channel control:run is disabled (0x0) note: this functionality has been replaced by the interrupt field, and as such should never be used. the field will not flag back appropriately timed status, and if used may cause the firmware to become out-of-sync with the hardware. this field has multiple non-exclusive statuses, but may only display a single status. as such, multiple statuses may be true, but this will appear as though only a single status has been triggered. r0h reset 2done this is a status signal. it is only valid while dma channel con- trol:run is enabled. this is the inverse of the dma channel con- trol:busy field, except this is qualified with the dma channel control:run field. 1 = channel is done 0 = channel is not done or it is off ro 0h reset 1request this is a status field. 1= there is a transfer request from the master device 0= there is no transfer request from the master device ro 0h reset 0 run this is a control field. note: this bit only applies to hardware flow control mode. 1= this channel is enabled and will service transfer requests 0=this channel is disabled. all transfer requests are ignored rw 0h reset offset 10h bits description type default reset event
MEC1322 ds00001719d-page 270 ? 2014 - 2015 microchip technology inc. 21.9.8 dma channel n interrupt status 21.9.9 dma channel n interrupt enable offset 14h bits description type default reset event 7:3 reserved r - - 2 status_done this is an interrupt source register. this flags when the dma channel has completed a transfer suc- cessfully on its side. a completed transfer is defined as when the dma channel reaches its limit; memory start address equals memory end address . a completion due to a hardware flow control terminate will not flag this interrupt. 1= memory start address equals memory end address 0= memory start address does not equal memory end address r/wc 0h reset 1 status_flow_control this is an interrupt source register. this flags when the dma channel has encountered a hardware flow control request after the dma channel has completed the transfer. this means the master device is attempting to overflow the dma. 1=hardware flow control is requesting after the transfer has com- pleted 0=no hardware flow control event 0h reset 0 status_bus_error this is an interrupt source register. this flags when there is an error detected over the internal 32-bit bus. 1: error detected. r/wc 0h reset offset 18h bits description type default reset event 7:3 reserved r - - 2 status_enable_done this is an interrupt enable for dma channel interrupt:status done. 1=enable interrupt 0=disable interrupt r/w 0h reset 1 status_enable_flow_control_error this is an interrupt enable for dma channel interrupt:status flow control error. 1=enable interrupt 0=disable interrupt r/w 0h reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 271 MEC1322 0 status_enable_bus_error this is an interrupt enable for dma channel interru pt:status bus error. 1=enable interrupt 0=disable interrupt r/w 0h reset offset 18h bits description type default reset event
MEC1322 ds00001719d-page 272 ? 2014 - 2015 microchip technology inc. 22.0 smbus interface 22.1 introduction the MEC1322 smbus interface includes one instance of the smbus controller core. this chapter describes aspects of the smbus interface that are unique to the MEC1322 instantiations of this core; including, power domain, resets, clocks, interrupts, re gisters and the physical interface. for a general description, features, block diagram, func- tional description, registers interface and other core-specific details, see ref [ 1 ] (note: in this chapter, italicized text typically refers to smbus c ontroller core interface elements as described in ref [ 1 ]). 22.2 references 1. smbus controller core interface, revision 3.4, core-level architecture specification, smsc, 7/16/12 22.3 terminology there is no terminology defined for this chapter. 22.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. in addition, this block is equipped with 22.5 signal description the signal description table lists the signals t hat are typically routed to the pin interface. figure 22-1: i/o diagram of block table 22-1: signal description table name direction description smb_dat0 input/output smbus data port 0 smb_clk0 input/output smbus clock port 0 smb_dat1 input/output smbus data port 1 smb_clk1 input/output smbus clock port 1 note: the smb block signals that are shown in table 22-1 are routed to the smb pins as listed in table 22-2 . signal description smbus interface interrupts power, clocks and reset host interface dma interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 273 MEC1322 22.6 host interface the registers defined for the smbus interface are accessible as indicated in section 22.12, "smbus registers" . 22.7 dma interface this block is designed to communicate with the internal dma controller. this feature is defined in the smbus controller core interface specification ( see ref [ 1 ]). note: for a description of the internal dma controller implemented in this design see chapter 21.0, "internal dma controller" . 22.8 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 22.8.1 power domains 22.8.2 clock inputs 22.8.3 resets 22.9 interrupts 22.10 low power modes the smbus interface may be put into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. 22.11 description 22.11.1 smbus controller core the MEC1322 smbus interface behavior is defined in the smbus controller core interface specification ( see ref [ 1 ]). table 22-2: signal to pi n name lookup table block name pin name description smbx_datn i2cx_datn smbus controller x port n data smbx_clkn i2cx_clkn smbus controller x port n clock table 22-3: power sources name description vcc1 this power well sources the regi sters and logic in this block. table 22-4: clock inputs name description 48 mhz ring oscillator this is the clock signal drives the smbus controller core. the core also uses this clock to generate the smb_clk on the pin interface. 16mhz_clk this is the clock signal is used for baud rate generation. table 22-5: reset signals name description vcc1_reset this reset signal resets all of the registers and logic in the smbus controller core. table 22-6: ec interrupts source description smb smbus activity interrupt event
MEC1322 ds00001719d-page 274 ? 2014 - 2015 microchip technology inc. 22.11.2 physical interface the smbus interface has two physical ports, selected by the port sel [3:0] bits in the configuration register as described in ref [ 1 ]. note 1: smbus controller 0 uses port 0 and port 1. smbus controllers 1-3 use port 0. 2: the buffer type for these pins must be configured as open-drain outputs in the gpio configuration registers associated with the gpio signals that share the ports. 22.12 smbus registers the registers listed in the smbus core register summary table in the smbus controller core interface specification (ref [ 1 ]) are for a single instance of the smbus controller core. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the following table: note 22-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. table 22-7: ec-only register base address table block instance instance number host address space base address ( note 22-1 ) smbus controller 0 ec 32-bit internal address space 4000_1800h smbus controller 1 ec 32-bit internal address space 4000_ac00h smbus controller 2 ec 32-bit internal address space 4000_b000h smbus controller 3 ec 32-bit internal address space 4000_b400h
? 2014 - 2015 microchip technology inc. ds00001719d-page 275 MEC1322 23.0 peci interface 23.1 overview the MEC1322 includes a peci interface to allow the ec to retrieve temperature readings from peci-compliant devices. the peci interface implements the phy and link layer of a peci host controller as defined in references [ 1 ] and includes hardware support for the peci 2.0 command set. this chapter focuses on MEC1322 specific peci interface configuration information such as power domains , clock inputs , resets , interrupts , and other chip specific information. for a functional description of the MEC1322 peci inter- face refer to references [ 1 ]. 23.2 references 1. peci interface core, rev. 1.31, core-level architecture specification, smsc confidential, 4/15/11 23.3 terminology no terminology has been defined for this chapter. 23.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 23.5 signal description the signal description table lists the signals t hat are typically routed to the pin interface. figure 23-1: peci interface i/o diagram table 23-1: signal description table name direction description peci_ready input peci ready input pin note: this signal is optional. if this signal is not on the pin inter- face it is pulled high internally. peci_dat input/output peci data signal pin note: routing guidelines for the peci_dat pin is provided in intel platform design guides. refer to the appropri- ate intel document for current information. see ta b l e 2 3 - 2 . peci_ready peci_dat peci interface power, clocks and reset interrupts host interface
MEC1322 ds00001719d-page 276 ? 2014 - 2015 microchip technology inc. 23.6 host interface the registers defined for the peci interface are accessible by the various hosts as indicated in section 23.11, "peci interface registers" . 23.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 23.7.1 power domains 23.7.2 clock inputs 23.7.3 resets 23.8 interrupts this section defines the interrupt sources generated from this block. 23.9 low power modes the peci interface may be put into a low power state by the chip ?s power, clocks, and reset (pcr) circuitry. 23.10 instance description there is one instance of the peci core implemented in the peci interface in the MEC1322. see peci interface core, rev. 1.31, core-level architecture specification, smsc confidential, 4/15/11 for a description of the peci core. 23.11 peci interface registers the registers listed in the peci interface regist er summary table are for a single instance of the peci interface . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the peci interface register base address table. table 23-2: peci routing guidelines trace impedance 50 ohms +/- 15% spacing 10 mils routing layer microstrip trace width calculate to match impedance length 1? - 15? table 23-3: power sources name description vcc1 the peci interface logic and registers are powered by vcc1 . table 23-4: clock inputs name description 48 mhz ring oscillator peci module input clock table 23-5: reset signals name description vcc1_reset peci core reset input table 23-6: ec interrupts source description pecihost peci host
? 2014 - 2015 microchip technology inc. ds00001719d-page 277 MEC1322 note 23-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. for register details see references [ 1 ]. table 23-7: ec-only register base address table block instance instance number host address space base address ( note 23-1 ) peci interface 0 ec 32-bit internal address space 4000_6400h table 23-8: peci interface register summary offset register name (mnemonic) 00h write data register 04h read data register 08h control register 0ch status register 1 10h status register 2 14h error register 18h interrupt enable 1 register 1ch interrupt enable 2 register 20h optimal bit time register (low byte) 24h optimal bit time register (high byte) 28h mchp reserved 2ch mchp reserved 30h-3ch reserved 40h block id register 44h revision register 48h - 7ch mchp reserved note: mchp reserved registers are reserved for microchi p use only. reading and writing mchp reserved reg- isters may cause undesirable results
MEC1322 ds00001719d-page 278 ? 2014 - 2015 microchip technology inc. 24.0 tach 24.1 introduction this block monitors tach output signals (or locked rotor signals) from various types of fans, and determines their speed. 24.2 references no references have been cited for this feature. 24.3 terminology there is no terminology defined for this section. 24.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 24.5 signal description 24.6 host interface the registers defined for the tach are accessible by the various hosts as indicated in section 24.11, "ec-only regis- ters" . figure 24-1: i/o diagram of block table 24-1: signal description table name direction description tach input input tachometer signal from tachx pin. signal description tach interrupts power, clocks and reset host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 279 MEC1322 24.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 24.7.1 power domains 24.7.2 clock inputs 24.7.3 resets 24.8 interrupts this section defines the interrupt sources generated from this block. 24.9 low power modes the tach may be put into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. 24.10 description the tach block monitors tach output signals or locked rotor signa ls generated by various types of fans. these signals can be used to determine the speed of the attached fan. th is block is designed to monitor fans at fan speeds from 100 rpms to 30,000 rpms. typically, these are dc brushless fans that generate (with each revolution) a 50% duty cycle, two-period square wave, as shown in figure 24-2 below. in typical systems, the fans are powered by the main power supply. firmware may disable this block when it detects that the main power rail has been turned off by either clearing the tach_enable bit or putting the block to sleep via the supported low power mode interface (see low power modes ). name description vcc1 the logic and registers implemented in this block are powered by this power well. name description 100khz_clk this is the clock input to the tachometer monitor logic. in mode 1, the tach is measured in the number of these clocks. name description vcc1_reset this signal resets all the registers and logic in this block to their default state. source description tach this internal signal is generated from the or?d result of the status events, as defined in the tachx status register . figure 24-2: fan generated 50%duty cycle waveform one revolution
MEC1322 ds00001719d-page 280 ? 2014 - 2015 microchip technology inc. 24.10.1 modes of operation the tachometer block supports two modes of operat ion. the mode of operation is selected via the tach_reading_- mode_select bit. 24.10.1.1 free running counter in mode 0, the tachometer block uses the tach input as the clock source for the internal tach pulse counter (see tachx_counter ). the counter is incremented when it detects a rising edge on the tach input. in this mode, the firmware may periodically poll the tachx_counter field to determine the average speed over a period of time. the firmware must store the previous reading and the current reading to compute the number of pulses detected over a period of time. in this mode, the counter continuously incr ements until it reaches ffffh. it then wraps back to 0000h and continues counting. the firmware must ensure that the sample rate is greater than the time it takes for the counter to wrap back to the starting point. 24.10.1.2 mode 1 -- number of clock pulses per revolution in mode 1, the tachometer block uses its 100khz_clk clock input to measure the programmable number of tach pulses. in this mode, the internal tach pulse counter ( tachx_counter ) returns the value in number of 100khz_clk pulses per programmed number of tach_edges . for fans that generate two square waves per revolution, these bits should be configured to five edges. when the number of edges is detected, the counter is latched and the count_ready_status bit is asserted. if the count_ready_int_en bit is set a tach interrupt event will be generated. 24.10.2 out-of-limit events the tach block has a pair of limit registers that may be configured to generate an event if the tach indicates that the fan is operating too slow or too fast. if the exceeds one of the programmed limits, the tachx high limit register and the tachx low limit register , the bit tach_out_of_limit_status will be set. if the tach_out_of_limit_status bit is set, the tachometer block will generate an interrupt event. 24.11 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the tach . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only reg- ister base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. note: tach interrupts should be disabled in mode 0. table 24-2: ec-only register base address table block instance instance number host address space base address tach 0 ec 32-bit internal address space 4000_6000h tach 1 ec 32-bit internal address space 4000_6010h table 24-3: tach re gister summary offset register name (mnemonic) 00h tachx control register 04h tachx status register 08h tachx high limit register 0ch tachx low limit register
? 2014 - 2015 microchip technology inc. ds00001719d-page 281 MEC1322 24.11.1 tachx control register offset 00h bits description type default reset event 31:16 tachx_counter this 16-bit field contains the latched value of the internal tach pulse counter, which may be configured by the tach reading mode select field to operate as a free-running c ounter or to be gated by the tach input signal. if the counter is free-running (mode 0), the internal tach counter increments (if enabled) on transitions of the raw tach input signal and is latched into this field every time it is incremented. the act of reading this field will not reset the counter, which rolls over to 0000h after ffffh. the firmware will compute the delta between the current count reading and the previous count reading, to determine the num- ber of pulses detected over a programmed period. if the counter is gated by the tach input and clocked by 100khz_clk (mode 1), the internal co unter will be latched into the reading register when the programmed number of edges is detected or when the counter reaches ffffh. the internal counter is reset to zero after it is copied into this register. note: in mode 1, a counter value of ffffh means that the tach did not detect the programmed number of edges in 655ms. a stuck fan can be detected by setting the tachx high limit register to a number less than ffffh. if the internal counter then reaches ffffh, the reading register will be set to ffffh and an out -of-limit interrupt can be sent to the ec. r00h vcc1_ reset 15 tach_input_int_en 1=enable tach input toggle interrupt from tach block 0=disable tach input toggle interrupt from tach block r/w 0b vcc1_ reset 14 count_ready_int_en 1=enable count ready interrupt from tach block 0=disable count ready interrupt from tach block r/w 0b vcc1_ reset 13 reserved r - - 12:11 tach_edges a tach signal is a square wave with a 50% duty cycle. typically, two tach periods represents one revolution of the fan. a tach period con- sists of three tach edges. this programmed value represents the number of tach edges that will be used to dete rmine the interval for which the number of 100khz_clk pulses will be counted 11b=9 tach edges (4 tach periods) 10b=5 tach edges (2 tach periods) 01b=3 tach edges (1 tach period) 00b=2 tach edges (1/2 tach period) r/w 00b vcc1_ reset
MEC1322 ds00001719d-page 282 ? 2014 - 2015 microchip technology inc. 10 tach_reading_mode_select 1=counter is incremented on the rising edge of the 100khz_clk input. the counter is latched into the tachx_counter field and reset when the programmed number of edges is detected. 0=counter is incremented when tach input transitions from low-to- high state (default) r/w 0b vcc1_ reset 9 reserved r - - 8 filter_enable this filter is used to remove high frequency glitches from tach input. when this filter is enabled, tach input pulses less than two 100khz_- clk periods wide get filtered. 1= filter enabled 0= filter disabled (default) it is recommended that the tach input filter always be enabled. r/w 0b vcc1_ reset 7:2 reserved r - - 1 tach_enable this bit gates the clocks into the bl ock. when clocks are gated, the tachx pin is tristated. when re-ena bled, the internal counters will continue from the last known stat e and stale status events may still be pending. firmware should discard any status or reading values until the reading value has been updated at least one time after the enable bit is set. 1= tach monitoring enabled, clocks enabled. 0= tach idle, clocks gated r/w 0b vcc1_ reset 0 tach_out_of_limit_enable this bit is used to enable the tach_out_of_limit_status bit in the tachx status register to generate an interrupt event. 1=enable interrupt output from tach block 0=disable interrupt output from tach block (default) r/w 0b vcc1_ reset offset 00h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 283 MEC1322 24.11.2 tachx status register note 1: some fans offer a locked rotor output pin that generates a level event if a locked rotor is detected. this bit may be used in combination with the tach pin status bit to detect a locked rotor signal event from a fan. 2: tach input may come up as active for locked rotor events. this would not cause an interrupt event because the pin would not toggle. firmware must read the status events as part of the initialization process, if polling is not implemented. offset 04h bits description type default reset event 31:4 reserved r - - 3 count_ready_status this status bit is asserted when the tach input changes state and when the counter value is latched. this bit remains cleared to '0' when the tach_reading_mode_select bit in the tachx con- trol register is '0'. when the tach_reading_mode_select bit in the tachx con- trol register is set to '1', this bit is set to ?1? when the counter value is latched by the hardware. it is cleared when written with a ?1?. if count_ready_int_en in the tachx control register is set to 1, this status bit will assert the tach interrupt signal. 1=reading ready 0=reading not ready r/wc 0b vcc1_r eset 2 toggle_status this bit is set when tach input changes state. it is cleared when writ- ten with a ?1?. if tach_input_int_en in the tachx control regis- ter is set to ?1?, this status bit will assert the tach interrupt signal. 1=tach input changed state (this bit is set on a low-to-high or high-to- low transition) 0=tach stable r/wc 0b vcc1_r eset 1 tach_pin_status this bit reflects the state of tach input. this bit is a read only bit that may be polled by the embedded controller. 1= tach input is high 0= tach input is low r0b vcc1_r eset 0 tach_out_of_limit_status this bit is set when the tach count value is greater than the high limit or less than the low limit. it is cleared when written with a ?1?. to disable this status event set the limits to their extreme values. if tach_out_of_limit_enable in the tachx control register is set to 1?, this status bit will a ssert the tach interrupt signal. 1=tach is outside of limits 0=tach is within limits r/wc 0b vcc1_r eset
MEC1322 ds00001719d-page 284 ? 2014 - 2015 microchip technology inc. 24.11.3 tachx high limit register 24.11.4 tachx low limit register offset 08h bits description type default reset event 31:16 reserved - - - 15:0 tach_high_limit this value is compared with the value in the tachx_counter field. if the value in the counter is greater than the value programmed in this register, the tach_out_of_limit_status bit will be set. the tach_out_of_limit_status status event may be enabled to generate an interrupt to the embedded controller via the tach_out_of_limit_enable bit in the tachx control register . r/w ffffh vcc1_ reset offset 0ch bits description type default reset event 31:16 reserved r - - 15:0 tachx_low_limit this value is compared with the value in the tachx_counter field of the tachx control register . if the value in the counter is less than the value programmed in this register, the tach_out_of_lim- it_status bit will be set. the tach_out_of_limit_status sta- tus event may be enabled to generate an interrupt to the embedded controller via the tach_out_of_limit_enable bit in the tachx control register to disable the tach_out_of_limit_status low event, program 0000h into this register. r/w 0000h vcc1_ reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 285 MEC1322 25.0 pwm 25.1 introduction this block generates a pwm output that can be used to control 4-wire fans, blinking leds, and other similar devices. each pwm can generate an arbitrary duty cycle output at frequencies from less th an 0.1 hz to 24 mhz. the pwm con- troller can also used to generate the prochot output and speaker output. the pwmx counter on time registers and pwmx counter off time registers determine the operation of the pwm_output signals. see section 25.11.1, "pwmx counter on time register," on page 288 and section 25.11.2, "pwmx counter off time register," on page 289 for a description of the pwm_output signals. 25.2 references there are no standards referenced in this chapter. 25.3 terminology there is no terminology defined for this section. 25.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. there are no external signals for this block. figure 25-1: i/o diagram of block pwm interrupts power, clocks and reset host interface signal description
MEC1322 ds00001719d-page 286 ? 2014 - 2015 microchip technology inc. 25.5 signal description 25.6 host interface the registers defined for the pwm interface are accessible by the various hosts as indicated in section 25.11, "ec-only registers" . 25.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 25.7.1 power domains 25.7.2 clock inputs 25.7.3 resets 25.8 interrupts the pwm block does not generate any interrupt events. 25.9 low power modes the pwm may be put into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. when the pwm is in the sleep state, the internal counters reset to 0 and the internal state of the pwm and the pwm_output signal set to the off state. 25.10 description the pwm_output signal is used to generate a duty cycle of specified frequency. this block can be programmed so that the pwm signal toggles the pwm_output, holds it high, or holds it low. when the pwm is configured to toggle, the pwm_output alternates from high to low at the rate specified in the pwmx counter on time register and pwmx counter off time register . the following diagram illustrates how the clock inputs and registers are routed to the pwm duty cycle & frequency control logic to generate the pwm output. table 25-1: signal description table name direction description pwm_output output pulse width modulated signal to pwmx pin. table 25-2: power sources name description vcc1 the pwm logic and registers are power ed by this single power source. table 25-3: clock inputs name description 100khz_clk 100khz_clk clock input for generating low pwm frequencies, such as 10 hz to 100 hz. 48 mhz ring oscillator 48 mhz ring oscillator clock input for generating high pwm frequencies, such as 15 khz to 30 khz. table 25-4: reset signals name description vcc1_reset this reset signal resets all the logic in this block to its initial state including the registers, which are set to their defined default state.
? 2014 - 2015 microchip technology inc. ds00001719d-page 287 MEC1322 the pwm clock source to the pwm down counter, used to generate a duty cycle and frequen cy on the pwm, is deter- mined through the clock select[1] and clock pre-divider[6:3] bits in the pwmx configuration register register. the pwmx counter on/off time regi sters determine both t he frequency and duty cycle of the signal generated on pwm_output as described below. the pwm frequency is determined by the selected clock source and the total on and off time programmed in the pwmx counter on time register and pwmx counter off time register registers. the frequency is the time it takes (at that clock rate) to count down to 0 from the total on and off time. the pwm duty cycle is determi ned by the relative va lues programmed in the pwmx counter on time register and pwmx counter off time register registers. the pwm frequency equation and pwm duty cycle equation are shown below. figure 25-3: pwm frequency equation in figure 25-3 , the clocksourcefrequency variable is the frequency of the clock source selected by the clock select bit in the pwmx configuration register , and predivisor is a field in the pwmx configuration register . the pwmcoun- terontime, pwmcounterofftime are registers that are defined in section 25.11, "ec-only registers" . figure 25-2: block diagram of pwm controller note: in figure 25-2 , the 48 mhz ring oscillator is represented as clock_high and 100khz_clk is repre- sented as clock_low. pwm block pwm duty cycle & frequency control pwm_ output pwm registers clock_high clock_low invert_pwm clock select 16-bit down counter ec i/f clock pre- divider (15:0) pwm frequency 1 p redivisor 1 + () -------------------------------------------- clocksourcefrequency () pwmcounterontime p wmcounterofftime + () ------------------------------------------------------------------------------------------------------------------------------- =
MEC1322 ds00001719d-page 288 ? 2014 - 2015 microchip technology inc. figure 25-4: pwm duty cycle equation the pwmx counter on time register and pwmx counter off time register registers should be accessed as 16-bit values. 25.11 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the pwm . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only reg- ister base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 25.11.1 pwmx counter on time register table 25-5: ec-only register base address table block instance instance number host address space base address pwm 0 ec 32-bit internal address space 4000_5800h pwm 1 ec 32-bit internal address space 4000_5810h pwm 2 ec 32-bit internal address space 4000_5820h pwm 3 ec 32-bit internal address space 4000_5830h table 25-6: ec-only register summary offset register name (mnemonic) 00h pwmx counter on time register 04h pwmx counter off time register 08h pwmx configuration register offset 00h bits description type default reset event 31:16 reserved r - - 15:0 pwmx_counter_on_time this field determine both the fr equency and duty cycle of the pwm signal. when this field is set to ze ro and the pwmx_counter_off_- time is not set to zero, the pwm_output is held low (full off). r/w 0000h vcc1_r eset pwm duty cycle pwmcounterontime pwmcounterontime p wmcounterofftime + () ------------------------------------------------------------------------------------------------------------------------------- - =
? 2014 - 2015 microchip technology inc. ds00001719d-page 289 MEC1322 25.11.2 pwmx counter off time register 25.11.3 pwmx configuration register offset 04h bits description type default reset event 31:16 reserved r - - 15:0 pwmx_counter_off_time this field determine both the fr equency and duty cycle of the pwm signal. when this field is set to zero, the pwm_output is held high (full on). r/w ffffh vcc1_r eset offset 08h bits description type default reset event 31:7 reserved r - - 6:3 clock_pre_divider the clock source for the 16-bit down counter (see pwmx counter on time register and pwmx counter off time register ) is deter- mined by bit d1 of this register. the clock source is then divided by the value of pre-divider+1 and the resulting signal determines the rate at which the down counter w ill be decremented. for example, a pre-divider value of 1 divides the input clock by 2 and a value of 2 divides the input clock by 3. a pre- divider of 0 will disable the pre- divider option. r/w 0000b vcc1_r eset 2invert 1= pwm_output on state is active low 0=pwm_output on state is active high r/w 0b vcc1_r eset 1 clock_select this bit determines the clock source used by the pwm duty cycle and frequency control logic. 1=clock_low 0=clock_high r/w 0b vcc1_r eset 0 pwm_enable 1=enabled (default) 0=disabled (gates cl ocks to save power) note: when the pwm enable bit is set to 0 the internal counters are reset and the internal state machine is set to the off state. in addition, the pwm_output signal is set to the inactive state as determined by the invert bit. the pwmx counter on time register and pwmx counter off time register are not affected by the pwm enable bit and may be read and written while the pwm enable bit is 0. r/w 0b vcc1_r eset
MEC1322 ds00001719d-page 290 ? 2014 - 2015 microchip technology inc. 26.0 rpm-pwm interface 26.1 introduction the rpm-pwm interface is closed-loop rpm based fan control algorith m that monitors the fan?s speed and automat- ically adjusts the drive to maintain the desired fan speed. the rpm-pwm interface functionality consists of a closed-loop ?set-and-forget? rpm based fan controller. 26.2 references no references have been cited for this chapter 26.3 terminology there is no terminology defined for this chapter. 26.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. the registers in the block are accessed by embedded controller code at the addresses shown in section 26.9, "fan control register bank" . figure 26-1 illustrates and categorizes the rpm-pwm interface block signals. these signals are described in table 26- 1 . 26.4.1 fan control the fan control signal description table lists the signals that are routed to/from the block. 26.4.2 host interface the registers defined for the rpm-pwm interface are accessible by the vari ous hosts as indicated in section 26.9, "fan control register bank" . figure 26-1: rpm-pwm interface i/o diagram table 26-1: fan control signal description table name direction description tach input tachometer input from fan pwm output pwm fan drive output rpm-pwm interface power, clocks and reset interrupts host interface fan control
? 2014 - 2015 microchip technology inc. ds00001719d-page 291 MEC1322 26.5 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 26.5.1 power domains 26.5.2 clock inputs 26.5.3 resets 26.6 interrupts this section defines the interrupt sources generated from this block. 26.7 low power modes the rpm-pwm interface may be put into a low power state by the ch ip?s power, clocks, and reset (pcr) circuitry. 26.8 description this section defines the functionality of the block. 26.8.1 general operation the rpm-pwm interface is an rpm based fan control algorithm that monitors the fan?s speed and automatically adjusts the drive to maintain the desired fan speed. th is rpm based fan control algorithm controls a pwm output based on a tachometer input. 26.8.2 fan control modes of operation the rpm-pwm interface has two modes of operation for the pwm fan driver. they are: 1. manual mode - in this mode of operation, the user direct ly controls the fan drive setting. updating the fan driver setting register (see section 26.9.1, "fan setting register" ) will update the fan drive based on the programmed ramp rate (default disabled). ? the manual mode is enabled by clearing the en_a lgo bit in the fan configuration register (see section 26.9.3, "fan configuration 1 register" ). ? whenever the manual mode is enabled the current drive settings will be changed to what was last used by the rpm control algorithm. ? setting the drive value to 00h w ill disable the pwm fan driver. ? changing the drive value from 00h will invoke the spin up routine. table 26-2: power sources name description vcc1 this power well sources the regi sters and logic in this block. table 26-3: clock inputs name description 48 mhz ring oscillator this clock signal drives sele cted logic (e.g., counters). table 26-4: reset signals name description vcc1_reset this reset signal resets all of the registers and logic in this block. table 26-5: interrupts source description fan fail/spin status interrupt the drive_fail & fan_spin bits in the fan status register are logi- cally ored and routed to the fail_spin interrupt fan stall status interrupt the fan_stall bit in the fan status register is routed to the fan_stall interrupt
MEC1322 ds00001719d-page 292 ? 2014 - 2015 microchip technology inc. 2. using rpm based fan control algorithm - in this mode of operation, the user determines a target tachometer reading and the drive setting is automatically updated to achieve this target speed. 26.8.3 rpm based fan control algorithm the rpm-pwm interface includes an rpm based fan control algorithm. the fan control algorithm uses proportional, integral, and de rivative terms to automatically approach and maintain the system?s desired fan speed to an accuracy directly proportional to the accuracy of the clock source. figure 26-2, "rpm based fan control algorithm" shows a simple flow diag ram of the rpm based fan control algorithm operation. the desired tachometer count is set by the user inputting the desired number of 32.768khz cycles that occur per fan revolution. the user may change the target count at any time. the user may also set the target count to ffh in order to disable the fan driver. for example, if a desired rpm rate for a 2-pole fan is 3 000 rpms, the user would input the hexadecimal equivalent of 1312d (52_00h in the tach target registers). this number represents the number of 32.768khz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000rpms (see section 26.9.11, "tach target register" and section 26.9.12, "tach reading register" ). the rpm-pwm interface ?s rpm based fan control algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. the fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the interrupt signal. the rpm-pwm interface works with fans that oper- ate up to 16,000 rpms and provide a valid tachometer signal. the fan controller will function either with an externally supplied 32.768khz clock source or with its own inter nal 32khz oscillator depending on the required accuracy. table 26-6: fan controls active for operating mode manual mode algorithm fan driver setting (read / write) fan driver setting (read only) edges[1:0] (fan configuration) edges[1:0] (fan configuration) update[2:0] (fan configuration) update[2:0] (fan configuration) level (spin up configuration) level (spin up configuration) spinup_time[1:0] (spin up configuration) spinup_time[1:0] (spin up configuration) fan step fan step - fan minimum drive valid tach count valid tach count - tach target tach reading tach reading range[2:0] (fan configuration 2) range[2:0] (fan configuration 2) - drive_fail_cnt[2:0] (spin up config) and drive fail band
? 2014 - 2015 microchip technology inc. ds00001719d-page 293 MEC1322 figure 26-2: rpm based fan control algorithm 26.8.3.1 programming the rpm based fan control algorithm the rpm based fan control algorithm powers-up disabled . the following registers control the algorithm. the rpm- pwm interface fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the tach target register is required to set a fa n speed. the other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. 1. set the valid tach count register to the minimum ta chometer count that indicates the fan is spinning. 2. set the spin up configuration register to the spin up level and spin time desired. 3. set the fan step register to the desired step size. 4. set the fan minimum drive regist er to the minimum drive value th at will maintain fan operation. 5. set the update time, and edges options in the fan configuration register. 6. set the tach target register to the desired tachometer count. 7. enable the rpm based fan control algorithm by setting the en_algo bit. set tach target count measure fan speed perform spin up routine maintain fan drive ramp rate control reduce fan drive increase fan drive spin up required ? tach reading= tach target? tach reading < tach target? yes no no no yes yes
MEC1322 ds00001719d-page 294 ? 2014 - 2015 microchip technology inc. 26.8.3.2 tachometer measurement in both modes of operation, the tachometer measurement operates independently of the mode of operation of the fan driver and rpm based fan speed control algorithm. any tach ometer reading that is higher than the valid tach count (see section 26.9.9, "valid tach count register" ) will flag a stalled fan a nd trigger an interrupt. when measuring the tachometer, the fan must provide a valid tachometer signal at all times to ensure proper operation. the tachometer measurement circuitry is programmable to detect the fan speed of a variety of fan configurations and architectures including 1-pole, 2-pole (default), 3-pole, and 4-pole fans. application note: the tachometer measurement works independently of the drive settings. if the device is put into manual mode and the fan drive is set at a level that is lower than the fan can operate (including zero drive), the tachometer measurement may signal a stalled fan condition and assert an interrupt. stalled fan if the tach reading register exceeds the user-programmable valid tach count setting, it will flag the fan as stalled and trigger an interrupt. if the rpm based fan control algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. the fan_stall status bit indicates that a stalled fan was detected. this bit is checked conditionally depending on the mode of operation. ? whenever the manual mode is enabled or whenever the drive value is changed from 00h, the fan_stall inter- rupt will be masked for t he duration of the programm ed spin up time (see table 26-17, ?spin time,? on page 303 ) to allow the fan an opportunity to reach a valid speed without generating unnecessary interrupts. ? in manual mode, whenever the tach reading register exceeds the valid tach count register setting, the fan_stall status bit will be set. ? when the rpm based fan control algorithm, the stalled fan condition is checked whenever the update time is met and the fan drive setting is updated. it is not a continuous check. 26.8.3.3 spin up routine the rpm-pwm interface also contains programmable circuitry to control th e spin up behavior of the fan driver to ensure proper fan operation. the spin up routine is initiated under the following conditions: ? the tach target high byte register value changes from a value of ffh to a value that is less than the valid tach count (see section 26.9.9, "valid tach count register" ). ? the rpm based fan control algorithm?s measured tachometer reading is greater than the valid tach count. ? when in manual mode, the drive setting changes from a value of 00h. when the spin up routine is operating, the fan driver is set to full scale for one quarter of the total user defined spin up time. for the remaining spin up time, the fan driver outp ut is set a a user defined level (30% to 65% drive). after the spin up routine has finished, the rpm-pwm interface measures the tachometer. if the measured tachometer reading is higher than the valid tach count register setti ng, the fan_spin status bit is set and the spin up routine will automatically attempt to restart the fan. application note: when the device is operating in manual mode, the fan_spin status bit may be set if the fan drive is set at a level that is lower than the fan can operate (excluding zero drive which disables the fan driver). if the fan_spin interr upt is unmasked, this condition will trigger an errant interrupt. figure 26-3, "spin up routine" shows an example of the spin up routine in response to a programmed fan speed change based on the first condition above.
? 2014 - 2015 microchip technology inc. ds00001719d-page 295 MEC1322 figure 26-3: spin up routine 26.8.4 pwm driver the rpm-pwm interface contains an optional, programmable 8-bit pwm driver which can serve as part of the rpm based fan speed control algorithm or in manual mode. when enabled, the pwm driver can operate in four prog rammable frequency bands. the lower frequency bands offer frequencies in the range of 9.5hz to 4.8khz while the hi gher frequency options offer frequencies of 21hz or 25.2khz. 26.8.5 alerts and limits figure 26-4, "interrupt flow" shows the interactions of the interrupts for fan events. if the fan driver detects a drive fail, spin-up or stall ev ent, the interrupt signal will be asserted (if enabled). all of these interrupts can be masked from asserting the interrupt signal individually. if any bit of either status register is set, the interrupt signal will be asserted provided that the corresponding interrupt enable bit is set accordingly. the status register will be updated due to an active event, regardless of the setting of the individual enable bits. once a status bit has been set, it will remain set until the status register bit is written to 1 (and the error condition has been removed). if the interrupt signal is asserted, it will be cleared im mediately if either the status or enable bit is cleared. see section 26.6, "interrupts," on page 291 . 100% (optional) prev target count = ffh update time spin up time ? of spin up time target count changed check tach target count reached 30% through 65% fan step algorithm controlled drive new target count
MEC1322 ds00001719d-page 296 ? 2014 - 2015 microchip technology inc. figure 26-4: interrupt flow 26.9 fan control register bank the registers listed in the table 26-8, "fan control register summary" are for a single instance of the rpm-pwm inter- face block. the addresses of each register listed in this tabl e are defined as a relative offset to the host ?base address? defined in table 26-7, "fan control register bank base address table" . note 26-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. table 26-7: fan control register bank base address table instance name instance number host address space base address ( note 26-1 ) rpm-pwm inter- face 0 ec 32-bit internal address space 4000_a000h table 26-8: fan control register summary register name offset fan setting 00h pwm divide 01h fan configuration 1 02h fan configuration 2 03h mchp reserved 04h gain 05h fan spin up configuration 06h fan step 07h fan minimum drive 08h valid tach count 09h fan drive fail band low byte 0ah fan drive fail band high byte 0bh tach target low byte 0ch tach target high byte 0dh tach reading low byte 0eh interrupt status bit 1 interrupt enable bit 1 interrupt status bit n interrupt enable bit n . . . . . . . . . interrupt signal . . . interrupt event 1 interrupt event n
? 2014 - 2015 microchip technology inc. ds00001719d-page 297 MEC1322 26.9.1 fan setting register the fan setting registers are used to control the output of the fan driver. the driver setting operates independently of the polarity bit for the pwm output. that is, a setting of 00h will mean that the fan drive is at minimum drive while a value of ffh will mean that the fan drive is at maximum drive. if the spin up routine is invoked, reading from the register s will return the current fan drive setting that is being used by the spin up routine instead of what was previously written into these registers. the fan driver setting registers, when the rpm based fan control algorithm is enabled, are read only. writing to the register will have no effect and the data will not be stored. reading from the register will always return the current fan drive setting. if the int_pwrgd pin is de-asserted, the fan driver setting r egister will be made read only. writing to the register will have no effect and reading from the register will return 000h. when the rpm based fan control algorithm is disabled, the current fan drive setting that was last used by the algorithm is retained and will be used. if the fan driver setting register is set to a value of 00h, all tachometer related status bits will be masked until the settin g is changed. likewise, the fan_short bit will be cleared and masked until the setting is changed. the contents of the regi ster represent the weight ing of each bit in determining the fi nal duty cycle. the output drive for a pwm output is given by the following equation: - drive = (fan_setting value/255) x 100%. 26.9.2 pwm divide register the pwm divide register determines the final pwm frequen cy. the base frequency set by the pwm_base[1:0] bits is divided by the decimal equivalent of the register settings. the final pwm frequency is derived as the base frequency divided by the value of this register as shown in the equation below: - pwm_frequency = base_clk / pwm_d where: - base_clk = the base frequency set by the pwmx_cfg[1:0] bits - pwm_d = the divide setting set by the pwm divide register. tach reading high byte 0fh pwm driver base frequency 10h fan status 11h offset 00h bits description type default reset event 7:0 fan_set ting[7:0] the fan driver setting used to control the output of the fan driver. r/w 00h vcc1_r eset offset 01h bits description type default reset event 7:0 pwm_divide[7:0] the pwm divide value determines the final frequency of the pwm driver. the driver base frequency is divided by the pwm divide value to determine the final frequency. r/w 01h vcc1_r eset table 26-8: fan control regi ster summary (continued) register name offset
MEC1322 ds00001719d-page 298 ? 2014 - 2015 microchip technology inc. 26.9.3 fan configuration 1 register the fan configuration register 1 controls the general oper ation of the rpm based fan control algorithm used by the fan driver. offset 02h bits description type default reset event 7en_algo enables the rpm based fan control algorithm. ? ?0? - (default) the control circuitry is disabled and the fan driver output is determined by the fan driver setting register. ? ?1? - the control circuitry is enabled and the fan driver output will be automatically updated to maintain the programmed fan speed as indicated by the tach target register. r/w 0b vcc1_r eset 6:5 range[1:0] adjusts the range of reported and programmed tachometer reading values. the range bits determine the weighting of all tach values (including the valid tach count, tach target, and tach reading) as shown in table 26-9, "range decode" . r/w 01b vcc1_r eset 4:3 edges[1:0] determines the minimum number of edges that must be detected on the tach signal to determine a single rotation. a typical fan mea- sured 5 edges (for a 2-pole fan). increasing the number of edges measured with respect to the num- ber of poles of the fan will cause the tach reading registers to indi- cate a fan speed that is higher or lower than the actual speed. in order for the fsc algorithm to operate correctly, the tach target must be updated by the user to accommodate this shift. the effec- tive tach multiplier shown in table 26-10, "minimum edges for fan rotation" is used as a direct multiplier term that is applied to the actual rpm to achieve the reported rpm. it should only be applied if the number of edges measured does not match the number of edges expected based on the number of poles of the fan (which is fixed for any given fan). contact microchip for recommended settings when using fans with more or less than 2 poles. r/w 01b vcc1_r eset 2:0 update[2:0] determines the base time between fan driver updates. the update time, along with the fan step register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. the update time is set as shown in table 26-11, "update time" . application note: this ramp rate control applies for all changes to the active pwm output including when the rpm based fan speed control algorithm is disabled. r/w 011b vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 299 MEC1322 26.9.4 fan configuration 2 register the fan configuration 2 register controls the tachometer measurement and advanced features of the rpm based fan control algorithm. table 26-9: range decode range [1:0] reported minimum rphm tach count multiplier 10 0 0 500 1 0 1 1000 (default) 2 1 0 2000 4 1 1 4000 8 table 26-10: minimum edges for fan rotation edges 1:0] minimum tach edges number of fan poles effective tach multiplier (based on 2 pole fans) if edges changed 10 00 3 1 0.5 0 1 5 2 (default) 1 10 7 3 1.5 11 9 4 2 table 26-11: update time update [2:0] tach count multiplier (ms) 210 0 0 0 100 0 0 1 200 0 1 0 300 0 1 1 400 (default) 1 0 0 500 1 0 1 800 110 1200 111 1600
MEC1322 ds00001719d-page 300 ? 2014 - 2015 microchip technology inc. offset 03h bits description type default reset event 7 mchp reserved r/w 0b vcc1_r eset 6 en_rrc enables the ramp rate control circuitry during the manual mode of operation. ? ?0? (default) - the ramp rate control circuitry for the manual mode of operation is disabled. when the fan drive setting val- ues are changed and the rpm based fan control algorithm is disabled, the fan driver will be set to the new setting immedi- ately. ? ?1? - the ramp rate control circuitry for the manual mode of oper- ation is enabled. the pwm setting will follow the ramp rate con- trols as determined by the fan step and update time settings. the maximum pwm step is capped at the fan step setting and is updated based on the update time as given by table 26-11, "update time" . r/w 0b vcc1_r eset 5dis_glitch disables the low pass glitch filter that removes high frequency noise injected on the tach pin. ? ?0? (default) - the glitch filter is enabled. ? ?1? - the glitch filter is disabled. r/w 0b vcc1_r eset 4:3 der_opt[1:0] control some of the advanced options that affect the derivative por- tion of the rpm based fan control algorithm as shown in table 26- 12, "derivative options" . these bits only apply if the fan speed control algorithm is used. r/w 11b vcc1_r eset 2:1 err_rng[1:0] control some of the advanced options that affect the error window. when the measured fan speed is within the programmed error win- dow around the target speed, the fan drive setting is not updated. these bits only apply if the fan speed control algorithm is used. see table 26-13, "error range options" . r/w 01b vcc1_r eset 0polarity determines the polarity of the pwm driver. this does not affect the drive setting registers. a setting of 0% drive will still correspond to 0% drive independent of the polarity. ? ?0? (default) - the polarity of the pwm driver is normal. a drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of ffh will cause the output to be set at 100% duty cycle. ? ?1? - the polarity of the pwm driver is inverted. a drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of ffh will cause the output to be set at 0% duty cycle. r/w 0b vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 301 MEC1322 26.9.5 gain register the gain register the gain register stores the gain term s used by the proportional and integral portions of the rpm based fan control algorithm. these terms will affect the fsc closed loop acquisition, overshoot, and settling as would be expected in a classic pid system. this register only applies if the fan speed control algorithm is used. table 26-12: derivative options der_opt[1:0] operation note (see section 26.9.7, "fan step register" ) 10 0 0 no derivative options used pwm steps are limited to the maxi- mum pwm drive step value in fan step register 0 1 basic derivative. the derivative of the error from the current drive setting and the target is added to the iterative pwm drive setting (in addition to proportional and integral terms) pwm steps are limited to the maxi- mum pwm drive step value in fan step register 1 0 step derivative. th e derivative of the error from the current drive setting and the target is added to the iterative pwm drive setting and is not capped by the maximum pwm drive step. this allows for very fast response times pwm steps are not limited to the max- imum pwm drive step value in fan step register (i.e., maximum fan step setting is ignored) 1 1 both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term (default). pwm steps are not limited to the max- imum pwm drive step value in fan step register (i.e., maximum fan step setting is ignored) table 26-13: error range options err_rngx[1:0] operation 10 00 0 rpm 0 1 50 rpm (default) 1 0 100 rpm 1 1 200 rpm offset 05h bits description type default reset event 7:6 reserved r/w 00h - 5:4 gaind[1:0] the derivative gain term. see table 26-14, "gain decode" . r/w 10h vcc1_r eset 3:2 gaini[1:0] the integral gain term. see table 26-14, "gain decode" . r/w 10h vcc1_r eset 1:0 gainp[1:0] the proportional gain term. see table 26-14, "gain decode" . r/w 10h vcc1_r eset
MEC1322 ds00001719d-page 302 ? 2014 - 2015 microchip technology inc. 26.9.6 fan spin up configuration register the fan spin up configuration register controls the settings of spin up routine. table 26-14: gain decode gaind or gainp or gaini [1:0] respective gain factor 10 00 1x 01 2x 1 0 4x (default) 11 8x offset 06h bits description type default reset event 7:6 drive_fail_cnt[1:0] determines how many update cycl es are used for the drive fail detection function as shown in table 26-15, "drive_fail_cnt[1:0] bit decode" . this circuitry determines whether the fan can be driven to the desired tach target. these settings only apply if the fan speed control algorithm is enabled . r/w 00b vcc1_r eset 5nokick determines if the spin up routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. ? ?0? (default) - the spin up routine will drive the pwm to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. ? ?1? - the spin up ro utine will not drive the pwm to 100%. it will set the drive at the programmed spin level for the entire duration of the programmed spin up time. r/w 0b vcc1_r eset 4:2 spin_lvl[2:0] spin_lvl[2:0] - determines the final drive level that is used by the spin up routine as shown in table 26-16, "spin level" . r/w 110b vcc1_r eset 1:0 spinup_ time[1:0] determines the maximum spin time that the spin up routine will run for. if a valid tachometer measurement is not detected before the spin time has elapsed, an interrupt will be generated. when the rpm based fan control algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. the spin time is set as shown in table 26-17, "spin time" . r/w 01b vcc1_r eset table 26-15: drive_fail_cnt[1:0] bit decode drive_fail_cnt[1:0] number of update periods 10 0 0 disabled - the drive fail detection circuitry is disabled 0 1 16 - the drive fail detection circuitry will count for 16 update periods
? 2014 - 2015 microchip technology inc. ds00001719d-page 303 MEC1322 26.9.7 fan step register the fan step register, along with the update time, controls th e ramp rate of the fan driver response calculated by the rpm based fan control algorithm for the derivative options fi eld values of ?00? and ?01? in the fan configuration 2 register (see table 26-12, ?derivative options,? on page 301 ). the value of the register represents the maximum step size the fan driver will take for each update (see section 26.9.3, "fan configuration 1 register," on page 298 ). when the maximum step size limitation is applied, if the necessary fan driver delta is larger than the fan step, it will be capped at the fan step setting and updated every update time ms. the maximum step size is ignored for the derivative options field values of ?10? and ?11?. 1 0 32 - the drive fail detection circuitry will count for 32 update periods 1 1 64 - the drive fail detection circuitry will count for 64 update periods table 26-16: spin level spin_lvl[2:0] spin up drive level 210 0 0 0 30% 0 0 1 35% 0 1 0 40% 0 1 1 45% 1 0 0 50% 1 0 1 55% 1 1 0 60% (default) 1 1 1 65% table 26-17: spin time spinup_time[1:0] total spin up time 10 0 0 250 ms 0 1 500 ms (default) 10 1 sec 11 2 sec offset 07h bits description type default reset event 7:6 reserved r/w 00h - 5:0 fan_step[5:0] the fan step value represents the maximum step size the fan driver will take between update times r/w 10h vcc1_r eset table 26-15: drive_fail_cnt[1:0] bit decode (continued) drive_fail_cnt[1:0] number of update periods 10
MEC1322 ds00001719d-page 304 ? 2014 - 2015 microchip technology inc. 26.9.8 fan minimum drive register the fan minimum drive register stores the minimum drive setting for the rpm based fan control algorithm. the rpm based fan control algorithm will not drive the fan at a level lower than the minimum drive unless the target fan speed is set at ffh (see "tach target registers" ). during normal operation, if the fan stops for any reason (i ncluding low drive), the rpm based fan control algorithm will attempt to restart the fan. setting the fan minimum drive registers to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan oper- ation. these registers only apply if the f an speed control algorithm is used. application note: to ensure proper operation, the fan minimum dr ive register must be set prior to setting the tach target high and low byte registers, and then the tach target registers can be subsequently updated. at a later time, if the fan minimum drive register is changed to a value higher than current fan value, the tach target registers must also be updated. 26.9.9 valid tach count register the valid tach count register stores the maximum tach readi ng register value to indicate that the fan is spinning properly. the value is referenced at the end of the spin up routine to determine if the fan has started operating and decide if the device needs to retry. see the equation in the tach reading registers section for translating the rpm to a count. if the tach reading register value exceeds the valid tach count register (indicating that the fan rpm is below the threshold set by this count), a stalled fan is detected. in th is condition, the algorithm will automatically begin its spin up routine. application note: the automatic invoking of the spin up routine only applies if the fan speed control algorithm is used. if the fsc is disabled, then the device will only invoke the spin up routine when the pwm setting changes from 00h. if a tach target setting is set above t he valid tach count setting, that setting will be ignored and the algorithm will use the current fan drive setting. these registers only apply if the f an speed control algorithm is used. 26.9.10 fan drive fail band register the fan drive fail band registers store the number of tach counts used by the fan drive fail detection circuitry. this circuitry is activated when the fan drive setting high byte is at ffh. when it is enabled, the actual measured fan speed is compared against the target fan speed. this circuitry is used to indicate that the target fan speed at full drive is higher than the f an is actually capable of reachi ng. if the measured fan speed does not exceed the target fan s peed minus the fan drive fail band register settings for a period of time longer than set by the drive_fail_cntx[1:0] bits in the fan spin up configuration register on page 302 , the drive_fail status bit will be set and an interrupt generated. these registers only apply if the f an speed control algorithm is used. offset 08h bits description type default reset event 7:0 min_drive[7:0] the minimum drive setting. r/w 66h vcc1_r eset offset 09h bits description type default reset event 7:0 valid_tach_cnt[7:0] the maximum tach reading register value to indicate that the fan is spinning properly. r/w f5h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 305 MEC1322 26.9.11 tach target register the tach target registers hold the target tachometer value that is maintained for the rpm based fan control algo- rithm. if the algorithm is enabled, setting the tach target register hi gh byte to ffh will disable the fan driver (or set the pwm duty cycle to 0%). setting the ta ch target to any othe r value (from a setting of ffh) will cause the algorithm to invoke the spin up routine after which it will function normally. these registers only apply if the f an speed control algorithm is used. 26.9.12 tach reading register the tach reading registers? contents describe the current tachometer reading for the fan. by default, the data rep- resents the fan speed as the number of 32.768khz clock periods that occur for a single revolution of the fan. the equation below shows the detailed conversion from tachometer measurement (count) to rpm. where: - poles = number of poles of the fan (typically 2) -f tach = the frequency of the tachometer measurement clock - n = number of edges measured (typically 5 for a 2 pole fan) - m = the multiplier defined by the range bits - count = tach reading register value (in decimal) the following equation shows the simplified translation of the tach reading register count to rpm assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768khz. offset 0ah bits description type default reset event 15:3 fan_drive_fail_band[12:0] the number of tach counts used by the fan drive fail detection cir- cuitry res 000000000 0000b vcc1_r eset 2:0 reserved r/w 000b - offset 0ch bits description type default reset event 15:3 tach_target[12:0] the target tachometer value. res 1111111111 111b vcc1_r eset 2:0 reserved r/w 000b - rpm 1 poles -------------- n 1 ? () count 1 m --- - ------------------------------- - ftach 60 = rpm 3932160 m count ------------------------------- =
MEC1322 ds00001719d-page 306 ? 2014 - 2015 microchip technology inc. 26.9.13 pwm driver base frequency register - the pwm driver base register controls the base pwm frequency range. 26.9.14 fan status register the bits in this register are routed to interrupts. offset 0eh bits description type default reset event 15:3 tach_reading[12:0] the current tachometer reading value. res 1111111111 111b vcc1_r eset 2:0 reserved r/w 000b - offset 10h bits description type default reset event 7:2 reserved res 000000b - 1:0 pwm_base[1:0] determines the frequency range of the pwm fan driver (when enabled) as shown in table 26-18 . r/w 00b vcc1_r eset table 26-18: pwm_base[1:0] decode pwm_base[1:0] pwm frequency 10 0 0 26.83khz 0 1 20.87khz 1 0 4.82khz 1 1 2.41khz offset 11h bits description type default reset event 7:6 reserved res 00b - 5 drive_fail the bit indicates that the rpm-based fan speed control algorithm cannot drive the fan to the desired target setting at maximum drive. ? ?0? - the rpm-based fan speed control algorithm can drive fan to the desired target setting. ? ?1? - the rpm-based fan speed control algorithm cannot drive fan to the desired target setting at maximum drive. r/wc 0b vcc1_r eset 4:2 reserved res 000b -
? 2014 - 2015 microchip technology inc. ds00001719d-page 307 MEC1322 1 fan_spin the bit indicates that the spin up routine for the fan could not detect a valid tachometer reading within its maximum time window. ? ?0? - the spin up routine for the fan detected a valid tachome- ter reading within its maximum time window. ? ?1? - the spin up routine for the fan could not detect a valid tachometer reading within its maximum time window. r/wc 0b vcc1_r eset 0 fan_stall the bit indicates that the tachometer measurement on the fan detects a stalled fan. ? ?0? - stalled fan not detected. ? ?1? - stalled fan not detected. r/wc 0b vcc1_r eset offset 11h bits description type default reset event
MEC1322 ds00001719d-page 308 ? 2014 - 2015 microchip technology inc. 27.0 general purpose seria l peripheral interface 27.1 overview the general purpose serial peripheral interface (gp-spi) may be used to communicate with various peripheral devices, e.g., eeproms, dacs, adcs, that use a standard serial peripheral interface. characteristics of the gp-spi controller include: ? 8-bit serial data transmitted and received simultaneously over two data pins in full duplex mode with options to transmit and receive data serially on one data pin in half duplex (bidirectional) mode. ? an internal programmable clock generator and clock polar ity and phase controls allowing communication with var- ious spi peripherals with specific clocking requirements. ? spi cycle completion that can be deter mined by status polling or interrupts. ? the ability to read data in on both spdin and spdout in parallel. this allows this spi interface to support dual data rate read accesses for emerging double rate spi flashes ? support of back-to-back reads and writes without clock st retching, provided the host can read and write the data registers within one byte transaction time. 27.2 references no references have been cited for this feature. 27.3 terminology no terminology for this block. 27.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. figure 27-1: i/o diagram of block general purpose serial peripheral interface interrupts power, clocks and reset host interface signal description
? 2014 - 2015 microchip technology inc. ds00001719d-page 309 MEC1322 27.5 signal description 27.6 host interface the registers defined for the general purpose serial peripher al interface are accessible by the various hosts as indi- cated in section 27.12, "ec-only registers" . 27.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 27.7.1 power domains 27.7.2 clock inputs 27.7.3 resets table 27-1: signal description table name direction description spdin input serial data in pin spdout input/output serial data output pin. switches to input when used in double-data- rate mode spi_clk output spi clock output used to drive the spclk pin. spi_cs# output spi chip select note: the spi block signals that are shown in table 27-1 are routed to the spi pins as listed in table 27-2 . table 27-2: signal to pi n name lookup table block name pin name spdin shd_miso, pvt_miso spdout shd_mosi, pvt_mosi spi_clk shd_sclk, pvt_sclk spi_cs# shd_cs0#, pvt_cs0# table 27-3: power sources name description vcc1 the logic and registers implemented in this block are powered by this power well. table 27-4: clock inputs name description 48 mhz ring oscillator this is a clock source fo r the spi clock generator. 2mhz this is a clock source for the spi clock generator. table 27-5: reset signals name description vcc1_reset this signal resets all the registers and logic in this block to their default state.
MEC1322 ds00001719d-page 310 ? 2014 - 2015 microchip technology inc. 27.8 interrupts this section defines the interrupt sources generated from this block. these status bits are also connected re spectively to the dma controller?s spi controller tx and rx requests signals. 27.9 low power modes the gp-spi interface may be put into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. 27.10 description the serial peripheral interface (spi) block is a master spi block used to communicate with external spi devices. the spi master is responsible for generating the spi clock and is designed to operate in full duplex, half duplex, and dual modes of operation. the clock source may be programmed to operated at various clock speeds. the data is transmit- ted serially via 8-bit transmit and receive shift registers. communication with spi peripherals that require transactions of varying lengths can be achieved with multiple 8-bit cycles. this block has many configuration options: the data may be transmitted and received either msbit or lsbit first; the spi clock polarity may be either active high or active low; data may be sampled or presented on either the rising of falling edge of the clock (referred to as the transmit clock phase); and the spi_clk spdout frequency may be pro- grammed to a range of values as illustrated in table 27-7, "spi_clk frequencies" . in addition to these many program- mable options, this feature has several status bits that may be enabled to notify the host that data is being transmitted or received. 27.10.1 initiating an spi transaction all spi transactions are initiated by a write to the tx_data register. no read or write operations can be initiated until the transmit buffer is empty, which is indicated by a one in the txbe status bit. if the transaction is a write operation, the host writes the tx_data register with the value to be transmitted. writing the tx_data register causes the t xbe status bit to be cleared, i ndicating that the value has bee n registered. if empty, the spi core loads this tx_data value into an 8-bit transmit shift register and begins shifting the data out. loading the value into the shift register causes the txbe status bit to be asserted, indicating to software that the next byte can be written to the tx_data register. if the transaction is a read operation, the host initiates a wr ite to the tx_data register in the same manner as the write operation. unlike the transmit command, the host must clear the rxbf status bit by reading the rx_data register before writing the tx_data register. this time, the host will be required to poll the rxbf status bit to determine when the value in the rx_data register is valid. note 1: if the spi interface is configured for half duplex mode, the host must still write a dummy byte to receive data. 2: since rx and tx transactions are executed by the same sequence of transactions, data is always shifted into the rx_data register. therefore, every write operation causes data to be latched into the rx_data register and the rxbf bit is set. th is status bit should be cleared before initiating subsequent transactions. the host utilizing this spi core to transmit spi data must discard the unwanted receive bytes. 3: the length and order of data sent to and received fr om a spi peripheral varies between peripheral devices. the spi must be properly configured and software-con trolled to communicate with each device and deter- mine whether spird data is valid slave data. the following diagrams show sample single byte and multi-byte spi transactions. table 27-6: ec interrupts source description txbe_sts transmit buffer empty status ( txbe ), in the spi status register , sent as an interrupt request to the interrupt aggregator. rxbf_sts receive buffer full status ( rxbf ), in the spi status register , sent as an interrupt request to the interrupt aggregator.
? 2014 - 2015 microchip technology inc. ds00001719d-page 311 MEC1322 figure 27-2: single byte spi tx/r x transactions (full duplex mode) single spi byte transactions rx_data buffer full (rxbf) tx_data buffer empty (txbe) write tx_data mclk spdout_direction tx_data byte 0 read rx_data rx_data byte 0 data out shift register 7 6 5 4 3 2 1 0 data in shift register 7 6 5 4 3 2 1 0 spclko
MEC1322 ds00001719d-page 312 ? 2014 - 2015 microchip technology inc. the data may be configured to be transmitted m sb or lsb first. this is configured by the lsbf bit in the spi control register . the transmit data is shifted out on the edge as selected by the tclkph bit in the spi clock control register . all received data can be sampled on a rising or falling spi_clk edge using the rclkph bit in the spi clock control register this clock setting must be identical to the clocking requirements of the current spi slave. there are three types of transactions that can be implemente d for transmitting and receiving the spi data. they are full duplex, half duplex, and dual m ode. these modes are define in section 27.10.3, "types of spi transactions" . 27.10.2 dma mode transmit and receive operations can use a dma channel. n ote that only one dma channel may be enabled at a time. setting up the dma controller involves specifying the device (flash gp-spi), dire ction (transmit/receive), and the start and end addresses of the dma buffers in the closely couple memory. please refer to the dma controller chap- ter for register programming information. spi transmit / dma write: the gp-spi block?s transmit empty (t xbe) status signal is used as a write request to the dma controller, which then fetches a byte from the dma transmit bu ffer and writes it to the gp-spi?s spi tx data register (spitd). as content of the latter is transferred to the internal tx shift register from which data is shifted out onto the spi bus bit by bit, the tx empty signal is again asserted, tr iggering the dma fetch-and-writ e cycle. the process continues until the end of the dma buffer is reached - the dma controller stops responding to an active tx empty until the buffer?s address registers are reprogrammed. spi receive / dma read: the auto_read bit in the spi contro l register must be set. the driver first writes (dummy data) to the spi tx data register (spitd) to initiate the toggling of the spi clock, enabling data to be shifted in. after one byte is received, the rx full (rxbf) status signal, used as a read request to the dma controller, is asserted. the figure 27-3: multi-byte spi tx/rx transactions (full duplex mode) note: common peripheral devices require a chip select signal to be asserted during a transaction. chip selects for spi devices may be controlled by MEC1322 gpio pins. spi byte transactions rx_data buffer full (rxbf) tx_data buffer empty (txbe) write tx_data mclk spdout_direction tx_data byte 0 byte 1 byte 2 read rx_data rx_data byte 0 byte 1 byt data out shift register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 data in shift register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 spclko 7 6 5 4 3 2 7 6 5 4 3 2 1 0 1 0
? 2014 - 2015 microchip technology inc. ds00001719d-page 313 MEC1322 dma controller then reads the received byte from the gp-spi?s spi rx data register (spird) and stores it in the dma receive buffer. with auto_read set, this read clears bo th the rxbf and txbe. clearing txbe causes (dummy) data from the spi tx data register (spitd) to be transferred to the internal shift register, mimicking the effect of the afore- mentioned write to the spi tx data register (spitd) by the driver. spi clock is toggled again to shift in the second read byte. this process continues until the end of the dma buffer is reached - the dma controller stops responding to an active tx empty until the buffer?s address registers are reprogrammed. 27.10.3 types of spi transactions the gp-spi controller can be configur ed to operate in three modes: full duplex, half duplex, and dual mode. 27.10.3.1 full duplex in full duplex mode, serial data is transmitted and received simultaneously by the spi master over the spdout and spdin pins. to enable full duplex mode clear spdin select. when a transaction is completed in the full-duplex mode, the rx_data shift register always contains received data (valid or not) from the last transaction. 27.10.3.2 half duplex in half duplex mode, serial data is transmitted and received sequentially over a single data line (referred to as the spd- out pin). to enable half duplex mode set spdin select to 01b. the direction of the spdout signal is determined by the bioen bit. ? to transmit data in half duplex mode set t he bioen bit before writing the tx_data register. ? to receive data in half duplex mode clear the bioen bi t before writing the tx_data register with a dummy byte. 27.10.3.3 dual mode of operation in dual mode, serial data is transmitted sequentially from the spdout pin and received in by the spi master from the spdout and spdin pins. this essentially doubles the received data rate and is often available in spi flash devices. to enable dual mode of operation the spi core must be configured to receive data in path on the spdin1 and spdin2 inputs via spdin select . the bioen bit determines if the spi core is transmitting or receiving. the setting of this bit determines the direction of the spdout signal. the spdin select bits are configuration bits that remain static for the duration of a dual read command. the bioen bit must be toggled to indicate when the spi core is transmitting and receiving. ? to transmit data in dual mode set the bioen bit before writing the tx_data register. ? to receive data in dual mode clear the bioen bit before writing the tx_data register with a dummy byte. the even bits (0,2,4,and 6) are received on the spdout pin and the odd bits (1,3,5,and 7) are received on the spdin pin. the hardware assembles these received bits into a single byte and loads them into the rx_data register accordingly. the following diagram illustrates a dual fast read command that is supported by some spi flash devices. note: the software driver must properly drive the bioen bit and store received data depending on the transac- tion format of the specific slave device.
MEC1322 ds00001719d-page 314 ? 2014 - 2015 microchip technology inc. 27.10.4 how bioen bit controls direction of spdout buffer when the spi is configured for half duplex mode or du al mode the spdout pin operates as a bi-directional signal. the bioen bit is used to determine the direction of the spdout buffer when a byte is transmitted. internally, the bioen bit is sampled to control the direction of the spdout buff er when the tx_data value is loaded into the transmit shift register. the direction of the buffer is never changed while a byte is being transmitted. since the tx_data register may be written while a byte is being shifted out on the spdout pin, the bioen bit does not directly control the direction of the spdout buffer. an internal direction bit, which is a latched version of the bioen bit determines the direction of the spdout buffer. the following list summarizes when the bioen bit is sam- pled. figure 27-4: dual fast read flash command note: when the spi core is used for flash commands, like the dual read command, the host discards the bytes received during the command, address, and dummy byte portions of the transaction. rx_data buffer full (rxbf) tx_data buffer empty (txbe) write tx_data mclk bioen tx_data read rx_data rx_data dummy byte byte 1 spdout pin spdin1 spclko spdin2 rx_data buffer full (rxbf) tx_data buffer empty (txbe) write tx_data read rx_data rx_data spclko spdout pin 7 6 spdin1 7 6 spdin2 command byte address [23:16] address byte [16:8] 5 4 3 2 1 0 7 6 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 7 6 5 4 3 2 1 0 1 0 7 6 5 4 3 2 7 6 5 4 3 2 1 0 1 0 7 6 5 4 3 2 1 0 address byte [7:0] bioen tx_data comm and address 23:16 address 15:8 address 7:0 mclk dummy byte byte 1 byte 2 byte 3 byte 4 5 3 1 6 4 2 0 7 531 6420 7 531 6420 7 531 6 420 7 byte 2 byte 3 byte 4 6 4 2 0 6 4206 4206 420 driven by master driven by slave
? 2014 - 2015 microchip technology inc. ds00001719d-page 315 MEC1322 ? the direction bit is equal to the bioen bit when data is not being shifted out (i.e., spi interface is idle). ? the hardware samples the bioen bit when it is shifting out the last bit of a byte to determine if the buffer needs to be turned around for the next byte. ? the bioen bit is also sampled any time the value in the tx_data register is loaded into the shift register to be transmitted. if a tar (turn-around time) is required between transm itting and receiving bytes on the spdout signal, software should allow all the bytes to be transmitted before changing the buffer to an input and then load the tx_data register to begin receiving bytes. if tar greater than zero is required, software must wait for the transmission in one direction to complete before writing the tx_data register to start sending/receiving in the opposite direction. this allows the spi block to operate the same as legacy microchip spi devices. 27.10.5 configuring the spi clock generator the spi controller generates the spi_clk signal to the ex ternal spi device. the frequency of the spi_clk signal is determined by one of two clock sources and the preload valu e of the clock generator dow n counter. the clock generator toggles the spi_clk output every time the counter underflows, while data is being transmitted. the clock source to the down counter is determined by bit clksrc. either the main system clock or the 2mhz clock can be used to decrement the down counter in the clock generator logic. the spi_clk frequency is determined by the following formula: the reference_clock frequency is selected by clksrc in the spi clock control register and preload is the preload field of the spi clock generator register . the frequency can be either the 48 mhz ring oscillator clock or a 2mhz clock. when the preload value is 0, the reference_clock is always the 48 mhz ring oscillator clock and the clksrc bit is ignored. sample spi clock frequencies are shown in the following table: 27.10.6 configuring spi mode in practice, there are four modes of operation that define when data should be latched. these four modes are the com- binations of the spi_clk polarity and phase. the output of the clock generator may be inverted to create an active high or active low clock pulse. this is used to determine the inactive state of the spi_clk signal and is used for determining the first edge for shifting the data. the polarity is selected by clkpol in the spi clock control register . note: when the spi interface is in the idle state and data is not being transmitted, the spi_clk signal stops in the inactive state as determined by the configuration bits. table 27-7: spi_clk frequencies clock source preload spi_clk frequency don?t care 0 48mhz 48mhz 1 24mhz 48mhz 2 12mhz (default) 48mhz 3 6mhz 48mhz 63 381khz 2mhz 1 1mhz 2mhz 2 500khz 2mhz 3 333khz 2mhz 63 15.9khz spi_clk_freq= 1 2 -- - reference_clock ?? ?? preload ? ?? ??
MEC1322 ds00001719d-page 316 ? 2014 - 2015 microchip technology inc. the phase of the clock is selected independently for receivi ng data and transmitting data. the receive phase is deter- mine by rclkph and the transmit phase is determine by tclkph in the spi clock control register. the following table summarizes the effect of clkpol, rclkph and tclkph. 27.11 spi examples 27.11.1 full duplex mo de transfer examples 27.11.1.1 read only the slave device used in this example is a maxim max1080 10 bit, 8 channel adc: ? the spi block is activated by setting the enable bit in spiar - spi enable register ? the spimode bit is de-asserted '0' to enable the spi interface in full duplex mode. ? the clkpol and tclkph bits are de-asserted '0', and rclkph is asserted '1' to match the clocking require- ments of the slave device. ? the lsbf bit is de-asserted '0' to indicate that the slave expects data in msb-first order. ? assert cs# using a gpio pin. ? write a valid command word (as specified by the slave dev ice) to the spitd - spi tx_data register with txfe asserted '1'. the spi master automatically clears the txfe bit indicating the byte has been put in the tx buffer. if the shift register is empty the tx_data byte is loaded in to the shift register and the spi master reasserts the txfe bit. once the data is in the shift register the spi master begins shifting the data value onto the spdout pin and drives the spclk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. table 27-8: spi data and clock behavior clkpol rclkph tclkph behavior 0 0 0 inactive state is low. first edge is rising edge. data is sampled on the rising edge. data is transmitted on the falling edge. data is valid before the first rising edge. 0 0 1 inactive state is low. first edge is rising edge. data is sampled on the rising edge. data is transmitted on the rising edge. 0 1 0 inactive state is low. first edge is rising edge. data is sampled on the falling edge. data is transmitted on the falling edge. data is valid before the first rising edge. 0 1 1 inactive state is low. first edge is rising edge. data is sampled on the falling edge. data is transmitted on the rising edge. 1 0 0 inactive state is high. first edge is falling edge. data is sampled on the falling edge. data is transmitted on the rising edge. data is valid before the first falling edge. 1 0 1 inactive state is high. first edge is falling edge. data is sampled on the falling edge. data is transmitted on the falling edge. 1 1 0 inactive state is high. first edge is falling edge. data is sampled on the rising edge. data is transmitted on the rising edge. data is valid before the first falling edge. 1 1 1 inactive state is high. first edge is falling edge. data is sampled on the rising edge. data is transmitted on the falling edge.
? 2014 - 2015 microchip technology inc. ds00001719d-page 317 MEC1322 ? a dummy 8 bit data value (any value) is written to the tx_data register. the spi master automatically clears the txfe bit, but does not begin shifting the dummy data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses from the first transmit bytes: - the first spi cycle is complete, rxbf bit is asserted '1', and the spint interrupt is asserted, if enabled. the data now contained in s pird - spi rx_data register is invalid sinc e the last cycle was initiated solely to transmit command data to the slave. this particular sl ave device drives '0' on the spdin pin to the master while it is accepting command data. this spird data is ignored. - once the first spi cycle is completed, the spi master takes the pending data in the tx_data register and loads it into the tx shift register. loading the shift regi ster automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spclk pin. data on the spdin pin is also sam- pled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? the final spi cycle is initiated when another dummy 8 bit data value (any va lue) is written to the tx_data regis- ter. note that this value may be another dummy value or it can be a new 8 bit command to be sent to the adc. the new command will be transmitted while the final data from the last command is received simultaneously. this overlap allows adc data to be read every 16 spclk cycles after the initia l 24 clock cycle.the spi master auto- matically clears the txfe bit, but does not begin shifting the dummy data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses, the second spi cycle is complete: - the first spi cycle is complete, rxbf bit is asserted '1', and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is the first half of a valid 16 bit adc value. spird is read and stored. - once the second spi cycle is completed, the spi master takes the pending data in the tx_data register and loads it into the tx shift register. loading the shift regi ster automatically asserts the txfe bit, begins shifting the data value onto the spdout pin, and drives the spclk pin. data on the spdin pin is also sampled on each clock. ? after 8 spi_clk pulses, the final spi cycl e is complete, txbf is asserted '1', and the spint inte rrupt is asserted (if enabled). the data now contained in spird - spi rx_data register is the second half of a valid 16 bit adc value. spird is read and stored. ? if a command was overlapped with the received data in the final cycle, #cs should remain asserted and the spi master will initiate another spi cycle. if no new co mmand was sent, #cs is rele ased and the spi is idle. 27.11.1.2 read/write the slave device used in this example is a fairchild ns 25c640 fm25c640 64k bit seri al eeprom. the following sub- sections describe the read and write sequences. read ? the spi block is activated by setting the enable bit in spiar - spi enable register ? the spimode bit is de-asserted '0' to enable the spi interface in full duplex mode. ? the clkpol, tclkph and rclkph bits are de-asserted '0' to match the clocking requirements of the slave device. ? the lsbf bit is de-asserted '0' to indicate that the slave expects data in msb-first order. ? assert cs# low using a gpio pin. ? write a valid command word (as specified by the slave dev ice) to the spitd - spi tx_data register with txfe asserted '1'. the spi master automatically clears the txfe bit indicating the byte has been put in the tx buffer. if the shift register is empty the tx_data byte is loaded into the shift register and the spi master reasserts the txfe bit. once the data is in the shift register the spi master begins shifting the data value onto the spdout pin and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, eeprom address a15-a8 is writ ten to the tx_data regi ster. the spi master au tomatically clears the txfe bit, but does not begin shifting the dummy data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty.
MEC1322 ds00001719d-page 318 ? 2014 - 2015 microchip technology inc. ? after 8 spi_clk pulses from the first transmit byte (command byte transmitted): - the first spi cycle is complete, rxbf bit is asserted '1', and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_d ata register is invalid since the last cycle was initiated solely to transmit command data to the slave. this particular sl ave device tri-states the spdin pin to the master while it is accepting command data. this spird data is ignored. - once the first spi cycle is completed, the spi mast er takes the pending data in the tx_data register (eeprom address a15-a8) and loads it into the tx shift register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. note: the particular slave device ignores address a15-a13. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, eeprom address a7-a0 is writte n to the tx_data register. the spi ma ster automatically clears the txfe bit, but does not begin shifting this data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses from the second transmit byte (address byte (msb) transmitted): - eeprom address a15-a8 has been tr ansmitted to the slave completing the second spi cycle. once again, the rxbf bit is asserted '1' and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is invalid si nce the last cycle was initiated solely to transmit address data to the slave. - once the second spi cycle is complete d, the spi master takes the pending data in the tx_data register (eeprom address a7-a0) and loads it into the tx shif t register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spclk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, a dummy byte is written to the tx_data register . the spi master automatically clears the txfe bit, but does not begin shifting this data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses, the third spi cycle is complete (address byte (lsb) transmitted): - eeprom address a7-a0 has been transm itted to the slave completing the third spi cycle. once again, the rxbf bit is asserted '1' and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is invalid since the last cycle was initiated solely to transmit address data to the slave. - once the third spi cycle is completed, the spi mast er takes the pending data in the tx_data register (dummy byte) and loads it into the tx shift register. lo ading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spclk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? if only one receive byte is required, the host would not write any more value to the tx_data register until this transaction completes. if more than one byte of data is to be received, another dummy byte would be written to the tx_data register (one dummy byte per receive byte is re quired). the spi master automatically clears the txfe bit when the tx_data register is written, but does not begin shifting this data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses, the fourth spi cycle is complete (first data byte received): - the dummy byte has been transmitted to the slave completing t he fourth spi cycle. once again, the rxbf bit is asserted '1' and the spint interrupt is asserted, if enabled. unlike the command and address phases, the data now contained in spird - spi rx_d ata register is the 8-bit eeprom data since the last cycle was ini- tiated to receive data from the slave. - once the fourth spi cycle is complete d, the spi master take s the pending data in th e tx_data register (if any) and loads it into the tx shift register. this proces s will be repeated until all the desired data is received. ? the host software will read and store the eeprom data value in spird - spi rx_data register. note: external pull-up or pull-down is required on the spdi n pin if it is tri-stated by the slave device.
? 2014 - 2015 microchip technology inc. ds00001719d-page 319 MEC1322 ? if no more data needs to be received by the master, cs# is released and the spi is idle. otherwise, master contin- ues reading the data by writing a dummy value to the tx_data register after every 8 spi_clk cycles. write ? the spi block is activated by setting the enable bit in spiar - spi enable register ? the spimode bit is de-asserted '0' to enable the spi interface in full duplex mode. ? the clkpol, tclkph and rclkph bits are de-asserted '0' to match the clocking requirements of the slave device. ? the lsbf bit is de-asserted '0' to indicate that the slave expects data in msb-first order. ? assert wr# high using a gpio pin. ? assert cs# low using a gpio pin. ? write a valid command word (as specified by the slave dev ice) to the spitd - spi tx_data register with txfe asserted '1'. the spi master automatically clears the txfe bit indicating the byte has been put in the tx buffer. if the shift register is empty the tx_data byte is loaded into the shift register and the spi master reasserts the txfe bit. once the data is in the shift register the spi master begins shifting the data value onto the spdout pin and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, eeprom address a15-a8 is writ ten to the tx_data regi ster. the spi master au tomatically clears the txfe bit, but does not begin shifting the dummy data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses from the first transmit byte (command byte transmitted): - the first spi cycle is complete, rxbf bit is asserted '1', and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_d ata register is invalid since the last cycle was initiated solely to transmit command data to the slave. this particular sl ave device tri-states the spdin pin to the master while it is accepting command data. this spird data is ignored. user?s note: external pull-up or pull-down is required on the spdin pin if it is tri-stated by the slave device. - once the first spi cycle is completed, the spi mast er takes the pending data in the tx_data register (eeprom address a15-a8) and loads it into the tx shift register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. note: the particular slave device ignores address a15-a13. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, eeprom address a7-a0 is writte n to the tx_data register. the spi ma ster automatically clears the txfe bit, but does not begin shifting this data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses from the second transmit byte (address byte (msb) transmitted): - eeprom address a15-a8 has been tr ansmitted to the slave completing the second spi cycle. once again, the rxbf bit is asserted '1' and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is invalid si nce the last cycle was initiated solely to transmit address data to the slave. - once the second spi cycle is complete d, the spi master takes the pending data in the tx_data register (eeprom address a7-a0) and loads it into the tx shif t register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spclk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, a data byte (d7:d0) is written to the tx_data register. the spi master automatically clears the txfe bit, but does not begin shifting this data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses, the third spi cycle is complete (address byte (lsb) transmitted): - eeprom address a7-a0 has be en transmitted to the slave completing the third spi cycle. once again, the rxbf bit is asserted '1' and the spint interrupt is asserted, if enabled. the data now contained in spird -
MEC1322 ds00001719d-page 320 ? 2014 - 2015 microchip technology inc. spi rx_data register is invalid since the last cycle was initiated solely to transmit address data to the slave. - once the third spi cycle is complet ed, the spi master takes the pending data in the tx_data register (data byte d7:d0) and loads it into the tx shift register. lo ading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spclk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? if only one data byte is to be written, the host would not write any more values to the tx_data register until this transaction completes. if more than one byte of data is to be written, another data byte would be written to the tx_data register. the spi master automatically clears t he txfe bit when the tx_data register is written, but does not begin shifting this data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses, the fourth spi cycle is complete (first da ta byte transmitted): - the data byte has been transmitted to the slave completing the fourth spi cycle. once ag ain, the rxbf bit is asserted '1' and the spint interrupt is asserted, if enabled. like the command and address phases, the data now contained in spird - spi rx_data register is invalid since the last cycle was initiated to transmit data to the slave. - once the fourth spi cycle is complete d, the spi master take s the pending data in th e tx_data register (if any) and loads it into the tx shift register. this proces s will be repeated until all the desired data is transmit- ted. ? if no more data needs to be transmitted by the master, cs# and wr# are released and the spi is idle. 27.11.2 half duplex (bidirectional mode) transfer example the slave device used in this example is a natio nal lm74 12 bit (plus sign) temperature sensor. ? the spi block is activated by setting the enable bit in spiar - spi enable register ? the spimode bit is asserted '1' to enable the spi interface in half duplex mode. ? the clkpol, tclkph and rclkph bits are de-asserted '0' to match the clocking requirements of the slave device. ? the lsbf bit is de-asserted '0' to indicate that the slave expects data in msb-first order. ? bioen is asserted '0' to indicate that the first data in the transaction is to be received from the slave. ? assert cs# using a gpio pin. //receive 16-bit temperature reading ? write a dummy command byte (as specified by the slave device) to the spitd - spi tx_data register with txfe asserted '1'. the spi master automatically clears the txfe bit indicating the byte has been put in the tx buffer. if the shift register is empty the tx_data byte is loaded in to the shift register and the spi master reasserts the txfe bit. once the data is in the shift register the spi master begins shifting the data value onto the spdout pin and drives the spi_clk pin. this data is lost because t he output buffer is disabled. data on the spdin pin is sam- pled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, another dummy byte is written to the tx_data regi ster. the spi master automatically clears the txfe bit, but does not begin shifting the dummy data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses from the first receive byte - the first spi cycle is complete, rxbf bit is asserted '1', and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is the first half of the 16 bit word containing the tem- perature data. - once the first spi cycle is completed, the spi mast er takes the pending data in the tx_data register (dummy byte 2) and loads it into the tx shift register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. //transmit next reading command
? 2014 - 2015 microchip technology inc. ds00001719d-page 321 MEC1322 ? bioen is asserted '1' to indicate that data will now be driven by the master. ? next, a command byte is written to the tx_data register. this value is the first half of a 16 bit command to be sent to temperature sensor peripheral. the spi master automatically clears the txfe bit, but does not begin shift- ing the command data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. this data will be transmitted because the output buffer is enabled. data on the spdin pin is sampled on each clock. ? after 8 spi_clk pulses from the second receive byte: - the second spi cycle is complete, rxbf bit is assert ed '1', and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is the second half of the 16 bit word containing the temperature data. - once the first spi cycle is completed, the spi master takes the pending data in the tx_data register (com- mand byte 1) and loads it into the tx shift register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? next, the second command byte is written to the tx _data register. the spi master automatically clears the txfe bit, but does not begin shifting the command data value onto the spdout pin. this byte will remain in the tx_data register until the tx shift register is empty. ? after 8 spi_clk pulses from the first transmit byte: - the third spi cycle is complete, rxbf bit is asserted '1 ', and the spint interrupt is asserted, if enabled. the data now contained in spird - spi rx_data register is invalid, since this command was used to transmit the first command byte to the spi slave. - once the first spi cycle is completed, the spi master takes the pending data in the tx_data register (com- mand byte 2) and loads it into the tx shift register. loading the shift register automatically asserts the txfe bit, begins shifting the dummy data value onto the spdout pin, and drives the spi_clk pin. data on the spdin pin is also sampled on each clock. ? once the txfe bit is asserted the spi master is ready to transmit or receive its next byte. before writing the next tx_data value, software must clear the rxbf status bit by reading the spird - spi rx_data register. ? since no more data needs to be transmitted, the host software will wait for the rxbf status bit to be asserted indi- cating the second command byte was transmitted successfully. ? cs# is de-asserted. 27.12 ec-only registers the registers listed in the ec-only register summary tabl e are for a single instance of the general purpose serial peripheral interface. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. table 27-9: ec-only register base address table block instance instance number host address space base address general purpose serial peripheral interface (gp-spi) 0 ec 32-bit internal address space 4000_9400h 1 ec 32-bit internal address space 4000_9480h note: the shared spi controller is instance 0 and the priv ate spi is instance 1 of the general purpose serial peripheral interface (gp-spi) block.
MEC1322 ds00001719d-page 322 ? 2014 - 2015 microchip technology inc. 27.12.1 spi enable register 27.12.2 spi control register table 27-10: ec-only register summary offset register name 0h spi enable register 4h spi control register 8h spi status register ch spi tx_data register 10h spi rx_data register 14h spi clock control register 18h spi clock generator register offset 00h bits description type default reset event 31:1 reserved r - - 0 enable 1=enabled. the device is fully operational 0=disabled. clocks are gated to conserve power and the spdout and spi_clk signals are set to their inactive state r/w 0h vcc1_r eset offset 00h bits description type default reset event 31:7 reserved r - - 6ce spi chip select enable. 1= spi_cs# output signal is asserted, i.e., driven to logic ?0? 0= spi_cs# output signal is deasserted, i.e., driven to logic ?1? r/w 0h vcc1_r eset 5 auto_read auto read enable. 1=a read of the spi rx_data regist er will clear both the rxbf sta- tus bit and the txbe status bit 0=a read of the spi rx_data register will clear the rxbf status bit. the txbe status bit will not be modified r/w 0h vcc1_r eset 4 soft_reset soft reset is a self-clearing bit. writing zero to this bit has no effect. writing a one to this bit resets the entire spi interface, including all counters and registers back to their initial state. r/w 0h vcc1_r eset 3:2 spdin_select the spdin select which spi input signals are enabled when the bioen bit is configured as an input. 1xb=spdin1 and spdin2. select this option for dual mode 01b=spdin2 only. select this option for half duplex 00b=spdin1 only. select this option for full duplex r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 323 MEC1322 27.12.3 spi status register 1bioen bidirectional output enable control. when the spi is configured for half duplex mode or dual mode the spdout pin operates as a bi- directional signal. the bioen bit is used by the internal direction bit to control the direction of the spdout buffers. the direction of the buffer is never changed while a byte is being transmitted. 1=the spdout_direction signal configures the spdout signal as an output. 0=the spdout_direction signal configures the spdout signal as an input. see section 27.10.4, "how bioen bit controls direction of spd- out buffer" for details on the use of bioen. r/w 1h vcc1_r eset 0 lsbf least significant bit first 1= the data is transferred in lsb-first order. 0= the data is transferred in msb-first order. (default) r/w 0h vcc1_r eset offset 08h bits description type default reset event 31:3 reserved r - - 2active r 0h vcc1_r eset 1 rxbf receive data buffer full status. when this bit is ?1? the rx_data buf- fer is full. reading the spi rx_data register clears this bit. this sig- nal may be used to generate a spi_rx interrupt to the ec. 1=rx_data buffer is full 0=rx_data buffer is not full r 0h vcc1_r eset 0 txbe transmit data buffer empty status. when this bit is ?1? the tx_data buffer is empty. writing the spi tx_data register clears this bit. this signal may be used to generate a spi_tx interrupt to the ec. 1=tx_data buffer is empty 0=tx_data buffer is not empty r 1h vcc1_r eset offset 00h bits description type default reset event
MEC1322 ds00001719d-page 324 ? 2014 - 2015 microchip technology inc. 27.12.4 spi tx_data register 27.12.5 spi rx_data register offset 00h bits description type default reset event 31:8 reserved r - - 7:0 tx_data a write to this register when t he tx_data buffer is empty (txbe in the spi status register is ?1?) initiates a spi transaction. the byte written to this register will be loaded into the shift register and the txbe flag will be asserted. this in dicates that the next byte can be written into the tx_data register. this byte will remain in the tx_- data register until the spi core has finished shifting out the previ- ous byte. once the shift register is empty, the hardware will load the pending byte into the shift register and once again assert the txbe bit. the tx_data register must not be written when the txbe bit is zero. writing this register may overwr ite the transmit data before it is loaded into the shift register. r/w 0h vcc1_r eset offset 00h bits description type default reset event 31:8 reserved r - - 7:0 rx_data this register is used to read the value returned by the external spi device. at the end of a byte transfer the rx_data register contains serial input data (valid or not) from the last transaction and the rxbf bit is set to one. this status bit indicates that the rx_data register has been loaded with a the serial input data. the rx_data register should not be read before the rxbf bit is set. the rx_data register must be read, clearing the rxbf status bit before writing the tx_data register. the data in the receive shift register is only loaded into the rx _data register when this bit is cleared. if a data byte is pending in the receive shift register the value will be loaded immediately into the rx_data register and the rxbf status flag will be asserted. software should read the rx_- data register twice before starting a new transaction to make sure the rx_data buffer and shift register are both empty. r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 325 MEC1322 27.12.6 spi clock control register this register should not be changed during an active spi transaction. offset 00h bits description type default reset event 31:5 reserved r - - 4 clksrc clock source for the spi clock generator. this bit should not be changed during a spi transaction. when the field preload in the spi clock generator register is 0, this bit is ignored and the clock source is always the main system clock (the equivalent of setting this bit to ?0?). 1= 2mhz 0= 48 mhz ring oscillator r/w 0h vcc1_r eset 3 reserved r - - 2 clkpol spi clock polarity. 1=the spi_clk signal is high when the interface is idle and the first clock edge is a falling edge 0=the spi_clk is low when the interface is idle and the first clock edge is a rising edge r/w 0h vcc1_r eset 1 rclkph receive clock phase, the spi_clk edge on which the master will sample data. the receive clock phase is not affected by the spi clock polarity. 1=valid data on spdin signal is expected after the first spi_clk edge. this data is sampled on the second and following even spi_clk edges (i.e., sample data on falling edge) 0=valid data is expected on the spdin signal on the first spi_clk edge. this data is sampled on the first and following odd spi_- clk edges (i.e., sample data on rising edge) r/w 1h vcc1_r eset 0 tclkph transmit clock phase, the spclk edge on which the master will clock data out. the transmit clock phase is not affected by the spi clock polarity. 1=valid data is clocked out on the first spi_clk edge on spdout signal. the slave device should sample this data on the second and following even spi_clk edges (i.e., sample data on falling edge) 0=valid data is clocked out on the spdout signal prior to the first spi_clk edge. the slave device should sample this data on the first and following odd spi_clk edges (i.e., sample data on ris- ing edge) r/w 0h vcc1_r eset
MEC1322 ds00001719d-page 326 ? 2014 - 2015 microchip technology inc. 27.12.7 spi clock generator register offset 00h bits description type default reset event 31:16 reserved r - - 5:0 preload spi clock generator preload value. r/w 2h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 327 MEC1322 28.0 blinking/breathing pwm 28.1 introduction leds are used in computer applications to communicate intern al state information to a user through a minimal interface. typical applications will cause an led to bl ink at different rates to convey differ ent state information. for example, an led could be full on, full off, blinking at a rate of once a second, or blinking at a rate of once every four seconds, in order to communicate four different states. as an alternative to blinking, an led can ?breathe?, that is, oscillate between a bright state and a dim state in a contin- uous, or apparently continuous manner. the rate of breathing, or the level of brightness at the extremes of the oscillation period, can be used to convey state information to the user th at may be more informative, or at least more novel, than traditional blinking. the blinking/breathing hardware is implemented us ing a pwm. the pwm can be driven either by the 48 mhz clock or by a 32.768 khz clock input. when driven by the 48 mhz clock , the pwm can be used as a standard 8-bit pwm in order to control a fan. when used to drive blinking or breathing leds, the 32.768 khz clock source is used. features: ? each pwm independently configurable ? each pwm configurable for led blinking and breathing output ? highly configurable breathing rate from 60ms to 1min ? non-linear brightness curves approximated with 8 piece wise-linear segments ? all led pwms can be synchronized ? each pwm configurable for 8-bit pwm support ? multiple clock rates ? configurable watchdog timer 28.2 interface this block is designed to drive a pin on the pin interface and to be accessed internally via a registered host interface. figure 28-1: i/o diagram of block blinking/breathing pwm signal description clock inputs interrupts resets host interface
MEC1322 ds00001719d-page 328 ? 2014 - 2015 microchip technology inc. 28.3 signal description 28.4 host interface the blinking/breathing pwm block is accessed by a controller over the stan dard register interface. 28.5 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 28.5.1 power domains 28.5.2 clock inputs 28.5.3 resets 28.6 interrupts each pwm can generate an interrupt. the interrupt is asserted for one 48 mhz clock period whenever the pwm wdt times out. the pwm wdt is described in section 28.8.3.1, "pwm wdt," on page 332 . table 28-1: signal description name direction description pwm output output output of pwm by default, the pwm pin is configured to be active high: when the pwm is configured to be fully on, the pin is driving high. when the pwm is configured to be fully off, the pin is low. if firmware requires the blinking/breathing pwm to be active low, the polarity bit in the gpio pin control register associated with the pwm can be set to 1, which inverts the output polarity. table 28-2: power sources name description vcc1 main power. the source of main power for the device is system dependent. table 28-3: clock inputs name description 32khz_clk 32.768 khz clock 48 mhz ring oscillator 48 mhz clock table 28-4: reset signals name description vcc1_reset block reset note: pwm_wdt[0] , pwm_wdt[1] , pwm_wdt[2] , pwm_wdt[3] bits in the girq17 and girq18 registers are the interrupt source bits for the three instances of the blinking/breathing pwm in the MEC1322. table 28-5: ec interrupts source description pwm_wdt pwm watchdog time out
? 2014 - 2015 microchip technology inc. ds00001719d-page 329 MEC1322 28.7 low power mode the blinking/breathing pwm may be put into a low power mode by the chip-level power, clocks, and reset (pcr) circuitry. the low power mode is only applicable when the blinking/breathing pwm is operating in the general pur- pose pwm mode. when the low speed clock mode is selected, the blinking/breathing function continues to operate, even when the 48 mhz clock is stopped. low power mode behavior is summarized in the following table: 28.8 description 28.8.1 breathing if an led blinks rapidly enough, the eye will interpret the lig ht as reduced brightness, rather than a blinking pattern. therefore, if the blinking period is short enough, modifying the duty cycle will set the apparent brightness, rather than a blinking rate. at a blinking rate of 128hz or greater, almost all people will perceive a continuous light source rather than an intermittent pattern. because making an led appear to breathe is an aesthetic effect, the breathing mechanism must be adjustable or cus- tomers may find the breathing effect unattractive. there ar e several variables that can affect breathing appearance, as described below. the following figure illustrates some of the variables in breathing: figure 28-2: breathing led example table 28-6: low power mode behavior clock_s ource control mode low power mode description x ?00?b pwm ?off? yes 32.768 khz clock is required. x ?01?b breathing yes 1 ?10?b general purpose pwm no 48 mhz clock is required, even when a sleep com- mand to the block is asserted. 0 ?10?b blinking yes 32.768 khz clock is required. x ?11?b pwm ?on? yes note: in order for the mec 1322 to enter its.h eavy and deep sleep st ates, the sleep_enable input for all blink- ing/breathing pwm instances must be asserted, even if the pwms are configured to use the low speed clock. full off full on rising ramp time falling ramp time min duty cycle max duty cycle
MEC1322 ds00001719d-page 330 ? 2014 - 2015 microchip technology inc. the breathing range of and led can range between full on and fu ll off, or in a range that falls within the full-on/full-off range, as shown in this figure. the ramp time can be differ ent in different applications. for example, if the ramp time was 1 second, the led would appear to breathe quickly. a time of 2 seconds would make the led appear to breathe more leisurely. the breathing pattern can be clipped, as shown in the followin g figure, so that the breathing effect appears to pause at its maximum and minimum brightnesses: figure 28-3: clipping example the clipping periods at the two extremes can be adjusted independently, so that for example an led can appear to breathe (with a short delay at maximum brightness) followed by a longer ?resting? period (with a long delay at minimum brightness). the brightness can also be changed in a non-li near fashion, as shown in the following figure: figure 28-4: example of a segmented curve in this figure, the rise and fall curves are implemented in 4 linear segments and are the rise and fall periods are sym- metric. the breathing mode uses the 32.768 khz clock for its time base. full off full on min duty cycle max duty cycle full off full on
? 2014 - 2015 microchip technology inc. ds00001719d-page 331 MEC1322 28.8.2 blinking when configured for blinking, a subset of the hardware used in breathing is used to implement the blinking function. the pwm (an 8-bit accumulator plus an 8-bit duty cycle register) drives the led directly. the duty cycle register is pro- grammed directly by the user, and not modified further. the pw m accumulator is configured as a simple 8-bit up counter. the counter uses the 32.768 khz clock , and is pre-scaled by the delay counter, to slow the pwm down from the 128hz provided by directly running the pwm on the 32.768 khz clock . with the pre-scaler, the blink rate of the led could be as fast as 128hz (which, because it is blinking faster than the eye can distinguish, would appear as a continuous level) to 0. 03125hz (that is, with a period of 7.8ms to 32 seconds). any duty cycle from 0% (0h) to 100% (ffh) ca n be configured, with an 8-bit precisi on. an led with a duty cycle value of 0h will be fully off, while an led with a duty cycle value of ffh will be fully on. in blinking mode the pwm counter is always in 8-bit mode. table 28-7, "led blink configuration examples" shows some example blinking configurations: the blinking and general purpose pwm modes share the hardw are used in the breathing mode. the prescale value is derived from the ld field of the led_delay register and the duty cycle is derived from the min field of the led_lim- its register. 28.8.3 general purpose pwm when used in the blinking configuration with the 48 mhz ring oscillator , the led module can be used as a general- purpose programmable pulse-width modulat or with an 8-bit programmable pulse width. it can be used for fan speed control, sound volume, etc. with the 48 mhz ring oscillator source, the pwm frequency can be configured in the range shown in ta b l e 2 8 - 9 . table 28-7: led blink configuration examples prescale duty cycle blink frequency blink 000h 00h 128hz full off 000h ffh 128hz full on 001h 40h 64hz 3.9ms on, 11.6ms off 003h 80h 32hz 15.5ms on, 15.5ms off 07fh 20h 1hz 125ms on, 0.875s off 0bfh 16h 0.66hz 125ms on, 1.375s off 0ffh 10h 0.5hz 125ms on, 1.875s off 180h 0bh 0.33hz 125ms on, 2.875s off 1ffh 40h 0.25hz 1s on, 3s off table 28-8: blinking mode calculations parameter unit equation frequency hz ( 32khz_clk frequency) /(prescale + 1)/255 ?h? width seconds (1/period) x (dutycycle/255) ?l? width seconds (1/period) x (255 - dutycycle) table 28-9: pwm configuration examples prescale pwm frequency 000h 187.5 khz 001h 93.75 khz 003h 46.875 khz 006h 26.8 khz 00bh 15.625 khz 07fh 1.46 khz 1ffh 366 hz fffh 46 hz
MEC1322 ds00001719d-page 332 ? 2014 - 2015 microchip technology inc. 28.8.3.1 pwm wdt when the pwm is configured as a general-purpose pwm (in the blinking configuration with the 48 mhz clock ), the pwm includes a watch dog timer (wdt). the wdt consists of an internal 8-bit counter and an 8-bit reload value (the field wdtld in led configuration register register). the internal counter is loaded with the reset value of wdtld (14h, or 4 seconds) on system vcc1_reset and loaded with the contents of wdtld whenever either the led configuration register register is written or the min byte in the led limits register register is written (the min byte controls the duty cycle of the pwm). whenever the internal counter is non-zero, it is decremented by 1 for every tick of the 5 hz clock. if the counter decre- ments from 1 to 0, a wdt terminal count causes an interrupt to be generated and reset sets the control bit in the led configuration register to 3h, which forces the pwm to be full on. no other pwm registers or fields are affected. if the 5 hz clock halts, the watchdog timer stops decrementing but retains its value, provided the device continues to be powered. when the 5 hz clock restarts, the watchdog counter will continue decrementing where it left off. setting the wdtld bits to 0 disables the pwm wdt. other sample values for wdtld are: 01h = 200 ms 02h = 400 ms 03h = 600 ms 04h = 800 ms ? 14h = 4seconds ffh = 51 seconds 28.9 implementation in addition to the registers described in section 28.10, "ec-only registers" , the pwm is implemented using a number of components that are interconnected differently when configured for breathing operation and when configured for blinking/pwm operation. 28.9.1 breathing configuration the psize parameter can configure the pwm to one of three modes: 8-bit, 7-bit and 6-bit. the period ctr counts ticks of its input clock. in 8-bit mode, it counts from 0 to 255 (that is, 256 steps), then repeats continuously. in this mode, a full cycle takes 7.8ms (128hz). in 7-bit mode it counts from 0 to 127 (128 steps), and a full cycle takes 3.9ms (256hz). in 6-bit mode it counts from 0 to 63 (64 steps) and a full cycle takes 1.95ms (512hz). the output of the led circuit is asserted whenever the period ctr is less than the contents of the duty cycle register. the appearance of breathing is cr eated by modifying the contents of the duty cycle register in a continuous manner. when the led control is off the internal counters and registers are all reset to 0 (i.e. after a write setting the reset bit in the led configuration register register.) once enabled, the duty cycle register is increased by an amount determined by the led_step regi ster and at a rate determined by the delay counter. once the duty cycle reaches its maximum value (det ermined by the field max), the duty cycle is held constant for a period determined by the field hd. once the hold time is complete, the duty cycle register is decreased, again by an amount determined by the led_step register and at a rate determined by the delay counter. when the duty cycl e then falls at or below the minimum value (determined by the field min), the duty cycle is held constant for a period determined by the field hd. once the hold time is complete , the cycle repeats, with the duty cycle oscillating between min and max. the rising and falling ramp times as shown in figure 28-3: clipping example on page 330 can be either symmetric or asymmetric depending on the setting of the symmetry bit in the led configuration register register. in symmetric mode the rising and falling ramp rates have mirror symmetry; both rising and falling ramp rates use the same (all) 8 table 28-10: general purpose pwm mode calculations parameter unit equation frequency hz ( 48 mhz ring oscillator frequency) / (prescale + 1) / 255 ?h? width seconds (1/period) x (dutycycle/255) ?l? width seconds (1/period) x (255 - dutycycle)
? 2014 - 2015 microchip technology inc. ds00001719d-page 333 MEC1322 segments fields in each of the following registers (see table 28-11 ): the led update stepsize register register and the led update interval register register. in asymmetric mode the rising ramp rate uses 4 of the 8 segments fields and the falling ramp rate uses the remainin g 4 of the 8 segments fields (see table 28-11 ). the parameters min, max, hd, ld and the 8 fields in led_step and led_int determine the brightness range of the led and the rate at which its brightness changes. see the descriptions of the fields in section 28.10, "ec-only regis- ters" , as well as the examples in section 28.9.3, "breathing examples" for information on how to set these fields. 28.9.2 blinking configuration the delay counter and the pwm counter are the same as in the breathing configuration, except in this configuration they are connected differently. the de lay counter is clocked on either the 32.768 khz clock or the 48 mhz clock , rather than the output of the pwm. the pwm counter is clocked by the zero output of the delay counter, which functions as a prescalar for the input clocks to the pwm. the delay counter is reloaded from the ld field of the led_delay register. when the ld field is 0 the input clock is passed directly to the pwm counter without prescaling. in blinking/pwm mode the pwm counter is always 8-bit, and the psize parameter has no effect. the frequency of the pwm pulse waveform is determined by the formula: where f pwm is the frequency of the pwm, f clock is the frequency of the input clock ( 32.768 khz clock or 48 mhz clock ) and ld is the contents of the ld field. table 28-11: symmetric breathing mode register usage rising/ falling ramp times in figure 28-3, "clipping example" duty cycle segment index symmetric mode register fields utilized x 000xxxxxb 000b step[0 ]/int[0] bits[3:0] x 001xxxxxb 001b step[1 ]/int[1] bits[7:4] x 010xxxxxb 010b step[2]/int[2] bits[11:8] x 011xxxxxb 011b step[3]/int[3] bits[15:12] x 100xxxxxb 100b step[4]/int[4] bits[19:16] x 101xxxxxb 101b step[5]/int[5] bits[23:20] x 110xxxxxb 110b step[6]/int[6] bits[27:24] x 111xxxxxb 111b step[7]/int[7] bits[31:28] note: in symmetric mode the segment_index[2:0] = duty cycle bits[7:5] table 28-12: asymmetric brea thing mode register usage rising/ falling ramp times in figure 28-3, "clipping example" duty cycle segment index asymmetric mode register fields utilized rising 00xxxxxxb 000b step[ 0]/int[0] bits[3:0] rising 01xxxxxxb 001b step[ 1]/int[1] bits[7:4] rising 10xxxxxxb 010b step[2]/int[2] bits[11:8] rising 11xxxxxxb 011b step[3]/int[3] bits[15:12] falling 00xxxxxxb 100b step[ 4]/int[4] bits[19:16] falling 01xxxxxxb 101b step[ 5]/int[5] bits[23:20] falling 10xxxxxxb 110b step[ 6]/int[6] bits[27:24] falling 11xxxxxxb 111b step[ 7]/int[7] bits[31:28] note: in asymmetric mode the segment_index[2:0] is the bit concatenation of following: segment_index[2] = ( falling ramp time in figure 28-3, "clipping example") and segment_index[1:0] = duty cycle bits[7:6]. f pwm f clock 256 ld 1 + () () ----------------------------------------- - =
MEC1322 ds00001719d-page 334 ? 2014 - 2015 microchip technology inc. the other registers in the block do not affect the pwm or the led output in blinking/pwm mode. 28.9.3 breathing examples 28.9.3.1 linear led brightness change in this example, the brightness of th e led increases and diminishes in a linear fashion. the entire cycle takes 5 sec- onds. the rise time and fall time are 1.6 seconds, with a hold time at maximum brightness of 200ms and a hold time at minimum brightness of 1.6 seconds. the led brightness varies between full off and full on. the pwm size is set to 8- bit, so the time unit for adjusting the pwm is approxi mately 8ms. the registers are configured as follows: note: at a duty cycle value of 00h (in the min register), the led ou tput is fully off. at a duty cycle value of 255h, the led output is fully on. alternatively, in order to force the led to be fully on, firmware can set the con- trol field of the configuration register to 3 (always on). table 28-13: linear example configuration field value psize 8-bit max 255 min 0 hd 25 ticks (200ms) ld 200 ticks (1.6s) duty cycle most significant bits 000b 001b 010b 011b 100b 101b 110b 1110 led_int 88888888 led_step 10 10 10 10 10 10 10 10
? 2014 - 2015 microchip technology inc. ds00001719d-page 335 MEC1322 figure 28-5: linear brightness curve example 28.9.3.2 non-linear led brightness change in this example, the brightness of the led increases and diminishes in a non-linear fashion. the brightness forms a curve that is approximated by four piece wise-linear line segments. the entir e cycle takes about 2.8 seconds. the rise time and fall time are about 1 second, with a hold time at maximum brightness of 320ms and a hold time at minimum brightness of 400ms. the led brightness varies between full of f and full on. the pwm size is set to 7-bit, so the time unit for adjusting the pwm is approximately 4m s. the registers are configured as follows: table 28-14: non-linear example configuration field value psize 7-bit max 255 (effectively 127) min 0 hd 80 ticks (320ms) ld 100 ticks (400ms) duty cycle most significant bits 000b 001b 010b 011b 100b 101b 110b 1110 led_int 2366991616 led_step 44444444 0 50 100 150 200 250 300 0 3 2 0 6 4 0 9 6 0 1 2 8 0 1 6 0 0 1 9 2 0 2 2 4 0 2 5 6 0 2 8 8 0 3 2 0 0 3 5 2 0 3 8 4 0 4 1 6 0 4 4 8 0 4 8 0 0 5 1 2 0 5 4 4 0 5 7 6 0 6 0 8 0 6 4 0 0 6 7 2 0 7 0 4 0 7 3 6 0 7 6 8 0 8 0 0 0 8 3 2 0 8 6 4 0 8 9 6 0 9 2 8 0 9 6 0 0 9 9 2 0 1 0 2 4 0 1 0 5 6 0 1 0 8 8 0 d u t y c y c l e time in ms
MEC1322 ds00001719d-page 336 ? 2014 - 2015 microchip technology inc. the resulting curve is shown in the following figure: figure 28-6: non-linear brightness curve example 28.10 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the blinking/breathing pwm . the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. table 28-15: ec-only register base address table block instance instance number host address space base address blinking/breathing pwm 0 ec 32-bit internal address space 4000_b800h blinking/breathing pwm 1 ec 32-bit internal address space 4000_b900h blinking/breathing pwm 2 ec 32-bit internal address space 4000_ba00h blinking/breathing pwm 3 ec 32-bit internal address space 4000_bb00h 0 50 100 150 200 250 300 0 1 6 0 3 2 0 4 8 0 6 4 0 8 0 0 9 6 0 1 1 2 0 1 2 8 0 1 4 4 0 1 6 0 0 1 7 6 0 1 9 2 0 2 0 8 0 2 2 4 0 2 4 0 0 2 5 6 0 2 7 2 0 2 8 8 0 3 0 4 0 3 2 0 0 3 3 6 0 3 5 2 0 3 6 8 0 3 8 4 0 4 0 0 0 4 1 6 0 4 3 2 0 4 4 8 0 4 6 4 0 4 8 0 0 4 9 6 0 5 1 2 0 5 2 8 0 5 4 4 0 d u t y c y c l e time in ms
? 2014 - 2015 microchip technology inc. ds00001719d-page 337 MEC1322 in the following register definitions, a ?pwm period? is de fined by time the pwm counter goes from 000h to its maximum value (ffh in 8-bit mode, feh in 7-bit mode and fch in 6-bit mode, as defined by the pscale field in register led_cfg). the end of a pwm period occurs when th e pwm counter wraps from its maximum value to 0. the registers in this block can be written 32-bits, 16-bits or 8-bits at a time. writes to led configuration register take effect immediately. writes to led limits register are held in a holding register and only take effect only at the end of a pwm period. the update takes place at the end of every period, even if only one byte of the register was updated. this means that in blink/pwm mode, software can change the duty cycle with a single 8-bit write to the min field in the led_limit register. writes to led delay register , led update stepsize register and led update interval register also go initially into a holding register. the holding register s are copied to the operating registers at the end of a pwm period only if the enable update bit in the led configuration register is set to 1. if led_cfg is 0, data in the holding registers is retained but not copied to the operating regi sters when the pwm period expires. to change an led breath- ing configuration, software should write these three regist ers with the desired values and then set led_cfg to 1. this mechanism ensures that all parameters affecting led breath ing will be updated consistently, even if the registers are only written 8 bits at a time. 28.10.1 led configuration register table 28-16: ec-onl y register summary offset register name (mnemonic) 00h led configuration register 04h led limits register 08h led delay register 0ch led update stepsize register 10h led update interval register offset 00h bits description type default reset event 31:16 reserved r - - 16 symmetry 1=the rising and falling ramp times are in asymmetric mode. table 28-12, "asymmetric breathing mode register usage" shows the application of the stepsize and interval registers to the four segments of rising duty cycle s and the four segments of fall- ing duty cycles. 0=the rising and falling ramp times (as shown in figure 28-2, "breath- ing led example") are in symmetric mode. table 28-11, "sym- metric breathing mode register usage" shows the application of the stepsize and interval registers to the 8 segments of both ris- ing and falling duty cycles. r/w 0b vcc1_ reset 15:8 wdt_reload the pwm watchdog timer counter relo ad value. on system reset, it defaults to 14h, which corresponds to a 4 second watchdog timeout value. r/w 14h vcc1_ reset 7 reset writes of?1? to this bit resets the pwm registers to their default val- ues. this bit is self clearing. writes of ?0? to this bit have no effect. w0b vcc1_ reset
MEC1322 ds00001719d-page 338 ? 2014 - 2015 microchip technology inc. 28.10.2 led limits register this register may be written at any time. values written into the register are held in an holding register, which is trans- ferred into the actual register at the end of a pwm peri od. the two byte fields may be written independently. reads of this register return the current contents and not the value of the holding register. 6 enable_update this bit is set to 1 when written with a ?1?. writes of ?0? have no effect. hardware clears this bit to 0 when the breathing configuration regis- ters are updated at the end of a pwm period. the current state of the bit is readable any time. this bit is used to enable consistent configuration of led_delay, led_step and led_int. as long as this bit is 0, data written to those three registers is retained in a holding register. when this bit is 1, data in the holding register are copied to the operating registers at the end of a pwm period. when the copy completes, hardware clears this bit to 0. r/ws 0b vcc1_ reset 5:4 pwm_size this bit controls the behavior of pwm: 3=reserved 2=pwm is configured as a 6-bit pwm 1=pwm is configured as a 7-bit pwm 0=pwm is configured as an 8-bit pwm r/w 0b vcc1_ reset 3 synchronize when this bit is ?1?, all counters for all leds are reset to their initial values. when this bit is ?0? in the led configuration register for all leds, then all counters for leds that are configured to blink or breathe will increment or decrement, as required. to synchronize blinking or breathing, the synchronize bit should be set for at least one led, the control registers for each led should be set to their required values, then the synchronize bits should all be cleared. if the all leds are set for the same blink period, they will all be synchronized. r/w 0b vcc1_ reset 2 clock_source this bit controls the base clock for the pwm. it is only valid when cntrl is set to blink (2). 1=clock source is the 48 mhz clock 0=clock source is the 32.768 khz clock r/w 0b vcc1_ reset 1:0 control this bit controls the behavior of pwm: 3=pwm is always on 2=led blinking (standard pwm) 1=led breathing configuration 0=pwm is always off. all internal registers and counters are reset to 0. clocks are gated r/w 00b vcc1_ reset 11b wdt tc offset 00h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 339 MEC1322 28.10.3 led delay register this register may be written at any time. values written into the register are held in an holding register, which is trans- ferred into the actual register at the end of a pwm period if the enable update bit in the led configuration register is set to 1. reads of this register return the current contents and not the value of the holding register. offset 04h bits description type default reset event 31:16 reserved r - - 15:8 maximum in breathing mode, when the current duty cycle is greater than or equal to this value the breathing apparatus holds the current duty cycle for the period specified by the field hd in register led_delay, then starts decrementing the current duty cycle r/w 0h vcc1_ reset 7:0 minimum in breathing mode, when the curren t duty cycle is less than or equal to this value th e breathing apparatus holds the current duty cycle for the period specified by the field ld in register led_delay, then starts incrementing the current duty cycle in blinking mode, this field defines the duty cycle of th e blink function. r/w 0h vcc1_ reset offset 08h bits description type default reset event 31:24 reserved r - - 23:12 high_delay in breathing mode, the number of pwm periods to wait before updat- ing the current duty cycle when the cu rrent duty cycle is greater than or equal to the value max in register led_limit. 4095=the current duty cycle is decremented after 4096 pwm periods ? 1=the delay counter is bypassed an d the current duty cycle is decre- mented after two pwm period 0=the delay counter is bypassed an d the current duty cycle is decre- mented after one pwm period r/w 000h vcc1_ reset 11:0 low_delay the number of pwm periods to wait before updating the current duty cycle when the current duty cycle is gr eater than or e qual to the value min in register led_limit. 4095=the current duty cycle is in cremented after 4096 pwm periods ? 0=the delay counter is bypassed and the current duty cycle is incre- mented after one pwm period in blinking mode, this field defines the prescalar for the pwm clock r/w 000h vcc1_ reset
MEC1322 ds00001719d-page 340 ? 2014 - 2015 microchip technology inc. 28.10.4 led update stepsize register this register has eight segment fields which provide the am ount the current duty cycle is adjusted at the end of every pwm period. segment field selection is decoded based on the segment index. the segment index equation utilized depends on the symmetry bit in the led configuration register register) ? in symmetric mode the segment_index[2:0] = duty cycle bits[7:5] . ? in asymmetric mode the segment_index[2:0] is the bit concatenation of following: segment_index[2] = (falling ramp time in figure 28-3, "clipping example") and segment_index[1:0] = duty cycle bits[7:6]. this register may be written at any time. values written into the register are held in an holding register, which is trans- ferred into the actual register at the end of a pwm period if the enable update bit in the led configuration register is set to 1. reads of this register return the current contents and not the value of the holding register. in 8-bit mode, each 4-bit stepsize field represents 16 possible duty cycle modifi cations, from 1 to 16 as the duty cycle is modified between 0 and 255: 15: modify the duty cycle by 16 ... 1: modify the duty cycle by 2 0: modify the duty cycle by 1 in 7-bit mode, the least significant bit of the 4-bit field is ignored, so each field represents 8 possible duty cycle modifi- cations, from 1 to 8, as the duty cycle is modified between 0 and 127: 14, 15: modify the duty cycle by 8 ... 2, 3: modify the duty cycle by 2 0, 1: modify the duty cycle by 1 in 6-bit mode, the two least significant bi ts of the 4-bit field is ignored, so each field represents 4 possible duty cycle modifications, from 1 to 4 as the dut y cycle is modified between 0 and 63: 12, 13, 14, 15: modify the duty cycle by 4 8, 9, 10, 11: modify the duty cycle by 3 4, 5, 6, 7: modify the duty cycle by 2 0, 1, 2, 3: modify the duty cycle by 1 offset 0ch bits description type default reset event 31:28 update_step7 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 111. r/w 0h vcc1_ reset 27:24 update_step6 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 110. r/w 0h vcc1_ reset 23:20 update_step5 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 101 r/w 0h vcc1_ reset 19:16 update_step4 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 100. r/w 0h vcc1_ reset 15:12 update_step3 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 011. r/w 0h vcc1_ reset
? 2014 - 2015 microchip technology inc. ds00001719d-page 341 MEC1322 28.10.5 led update interval register this register has eight segment fields which provide the number of pwm peri ods between updates to current duty cycle. segment field selection is decoded based on the segment index. the segment index equation utilized depends on the symmetry bit in the led configuration register register) ? in symmetric mode the segment_index[2:0] = duty cycle bits[7:5] ? in asymmetric mode the segment_index[2:0] is the bit concatenation of following: segment_index[2] = (falling ramp time in figure 28-3, "clipping example") and segment_index[1:0] = duty cycle bits[7:6]. this register may be written at any time. values written into the register are held in an holding register, which is trans- ferred into the actual register at the end of a pwm period if the enable update bit in the led configuration register is set to 1. reads of this register return the current contents and not the value of the holding register. 11:8 update_step2 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 010. r/w 0h vcc1_ reset 7:4 update_step1 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 001. r/w 0h vcc1_ reset 3:0 update_step0 amount the current duty cycle is adjusted at the end of every pwm period when the segment index is equal to 000. r/w 0h vcc1_ reset offset 10h bits description type default reset event 31:28 update_interval7 the number of pwm per iods between updates to current duty cycle when the segment index is equal to 111b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset 27:24 update_interval6 the number of pwm per iods between updates to current duty cycle when the segment index is equal to 110b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset 23:20 update_interval5 the number of pwm per iods between updates to current duty cycle when the segment index is equal to 101b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset offset 0ch bits description type default reset event
MEC1322 ds00001719d-page 342 ? 2014 - 2015 microchip technology inc. 19:16 update_interval4 the number of pwm periods betwe en updates to current duty cycle when the segment index is equal to 100b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset 15:12 update_interval3 the number of pwm periods betwe en updates to current duty cycle when the segment index is equal to 011b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset 11:8 update_interval2 the number of pwm periods betwe en updates to current duty cycle when the segment index is equal to 010b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset 7:4 update_interval1 the number of pwm periods betwe en updates to current duty cycle when the segment index is equal to 001b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset 3:0 update_interval0 the number of pwm periods betwe en updates to current duty cycle when the segment index is equal to 000b. 15=wait 16 pwm periods ? 0=wait 1 pwm period r/w 0h vcc1_ reset offset 10h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 343 MEC1322 29.0 ps/2 interface 29.1 introduction there are four ps/2 ports in the MEC1322 which are directly controlled by the ec. the hardware implementation elim- inates the need to bit bang i/o ports to generate ps/2 traffi c, however bit banging is available via the associated gpio pins. 29.2 references no references have been cited for this feature. 29.3 terminology there is no terminology defined for this section. 29.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 29.5 signal description figure 29-1: i/o diagram of block table 29-1: signal description table name direction description ps2dat input/ output data from the ps/2 device ps2clk input/ output clock from the ps/2 device ps/2 interface interrupts power, clocks and reset host interface signal description
MEC1322 ds00001719d-page 344 ? 2014 - 2015 microchip technology inc. 29.6 host interface the registers defined for the keyboard scan interface are accessible by the various hosts as indicated in section 29.15, "ec-only registers" . 29.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 29.7.1 power domains 29.7.2 clock inputs 29.7.3 resets 29.8 interrupts this section defines the interrupt sources generated from this block. 29.9 low power modes the ps/2 interface may be pu t into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. the ps2 interface will only sleep wh ile the ps2 is disabled or in rx mode with no traffic on the bus. 29.10 description each ec ps/2 serial channels use a synchronous serial protocol to communicate with the auxiliary device. each ps/2 channel has clock and data signal lines. the signal lines ar e bi-directional and employ open drain outputs capable of sinking 12m, as required by the ps/2 specification. a pull-up resistor, typically 10k, is connected to both lines. this allows either the ec ps/2 logic or the auxiliary device to drive the lines. regardless of the drive source, the auxiliary table 29-2: power sources name description vcc1 the logic and registers implemented in this block are powered by this power well. table 29-3: clock inputs name description 48 mhz ring oscillator this is the clock source for ps/2 interface logic. 2 mhz clock the ps/2 state machine is clocked using the 2 mhz clock. table 29-4: reset signals name description vcc1_reset this signal resets all the registers and logic in this block to their default state. table 29-5: ec interrupts source description pw2_x interrupt request to the interrupt aggregator for ps2 controller instance x , based on ps2 controller activity. section 29.15.4, "ps2 status register" defines the sources for the interrupt request. ps2_ x _wk wake-up request to the interrupt aggregator?s wake-up interface for ps2 port x . in order to enable ps2 wakeup interrupts, the pin control registers for the ps2dat pin must be programmed to input, falling edge triggered, non- inverted polarity detection.
? 2014 - 2015 microchip technology inc. ds00001719d-page 345 MEC1322 device always provides the clock for transmit and receive oper ations. the serial packet is made up of eleven bits, listed in the order they appear on the data line: start bit, eight data bits (least significant bit first), odd parity, and stop bit. each bit cell is from 60 s to 100 s long. all ps/2 serial channel signals (ps2clk and ps2dat) are dr iven by open drain drivers which can be pulled to vcc1 or the main power rail (+3.3v nominal) through 10k-ohm resistors. the ps/2 controller supports a ps/2 wake interface that can wake the ec from the idle or sleep states. the wake interface can generate wake interrupts without a clock. t he ps/2 wake interface is only active when the peripheral device and external pull-up resisters are powered by the vcc1 supply. there are no special precautions to be taken to prevent back drive of a ps/2 peripheral powered by the main power well when the power well is off, as long as the external 10k pull-up resistor is tied to the same power source as the peripheral. 29.11 block diagram 29.12 ps/2 port physical layer byte transmission protocol the ps/2 physical layer transfers a byte of data via an eleven bit serial stream as shown in ta b l e 2 9 - 6 . a logic 1 is sent at an active high level. data sent from a keyboard or mouse device to the host is read on the falling edge of the clock signal. the keyboard or mouse device al ways generates the clock signal. the host may inhibit communication by pull- ing the clock line low. the clock line must be continuously high for at least 50 microseconds before the keyboard or mouse device can begin to transmit its data. see table 29-7, "ps/2 port physical layer bus states" . figure 29-2: port ps/2 block diagram table 29-6: ps/2 port physical la yer byte transmission protocol bit function 1 start bit (always 0) 2 data bit 0 (least significant bit) 3 data bit 1 4 data bit 2 5 data bit 3 6 data bit 4 7 data bit 5 8 data bit 6 9 data bit 7 (most significant bit) 10 parity bit (odd parity) 11 stop bit (always 1) control registers ps2dat ps2clk ps/2 channel state machine ec i/f ps2_x interrupt 48mhz 2 mhz
MEC1322 ds00001719d-page 346 ? 2014 - 2015 microchip technology inc. 29.13 controlling ps/2 transactions ps/2 transfers are controlled by fields in the ps2 control register . the interface is enabled by the ps2_en bit. transfers are enabled when ps2_en is ?1? and disabled when ps2_en is ?0?. if the ps2_en bit is cleared to ?0? while a transfer is in progress but prior to the leading edge (falling edge) of the 10th (parity bit) clock edge, the receive data is discarded (rdata_rdy remains low). if the ps2_en bit is cleared fol- lowing the leading edge of the 10th clock signal, then the receive data is saved in the receive register (rdata_rdy goes high) assuming no parity error. the direction of a ps/2 transfer is controlled by the ps2_t/r bit. 29.13.1 receive if ps2_t/r is ?0? while the ps2 interface is enabled, the interface is configured to receive data. if while ps2_t/r is ?0? rdata_rdy is ?0?, the channel?s ps2clk and ps2dat will float waiting for the external ps/2 device to signal the start of a transmission. if rdata_rdy is ?1?, the channel?s ps2dat line will floa t but its ps2clk line will be held low, holding off the peripheral, until the receive register is read. the peripheral initiates a reception by sending a start bit followed by the data bits). after a successful reception, data are placed in the ps2 receive buffer register , the rdata_rdy bit in the ps2 status register is set and the ps2clk line is forced low. further receive transfers are inhibited until the ec reads the data in the ps2 receive buffer register. rdata_rdy is cleared and the ps2clk line is tri-stated following a read of the ps2 receive buffer register. the receive buffer register is initialized to ffh after a read or after a time-out has occurred. 29.13.2 transmit if ps2_t/r is ?1? while the ps2 interface is enabled, the inte rface is configured to transm it data. when the ps2_t/r bit is written to ?1? while the state machine is idle, the channel prepares for a transmission: the interface will drive the ps2- clk line low and then float the ps2dat line, holding this state until a write occurs to the transmit register or until the ps2_t/r bit is cleared. a transmi ssion is started by writing the ps2 transmit buffer register . writes to the transmit buffer register are blocked when ps2_en is ?0?, ps2_t/r is ?0? or when the transmit state machine is active (the xmit_idle bit in the ps/2 status register is ?0?). the transmi ssion of data will not start if there is valid data in the receive data register (when the status bit rdata_rdy is ?1?). when a transmission is st arted, the transmission state machine becomes active (the xmit_idle bit is set to ?1? by hardware), the ps2dat line is driven low and within 80ns the ps2clk line floats (externally pulled high by the pull-up resistor). the transmission terminates either on the 11th clock edge of the transmission or if a transmit time-out error condition occurs. when the transmission terminates, the ps2_t/r bit is cleared to ?0?and the state machine becomes idle, setting xmit_idle to ?1?. figure 29-3: ps/2 port physical la yer byte transmission protocol table 29-7: ps/2 port physical layer bus states data clock state high high idle high low communication inhibited low low request to send start bit bit 0 parity bit 7 bit 1 stop bit clk 1 clk2 clk9 clk10 clk11 clk3 ps2clk ps2data
? 2014 - 2015 microchip technology inc. ds00001719d-page 347 MEC1322 the ps2_t/r bit must be written to a ?1? before initiating anoth er transmission to the remote device. if the ps2_t/r bit is set to ?1? while the channel is actively receiving data (that is, while the status bit rdata_rdyis ?1?) prior to the leading edge of the 10th (parity bit) clock edge, the receive data is discarded. if the bit is set after the 10th edge, the receive data is saved in the receive register. 29.14 instance description 29.15 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the ps/2 interface. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 29.15.1 ps2 transmit buffer register table 29-8: ec-only register base address table block instance instance number host address space base address ps/2 interface 0 ec 32-bit internal address space 4000_9000h 1 ec 32-bit internal address space 4000_9040h 2 ec 32-bit internal address space 4000_9080h 3 ec 32-bit internal address space 4000_90c0h table 29-9: ec-only register summary offset register name 0h ps2 transmit buffer register 0h ps2 receive buffer register 4h ps2 control register 8h ps2 status register offset 00h bits description type default reset event 31:8 reserved r - - 7:0 transmit_data writes to this register start a transmission of the data in this register to the peripheral. w 0h vcc1_r eset
MEC1322 ds00001719d-page 348 ? 2014 - 2015 microchip technology inc. 29.15.2 ps2 receive buffer register 29.15.3 ps2 control register offset 00h bits description type default reset event 31:8 reserved r - - 7:0 receive_data data received from a peripheral are recorded in this register. a transmission initiated by writing the ps2 transmit buffer register will not start until valid data in this register have been read and rdata_rdy has been cleared by hardware. the receive buffer register is initialized to ffh after a read or after a time-out has occurred. rffh vcc1_r eset offset 00h bits description type default reset event 31:6 reserved r - - 5:4 stop these bits are used to set the level of the stop bit expected by the ps/2 channel state machine. these bits are therefore only valid when ps2_en is set. 00b=receiver expects an active high stop bit. 01b=receiver expects an active low stop bit. 10b=receiver ignores the level of the stop bit (11th bit is not inter- preted as a stop bit). 11b=reserved. r/w 0h vcc1_r eset 3:2 parity these bits are used to set the parity expected by the ps/2 channel state machine. these bits are therefore only valid when ps2_en is set. 00b=receiver expects odd parity (default). 01b=receiver expects even parity. 10b=receiver ignores level of the parity bit (10th bit is not interpreted as a parity bit). 11b=reserved r/w 0h vcc1_r eset 1 ps2_en ps/2 enable. 0=the ps/2 state machine is disabled. the clk pin is driven low and the data pin is tri-stated. 1=the ps/2 state machine is enabled, allowing the channel to per- form automatic reception or transmission, depending on the state of ps2_t/r. r/w 0h vcc1_r eset 0 ps2_t/r ps/2 transmit/receive 0=the p2/2 channel is enabled to receive data. 1=the ps2 channel is enabled to transmit data. r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 349 MEC1322 changing values in the ps2 control register at a rate faster than 2 mhz, may result in unpredictable behavior. 29.15.4 ps2 status register offset 08h bits description type default reset event 31:8 reserved r - - 7 xmit_start_timeout transmit start timeout. 0=no transmit start timeout detected 1=a start bit was not received within 25 ms following the transmit start event. the transmit start bit time-out condition is also indicated by the xmit_timeout bit. r/wc 0h vcc1_r eset 6 rx_busy receive channel busy. 0=the channel is actively receiving ps/2 data 1=the channel is idle r 0h vcc1_r eset 5 xmit_time_out transmitter idle. when the xmit_timeout bit is set, the ps2_t/r bit is held clear, the ps/2 channel?s clk line is pulled low for a minimum of 300 s until the ps/2 status register is read. the xmit_timeout bit is set on one of three transmit conditions: when the transmitter bit time (the time between falling edges) exceeds 300 s, when the transmit- ter start bit is not received within 25ms from signaling a transmit start event or if the time from the first bit (start) to the 10th bit (parity) exceeds 2ms r/wc 0h vcc1_r eset 4xmit_idle transmitter idle. 0=the channel is actively transmitting ps/2 data. writing the ps2 transmit buffer register will cause the xmit_idle bit to clear 1=the channel is not transmitting. this bit transitions from ?0? to ?1? in the following cases: the falling edge of the 11th clk xmit_timeout is set the ps2_t/r bit is cleared the ps2_en bit is cleared. a low to high transition on this bit generates a ps2 activity interrupt. r 0h vcc1_r eset 3fe framing error when receiving data, the stop bit is clocked in on the falling edge of the 11th clk edge. if the channel is configured to expect either a high or low stop bit and the 11th bit is contrary to the expected stop polarity, then the fe and rec_timeout bits are set following the falling edge of the 11th clk edge and an interrupt is generated. r/wc 0h vcc1_r eset
MEC1322 ds00001719d-page 350 ? 2014 - 2015 microchip technology inc. 2pe parity error when receiving data, the parity bit is clocked in on the falling edge of the 10th clk edge. if the channel is configured to expect either even or odd parity and the 10th bit is contrary to the expected parity, then the pe and rec_timeout bits are set following the falling edge of the 10th clk edge and an interrupt is generated. r/wc 0h vcc1_r eset 1 rec_timeout receive timeout following assertion of the rec_timeout bit, the channel?s clk line is automatically pulled low for a minimum of 300us until the ps/2 status register is read. under ps2 automatic operation, ps2_en is set, this bit is set on one of three receive error conditions: when the receiver bit time (the time between fallin g edges) exceeds 300 s. if the time from the first bit (start) to the 10th bit (parity) exceeds 2ms. on a receive parity error along with the parity error (pe) bit. on a receive framing error due to an incorrect stop bit along with the framing error (fe) bit. a low to high transition on this bit generates a ps2 activity interrupt. r/wc 0h vcc1_r eset 0 rdata_rdy receive data ready under normal operating conditions, this bit is set following the falling edge of the 11th clock given successful reception of a data byte from the ps/2 peripheral (i.e., no parity, framing, or receive time-out errors) and indicates that the received data byte is available to be read from the receive register. this bit may also be set in the event that the ps2_en bit is cleared following the 10th clk edge. reading the receive register clears this bit. a low to high transition on this bit generates a ps2 activity interrupt. r 0h vcc1_r eset offset 08h bits description type default reset event
? 2014 - 2015 microchip technology inc. ds00001719d-page 351 MEC1322 30.0 keyboard scan interface 30.1 overview the keyboard scan interface block provides a register interfac e to the ec to directly scan an external keyboard matrix of size up to 18x8. the maximum configuration of the keyboard scan interface is 18 outputs by 8 inputs. for a smaller matrix size, firmware should configure unused kso pins as gpios or another alternate function, and it should mask out unused ksis and associated interrupts. 30.2 references no references have been cited for this feature. 30.3 terminology there is no terminology defined for this section. 30.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 30.5 signal description figure 30-1: i/o diagram of block table 30-1: signal description table name direction description ksi[7:0] input column inputs from external keyboard matrix. kso[17:0] output row outputs to external keyboard matrix. signal description keyboard scan interface interrupts power, clocks and reset host interface
MEC1322 ds00001719d-page 352 ? 2014 - 2015 microchip technology inc. 30.6 host interface the registers defined for the keyboard scan interface are accessible by the various hosts as indicated in section 30.11, "ec-only registers" . 30.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 30.7.1 power domains 30.7.2 clock inputs 30.7.3 resets 30.8 interrupts this section defines the interrupt sources generated from this block. 30.9 low power modes the keyboard scan interface automatically enters a low power mode whenever it is not actively scanning the keyboard matrix. the block is also placed in a low-power state when it is disabled by the ksen bit. when the interface is in a low- power mode it will not prevent the chip from entering a sleep state. when the interf ace is active it will inhibit the chip sleep state until the interface has re-entered its low power mode. table 30-2: power sources name description vcc1 the logic and registers implemented in this block are powered by this power well. table 30-3: clock inputs name description 48 mhz ring oscillator this is the clock source for keyboard scan interface logic. table 30-4: reset signals name description vcc1_reset this signal resets all the registers and logic in this block to their default state. table 30-5: ec interrupts source description ksc_int interrupt request to the interrupt aggregator. ksc_int_wake wake-up request to the interrupt aggregator?s wake-up interface.
? 2014 - 2015 microchip technology inc. ds00001719d-page 353 MEC1322 30.10 description during scanning the firmware sequentially drives low one of the rows (kso[17:0]) and then reads the column data line (ksi[7:0]). a key press is detected as a zero in the corre sponding position in the matrix. keys that are pressed are debounced by firmware. once confirmed, the corresponding ke ycode is loaded into host data read buffer in the 8042 host interface module. firmware may need to buffer keycodes in memory in case this interface is stalled or the host requests a resend. 30.10.1 initialization of kso pins if the keyboard scan interface is not configured for pre drive mode, kso pins should be configured as open-drain outputs. internal or external pull-ups should be used so that the gpio functions that share the pins do not have a floating input when the kso pins are tri-stated. if the keyboard scan interface is configured for predrive mode, kso pins must be configured as push-pull outputs. internal or external pull-ups should be used to protect the gpio inputs associated with the kso pins from floating inputs. 30.10.2 predrive mode there is an optional predrive mode that can be enabled to ac tively drive the kso pins high before switching to open- drain operation. the predrive enable bit in the keyscan extended control register is used to enable the pre- drive option. timing for the predive mode is shown in section 38.9, keyboard scan matrix timing . 30.10.2.1 predrive mode programming the following precautions should be ta ken to prevent output pad damage during predrive mode programming . figure 30-2: keyboard scan interface block diagram kso select register kso[17:0] ksi input and status registers ksi[7:0] ksi interrupt interface output decoder ksc_int ksc_int_wake 48mhz vcc1_reset spb i/f ec bus
MEC1322 ds00001719d-page 354 ? 2014 - 2015 microchip technology inc. 30.10.2.2 asserting predrive_enable 1. disable key scan in terface (ksen = '1') 2. enable predrive function (predrive_enable = '1') 3. program buffer type for all kso pins to "push-pull? 4. enable keyscan interface (ksen ='0') 30.10.2.3 de-assert ing predrive_enable 1. disable key scan in terface (ksen = '1') 2. program buffer type for all kso pins to "open-drain? 3. disable predrive function (predrive_enable = '0') 4. enable keyscan interface (ksen ='0') 30.10.3 interrupt generation to support interrupt-based processing, an interrupt can optionally be generated on the high-to-low transition on any of the ksi inputs. a running clock is not required to generate interrupts. 30.10.3.1 runtime interrupt ksc_int is the block?s runtime active-high level interrupt. it is connected to the interrupt interface of the interrupt aggre- gator, which then relays interrupts to the ec. associated with each ksi input is a status register bit and an in terrupt enable register bit. a status bit is set when the associated ksi input goes from high to low. if the interrupt enable bit for that input is set, an interrupt is generated. an interrupt is de-asserted when the status bit and/or interrupt e nable bit is clear. a status bit cleared when written to a ?1?. interrupts from individual ksis are logically ored together to drive the ksc_int output port. once asserted, an interrupt is not asserted again until either all ksi[7:0] inputs have returned high or the has changed. 30.10.3.2 wake-up interrupt ksc_int_wake is the block?s wakeup interrupt. it is routed to the interrupt aggregator. during sleep mode, i.e., when the bus clock is stopped, a hi gh-to-low transition on any ksi whose interrupt enable bit is set causes the ksc_int_wake to be asserted. also set is th e associated status bit in the ec clock required 2 status register (ec_clk_req2_sts) . ksc_wakeup_int remains active un til the bus clock is started. the aforementioned transition on ksi also sets the corresponding status bit in the ksi status register . if enabled, a runtime interrupt is also asserted on ksc _int when the bus cl ock resumes running. 30.10.4 wake programming using the keyboard scan interface to ?wake? the MEC1322 can be accomplished using either the keyboard scan inter- face wake interrupt, or using the wake capabilities of the gpio interface pins that are multiplexed with the keyboard scan interface pins. enabling the keyboard scan interface wake interrupt requires only a single interrupt enable access and is recommended over using the gpio interface for this purpose. 30.11 ec-only registers the registers listed in the ec-only register summary tabl e are for a single instance of the keyboard scan interface. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. table 30-6: ec-only register base address table block instance instance number host address space base address keyboard scan interface 0 ec 32-bit internal address space 4000_9c00h
? 2014 - 2015 microchip technology inc. ds00001719d-page 355 MEC1322 30.11.1 kso select register table 30-7: ec-only register summary offset register name 0h reserved 4h kso select register 8h ksi input register ch ksi status register 10h ksi interrupt enable register 14h keyscan extended control register offset 04h bits description type default reset event 31:4 reserved r - - 7 kso_invert this bit controls the output level of kso pins when selected. 0= kso[x] driven low when selected 1= kso[x] driven high when selected. r/w 0b vcc1_r eset 6 ksen this field enables and disables keyboard scan 0= keyboard scan enabled 1= keyboard scan disabled. all kso output buffers disabled. r/w 1h vcc1_r eset 5 kso_all 0=when key scan is enabled, kso output controlled by the kso_se- lect field. 1=kso[x] driven high when selected. r/w 0b vcc1_r eset 4:0 kso_select this field selects a kso line (00000b = kso[0] etc.) for output according to the value off kso_invert in this register. see table 30-8, "kso select decode" r/w 0h vcc1_r eset table 30-8: kso select decode kso select [4:0] kso selected 00h kso00 01h kso01 02h kso02 03h kso03 04h kso04 05h kso05 06h kso06 07h kso07 08h kso08 09h kso09 0ah kso10
MEC1322 ds00001719d-page 356 ? 2014 - 2015 microchip technology inc. 30.11.2 ksi input register 30.11.3 ksi status register 0bh kso11 0ch kso12 0dh kso13 0eh kso14 0fh kso15 10h kso16 11h kso17 table 30-9: keyboard sc an out control summary kso_invertt ksen kso_all kso_select description x 1 x x keyboard scan disabled. kso[17:0] output buffers disabled. 0 0 0 10001b-00000b kso[drive selected] driven low. all others driven high 1 0 0 10001b-00000b kso[drive selected] driven high. all others driven low 0 0 0 11111b-10010b all kso?s driven high 1 0 0 11111b-10010b all kso?s driven low 0 0 1 x all kso?s driven high 1 0 1 x all kso?s driven low offset 08h bits description type default reset event 31:8 reserved r - - 7:0 ksi this field returns the current state of the ksi pins. r 0h vcc1_r eset offset 0ch bits description type default reset event 31:8 reserved r - - 7:0 ksi_status each bit in this field is set on the falling edge of the corresponding ksi input pin. a ksi interrupt is generated when its corresponding status bit and interrupt enable bit are both set. ksi interrupts are logically ored together to produce ksc_int and ksc_int_wake . writing a ?1? to a bit will clear it. wr iting a ?0? to a bit has no effect. r/wc 0h vcc1_r eset table 30-8: kso select decode (continued) kso select [4:0] kso selected
? 2014 - 2015 microchip technology inc. ds00001719d-page 357 MEC1322 30.11.4 ksi interrupt enable register 30.11.5 keyscan extende d control register offset 10h bits description type default reset event 31:8 reserved r - - 7:0 ksi_int_en each bit in ksi_int_en enables interrupt generation due to high-to- low transition on a ksi input. an interrupt is generated when the cor- responding bits in ksi_status and ksi_int_en are both set. r/w 0h vcc1_r eset offset 14h bits description type default reset event 32:1 reserved r - - 0 predrive_enable predrive_enable enables the predrive mode to actively drive the kso pins high for approximately 100 ns before switching to open-drain operation. 0=disable predrive on kso pins 1=enable predrive on kso pins. rw 0 vcc1_reset
MEC1322 ds00001719d-page 358 ? 2014 - 2015 microchip technology inc. 31.0 bc-link master 31.1 overview this block provides bc-link ? connectivity to a slave device. the bc-link ? protocol includes a start bit to signal the beginning of a message and a turnaround (tar) period for bus transfer between the master and companion devices. 31.2 references no references have been cited for this feature. 31.3 terminology there is no terminology defined for this section. 31.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 31.5 signal description figure 31-1: i/o diagram of block table 31-1: signal description table name direction description bcm_clk output bc-link output clock bcm_dat input/output bidirectional data line bcm_int# input input from the companion device note: a weak pull-up resistor is recommended on the data line (100k ). bc-link master interrupts power, clocks and reset interface signal description
? 2014 - 2015 microchip technology inc. ds00001719d-page 359 MEC1322 the maximum speed at which the bc-link master interface can operate reliably depends on the drive strength of the bc-link bcm_clk and bcm_dat pins, as well as the nature of the connection to the companion device (over ribbon cable or on a pc board). the following table shows the reco mmended maximum speeds over a pc board as well as a 12 inch ribbon cable for selected drive strengths. the frequency is set with the bc-link clock select register . 31.6 host interface the registers defined for the bc-link master interface are accessible by the various hosts as indicated in section 31.11, "ec-only registers" . 31.7 power, clocks and reset 31.7.1 power domains 31.7.2 clock inputs 31.7.3 resets 31.8 interrupts this section defines the interrupt sources generated from this block. table 31-2: bc-link master pin drive strength vs. frequency pin drive strength max freq on pc board min value in bc-link clock select register max freq over ribbon cable min value in bc-link clock select register 16ma 24mhz 1 16mhz 2 table 31-3: power sources name description vcc1 the logic and registers implemented in this block are powered by this power well. table 31-4: clock inputs name description 48 mhz ring oscillator this is the clock source for keyboard scan interface logic. table 31-5: reset signals name description vcc1_reset this signal resets all the registers and logic in this block to their default state. table 31-6: ec interrupts source description bcm_int busy interrupt request to the interrupt aggregator, generated from the status event busy defined in the bc-link status register . bcm_int err interrupt request to the interrupt aggregator, generated from the status event defined in the bc-link status register . bc_int_n_wk wake-up request to the interrupt aggregator?s wake-up interface for bc- link master port. in order to enable bc-link wakeup interrupts, the pin control registers for the bc_int# pin must be programmed to input, falling edge triggered, non-inverted polarity detection.
MEC1322 ds00001719d-page 360 ? 2014 - 2015 microchip technology inc. 31.9 low power modes the bc-link master interface automatically enters a low power mode whenever it is not active (that is, whenever the busy bit in the bc-link status register is ?0?). when the interface is in a low-power mode it will not prevent the chip from entering a sleep state. when the inte rface is active it will inhibit the chip sleep state until the interface has re- entered its low power mode. 31.10 description 31.10.1 bc-link mast er read operation the bc-link read protocol requires two reads of the bc-link data register . the two reads drive a two state-state machine: the two states are read#1 and read#2. the read#1 of the data register starts the read protocol on the bc- link pins and sets the busy bit in the bc-link status register . the contents of the data read during read#1 by the ec is stale and is not to be used. after the busy bit in the bc-link status register autonomously clears to ?0?, the read#2 of the data register transfers the data read from the peripheral/bc-link companion chip to the ec. 1. software starts by checking the status of the busy bit in the status register. if the busy bit is ?0?, proceed. if busy is ?1?, firmware must wait until it is ?0?. 2. software writes the address of the register to be read into the bc-link address register . 3. software then reads the data register. this read returns random data. the read activates the bc-link master state machine to transmit the read request packet to the bc-link companion. when the transfer initiates, the hardware sets the busy bit to a ?1?. 4. the bc-link companion reads the selected register and transmits the read response packet to the bc-link mas- ter. the companion will i gnore the read request if there is a crc erro r; this will cause t he master state machine to time-out and issue a bc_err interrupt. figure 31-2: bc-link master block diagram bc bus master ip bcm_clk bcm_dat bcm_int# bc status / control register bc data register bc address register external pin interface ec if registers clock divider bits bc_busy_clr bc_err clock generator mclk/2 mclk/4 mclk/8 ? ? ? mclk/ 63 mclk=48mhz ring oscillator ? ? ? mclk/ divider
? 2014 - 2015 microchip technology inc. ds00001719d-page 361 MEC1322 5. the master state machine loads the data register, issu es a busy bit clear interrupt and clears the busy bit to ?0?. 6. software, after either receiving the bit clear interrupt, or polling the busy bit until it is ?0?, checks the bc_err bit in the status register. 7. software can now read the data register which contains the valid data if there was no bc bus error. 8. if a bus error occurs, firmware must issue a soft reset by setting the reset bit in the status register to ?1?. 9. the read can re-tried once busy is cleared. 31.10.2 bc-link master write operation 1. software starts by checking the status of the busy bit in the bc-link status register . if the busy bit is ?0?, pro- ceed. if busy is ?1?, firmware must wait until it is ?0?. 2. software writes the address of the register to be written into the bc-link address register . 3. software writes the data to be written into the addressed register in to the bc-link data register . 4. the write to the data register starts the bc_link write operation. the master state machine sets the busy bit. 5. the bc-link master interface transmits the write request packet. 6. when the write request packet is received by the bc-lin k companion, the crc is checked and data is written to the addressed companion register. 7. the companion sends an ack if the wr ite is completed. a time-out will o ccur approximately 16 bc-link clocks after the packet is sent by the master state machine. if a time-out occurs, the state machine will set the bc_err bit in the status register to ?1? approximately 48 clocks later and then clear the busy bit. 8. the master state machine issues the bit clear interrupt and clears the busy bit after receiving the ack from the companion 9. if a bus error occurs, firmware must issue a soft reset by setting the reset bit in the status register to ?1?. 10. the write can re-tried once busy is cleared. 31.11 ec-only registers the registers listed in the ec-only register summary tabl e are for a single instance of the bc-link master interface. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in the ec-only register base address table. note 31-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. note: steps 3 thorough 7 should be completed as a contiguous sequence. if not the interface could be presenting incorrect data when software thinks it is accessing a valid register read. table 31-7: ec-only register base address table block instance instance number host address space base address ( note 31-1 ) bc-link 0 ec 32-bit internal address space 4000_bc00h table 31-8: ec-only register summary register name ec offset bc-link status register 00h bc-link address register 04h bc-link data register 08h bc-link clock select register 0ch
MEC1322 ds00001719d-page 362 ? 2014 - 2015 microchip technology inc. 31.11.1 bc-link status register 31.11.2 bc-link address register offset 00h bits description type default reset event 31:4 reserved r - - 7 reset when this bit is ?1?the bc_link ma ster interface will be placed in reset and be held in reset until this bit is cleared to ?0?. setting reset to ?1? causes the busy bi t to be set to ?1?. the busy remains set to ?1? until the reset operation of the bc interface is com- pleted, which takes approximately 48 bc clocks. the de-assertion of the busy bit on reset will not generate an inter- rupt, even if the bc_busy_clr_in t_en bit is ?1?. the busy bit must be polled in order to determine when the reset operation has completed. r/w 1h vcc1_r eset 6bc_err this bit indicates that a bc bus error has occurred. if an error occurs this bit is set by hardware when the busy bit is cleared. this bit is cleared when written with a ?1?. an interrupt is generated if this bit is ?1? and bc_err_int_en bit is ?1?. errors that cause this interrupt are: ? bad data received by the base (crc error) ? time-out caused by the companion not responding. all companion errors cause the companion to abort the opera- tion and the base to time-out. r/wc 0h vcc1_r eset 5 bc_err_int_en this bit is an enable for generating an interrupt when the bc_err bit is set by hardware. when this bit is ?1?, the interrupt signal is enabled. when this bit is ?0?, the interrupt is disabled. r/w 0b vcc1_r eset 4 bc_busy_clr_int_en this bit is an enable for generating an interrupt when the busy bit in this register is cleared by hardware. when this bit is set to ?1?, the interrupt signal is enabled. when the this bit is cleared to ?0?, the inter- rupt is disabled. when enabled, the interrupt occurs after a bc bus read or write. r/w 0h vcc1_r eset 3:1 reserved r - - 0busy this bit is asserted to ?1? when the bc interface is transferring data and on reset. otherwise it is cleared to ?0?. when this bit is cleared by hardware, an interrupt is generated if the bc_busy_cl- r_int_en bit is set to ?1?. r 1h vcc1_r eset offset 04h bits description type default reset event 31:8 reserved r - - 7:0 address address in the companion for the bc-link transaction. r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 363 MEC1322 31.11.3 bc-link data register 31.11.4 bc-link clock select register offset 08h bits description type default reset event 31:8 reserved r - - 7:0 data as described in section 31.10.1, "bc-link master read operation" and section 31.10.2, "bc-link master write operation" , this regis- ter hold data used in a bc-link transaction. r/w 0h vcc1_r eset offset 0ch bits description type default reset event 31:8 reserved r - - 7:0 divider the bc clock is set to the master clock divided by this field, or 48mhz/ (divider +1). the clock divider bits can only can be changed when the bc bus is in soft reset (when either the reset bit is set by software or when the busy bit is set by the interface). example settings for divider are shown in table 31-9, "example frequency settings" . r/w 4h vcc1_r eset table 31-9: example frequency settings divider frequency 0 48mhz 1 24mhz 2 16mhz 3 12mhz 49.6mhz 15 2.18mhz 2a 1.12mhz
MEC1322 ds00001719d-page 364 ? 2014 - 2015 microchip technology inc. 32.0 trace fifo debug port (tfdp) 32.1 introduction the tfdp serially transmits embedded controller (ec)-origi nated diagnostic vectors to an external debug trace system. 32.2 references no references have been cited for this chapter. 32.3 terminology there is no terminology defined for this chapter. 32.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 32.5 signal description the signal description table lists the signals t hat are typically routed to the pin interface. 32.6 host interface the registers defined for the trace fifo debug port (tfdp) are accessible by the various hosts as indicated in section 32.11, "ec-only registers" . figure 32-1: i/o diagram of block table 32-1: signal description table name direction description tfdp clk output derived from ec bus clock. tfdp data output serialized data shifted out by tfdp clk . signal description trace fifo debug port (tfdp) interrupts power, clocks and reset host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 365 MEC1322 32.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 32.7.1 power domains 32.7.2 clock inputs 32.7.3 resets 32.8 interrupts there are no interrupts generated from this block. 32.9 low power modes the trace fifo debug port (tfdp) may be put into a low power state by the chip?s power, clocks, and reset (pcr) circuitry. 32.10 description the tfdp is a unidirectional (from processor to external world) two-wire serial, byte-oriented debug interface for use by processor firmware to transmit diagnostic information. the tfdp consists of the debug data register , debug control register , a parallel-to-serial conv erter, a clock/control interface and a two-pin external interface ( tfdp clk , tfdp data ). figure 32-2: block diag ram of tfdp debug port table 32-2: power sources name description vcc1 this power well sources all of the registers and logic in this block. table 32-3: clock inputs name description 48 mhz ring oscillator this clock input is used to derive the tfdp clk . table 32-4: reset signals name description vcc1_reset this reset signal resets all of the registers and logic in this block. data register parallel-to-serial converter clock/control interface write_complete mclk tfdp_dat tfdp_clk
MEC1322 ds00001719d-page 366 ? 2014 - 2015 microchip technology inc. the firmware executing on the embedded controller writes to the debug data register to initiate a transfer cycle. at first, data from the debug data register is shifted into the lsb. afterwards, it is transmitted at the rate of one byte per transfer cycle. data is transferred in one direction only from the debug data register to the external interface. the data is shifted out at the clock edge. the clock edge is selected by the edge_sel bit in the debug control register . after being shifted out, valid data is provided at the opposite edge of the tfdp_clk. for example, when the edge_sel bit is ?0? (default), valid data is maintained at the falling edge of tfdp_clk. the setup time (to the falling edge of tfdp_clk) is 10 ns, minimum. the hold time is 1 ns, minimum. when the serial debug port is inactive, the tfdp_clk and tfdp_dat outputs are ?1.? the ec bus clock clock input is the transfer clock. figure 32-3: data transfer 32.11 ec-only registers the registers listed in the ec-only register summary table are for a single instance of the trace fifo debug port (tfdp) . the addresses of each register listed in this table ar e defined as a relative offset to the host ?base address? defined in the ec-only register base address table. the base address indicates where the first register can be accessed in a particular address space for a block instance. 32.11.1 debug data register the debut data register is read/write. it always returns t he last data written by the tfdp or the power-on default ?00h?. table 32-5: ec-only register base address table block instance instance number host address space base address tfdp debug port 0 ec 32-bit internal address space 4000_8c00h table 32-6: ec-only register summary offset register name (mnemonic) 00h debug data register 04h debug control register offset 00h bits description type default reset event 7:0 data debug data to be shifted out on the tfdp debug port. while data is being shifted out, the host interface will ?hold-off? additional writes to the data register until the transfer is complete. r/w 00h vcc1_r eset tfdp_clk tfdp_dat cpu_clock d0 d1 d2 d3 d4 d5 d6 d7
? 2014 - 2015 microchip technology inc. ds00001719d-page 367 MEC1322 32.11.2 debug control register offset 04h bits description type default reset event 7 reserved r - - 6:4 ip_delay inter-packet delay. the delay is in terms of tfdp debug output clocks. a value of 0 provides a 1 clock inter-packet period, while a value of 7 provides 8 clocks between packets: r/w 000b vcc1_r eset 3:2 divsel clock divider select. the tfdp debug output clock is determined by this field, according to table 32-7, "tfdp debug clocking" : r/w 00b vcc1_r eset 1 edge_sel 1= data is shifted out on t he falling edge of the debug clock 0= data is shifted out on the rising edge of the debug clock (default) r/w 0b vcc1_r eset 0en enable. 1=clock enabled 0=clock is disabled (default) r/w 0b vcc1_r eset table 32-7: tfdp debug clocking divsel tfdp debug clock 00 24 mhz 01 12 mhz 10 6 mhz 11 reserved
MEC1322 ds00001719d-page 368 ? 2014 - 2015 microchip technology inc. 33.0 analog to digital converter 33.1 introduction this block is designed to convert external analog voltage read ings into digital values. it co nsists of a single successive- approximation analog-digital converter that can be shared among five inputs. 33.2 references no references have been cited for this chapter 33.3 terminology no terminology is defined for this chapter 33.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 33.5 signal description the signal description table lists the signals t hat are typically routed to the pin interface. note: transitions on adc gpios are not permitted when analog to digital converter readings are being taken. figure 33-1: i/o diagram of block table 33-1: signal description table name direction description adc 4:0 input adc analog voltage input 4:0 from pins note: vref_adc, the analog voltage reference of 3.0v, is internally generated in the ip block. signal description analog to digital converter interrupts power, clocks and reset host interface
? 2014 - 2015 microchip technology inc. ds00001719d-page 369 MEC1322 33.6 host interface the registers defined for the trace fifo debug port ar e accessible by the various hosts as indicated in section 33.11, "ec-only registers" . 33.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 33.7.1 power domains 33.7.2 clock inputs 33.7.3 resets 33.8 interrupts 33.9 low power modes the adc may be put into a low power state by the chip?s powe r, clocks, and reset (pcr) circuitry. the adc is designed to conserve power when it is either sleeping or disabled. it is disabled via the activate bit and sleeps when the adc_sleep_en signal is asserted. the sleeping state only controls clocking in the adc and does not power down the analog circuitry. for lowest power consumption, the adc activate bit must be set to ?0.? table 33-2: power sources name description vcc1 this power well sources the registers tn this block. avcc this power well sources of the logic in this block, except where noted. avss this is the ground signal for the block. table 33-3: clock inputs name description 1.2mhz this derived clock signal drives selected logic (1.2 mh z clock with a 50% duty cycle). table 33-4: reset signals name description vcc1_reset this reset signal resets all of the registers and logic in this block. table 33-5: ec interrupts source description adc_single_int interrupt signal from adc cont roller to ec for single-sample adc con- version. adc_repeat_int interrupt signal from adc cont roller to ec for repeated adc conversion. note: the adc vref must be powered down in order to get the lowest deep sleep current. the adc vref power down bit, adc_vref_pd_ref is in the ec subsystem registers adc vref pd on page 381 .
MEC1322 ds00001719d-page 370 ? 2014 - 2015 microchip technology inc. 33.10 description the MEC1322 features a five channel successive approximati on analog to digital converter. the adc architecture fea- tures excellent linearity and converts analog signals to 10 bit words. conversion takes less than 12 microseconds per 10-bit word. the five channels are implemented with a single high speed adc fed by a five input analog multiplexer. the multiplexer cycles through the five voltage channels, star ting with the lowest-numbered channel and proceeding to the highest-number channel, selecting only thos e channels that are programmed to be active. the input range on the voltage channels spans from 0v to the internal voltage reference. with an internal voltage ref- erence of 3.0v, this provides resolutions of 2.9mv. the r ange can easily be extended with the aid of resistor dividers. the accuracy of any voltage reading depends on the accuracy and stability of the voltage reference input. the adc conversion cycle starts either when the start_single bit in the adc to set to 1 or when the adc repeat timer counts down to 0. when the start_single is set to 1 the conversion cycle converts channels enabled by configuration bits in the adc single register . when the repeat timer counts down to 0 the conversion cycle converts channels enabled by configuration bits in the adc repeat register . when both the start_single bit and the repeat timer request conversions the start_single conversion is completed first. conversions always start with the lowest-numbered enab led channel and proceed to the highest-numbered enabled channel. 33.10.1 repeat mode ? repeat mode will start a conversion cycl e of all adc channels enabled by bits rpt_en[4:0] in the adc repeat register . the conversion cycle will begin after a delay determined by start_delay[15:0] in the adc delay regis- ter . figure 33-2: adc block diagram note: the adc pins are 3.3v tolerant. note: if software repeatedly sets start_single to 1 at a rate faster than the repeat timer count down interval, the conversion cycle defined by the adc repeat register will not be executed. adc block adc reading registers adc_single_int latch control logic 10-bit reading value reading host interface mux adc control analog inputs ( ( ( vref adc_repeat_int adc_sleep_en adc_clk_req
? 2014 - 2015 microchip technology inc. ds00001719d-page 371 MEC1322 ? after all channels enabled by rpt_en[4:0] are complete, repeat_done_status will be set to 1. this status bit is cleared when the next repeat ing conversion cycle begins to give a reflec tion of when the conversion is in prog- ress. ? as long as start_repeat is 1 the adc will repeatedly begin c onversion cycles with a period defined by repeat_delay[15:0] . ? if the delay period expires and a conversion cycle is already in progress because start_single was written with a 1, the cycle in progress will complete, followed immediately by a conversion cycle using rpt_en[4:0] to control the channel conversions. 33.10.2 single mode ? the single mode conversion cycle will begin wi thout a delay. after all channels enabled by single_en[4:0] are complete, single_done_status will be set to 1. when the next conver sion cycle begins the bit is cleared. ?if start_single is written with a 1 while a conv ersion cycle is in progress because start_repeat is set, the conver- sion cycle will complete, followed i mmediately by a conversion cycle using single_en[4:0] to control the channel conversions. 33.11 ec-only registers the registers listed in the table 33-7, "analog to digital converter register summary" are for a single instance of the analog to digital converter block. the addresses of each register listed in this table are defined as a relative offset to the host ?base address? defined in table 33-6, "analog to digital converter base address table" . note 33-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. table 33-6: analog to digital converter base address table instance name instance number host address space base address ( note 33-1 ) adc 0 ec 32-bit internal address space 4000_7c00h table 33-7: analog to digita l converter register summary offset register name (mnemonic) 00h adc control register 04h adc delay register 08h adc status register 0ch adc single register 10h adc repeat register 14h adc channel 0 reading register 18h adc channel 1 reading register 1ch adc channel 2 reading register 20h adc channel 3 reading register 24h adc channel 4 reading register
MEC1322 ds00001719d-page 372 ? 2014 - 2015 microchip technology inc. 33.11.1 adc control register the adc control register is used to control the behavior of the analog to digital converter. offset 00h bits description type default reset event 31:8 reserved res 7 single_done_status this bit is cleared when it is written with a 1. writing a 0 to this bit has no effect. this bit can be used to generate an ec interrupt. 0: adc single-sample conversion is not complete. this bit is cleared whenever an adc conversion cycle begins for a single conversion cycle. 1: adc single-sample conversion is completed. this bit is set to 1 when all enabled channels in the single conversion cycle. r/wc 0h vcc1_r eset 6 repeat_done_status this bit is cleared when it is written with a 1. writing a 0 to this bit has no effect. this bit can be used to generate an ec interrupt. 0: adc repeat-sample conversion is not complete. this bit is cleared whenever an adc conversion cycle begins for a repeating conver- sion cycle. 1: adc repeat-sample conversion is completed. this bit is set to 1 when all enabled channels in a repeating conversion cycle com- plete. r/wc 0h vcc1_r eset 5 reserved res 4 soft reset 1: writing one causes a reset of the adc block hardware (not the registers) 0: writing zero takes th e adc block out of reset r/w 0h vcc1_r eset 3 power_saver_dis 0: power saving feature is enabled. the analog to digital converter controller powers down the adc between conversion sequences. 1: power saving feature is disabled. r/w 0h vcc1_r eset 2 start_repeat 0: the adc repeat mode is disabled. note: this setting will not ter- minate any conversion cycle in proce ss, but will inhibit any further periodic conversions. 1: the adc repeat mode is enabled. this setting will start a conver- sion cycle of all adc c hannels enabled by bits rpt_en[4:0] in the adc repeat register . r/w 0h vcc1_r eset 1 start_single 0: the adc single mode is disabled. 1: the adc single mode is enabled. this setting starts a single con- version cycle of all adc channels enabled by bits single_en[4:0] in the adc single register . note: this bit is self-clearing r/w 0h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 373 MEC1322 33.11.2 adc delay register the adc delay register determines the delay from setting start_repeat in the adc control register and the start of a conversion cycle. this register also controls the interval between conversion cycles in repeat mode. 33.11.3 adc status register the adc status register indicates whether the adc has completed a conversion cycle. 0 activate 0: the adc is disabled and placed in its lowest power state. note: any conversion cycle in process will complete before the block is shut down, so that the reading registers will contain valid data but no new conversion cycles will begin. 1: adc block is enabled for operation. start_single or start_repeat can begin data conversions by the adc. note: a reset pulse is sent to the adc core when this bit changes from 0 to 1. r/w 0h vcc1_r eset offset 04h bits description type default reset event 31:16 repeat_delay[15:0] this field determines the interval between conversion cycles when start_repeat is 1. the delay is in units of 40 s. a value of 0 means no delay between conversion cycles, and a value of 0xffff means a delay of 2.6 seconds. this field has no effect when start_single is written with a 1. r/w 0000h vcc1_r eset 15:0 start_delay[15:0] this field determines the starting delay before a conversion cycle is begun when start_repeat is written with a 1. the delay is in units of 40 s. a value of 0 means no delay before the start of a conversion cycle, and a value of 0xffff means a delay of 2.6 seconds. this field has no effect when start_single is written with a 1. r/w 0000h vcc1_r eset offset 08h bits description type default reset event 31:5 reserved res 4:0 adc_ch_status[4:0] all bits are cleared by being written with a ?1?. 0: conversion of the corresponding adc channel is not complete 1: conversion of the corresponding adc channel is complete note: for enabled single cycles, the single_done_status bit in the adc control register is also set after all enabled channel conver- sion are done; for enabled repeat cycles, the repeat_done_status in the adc control register is also set after all enabled channel con- version are done. r/wc 00h vcc1_r eset offset 00h bits description type default reset event
MEC1322 ds00001719d-page 374 ? 2014 - 2015 microchip technology inc. 33.11.4 adc single register the adc single register is used to control which adc channel is captured during a single- sample conversion cycle initiated by the start_single bit in the adc control register . application note: do not change the bits in this register in t he middle of a conversion cycle to insure proper operation. 33.11.5 adc repeat register the adc repeat register is used to control which adc channels are capt ured during a repeat conversion cycle initiated by the start_repeat bit in the adc control register . 33.11.6 adc channel reading registers all 5 adc channels return their results into a 32-bit reading register. in each case the low 10 bits of the reading register return the result of the analog to digital conversion and the upper 22 bits return 0. table 33-7, ?analog to digital con- verter register summary,? on page 371 shows the addresses of all the reading registers. offset 0ch bits description type default reset event 31:5 reserved res 4:0 single_en[4:0] 0: single cycle conversions for this channel are disabled 1: single cycle conversions for this channel are enabled each bit in this field enables the corresponding adc channel when a single cycle of conversions is started when the start_single bit in the adc control register is written with a 1. r/w 00h vcc1_r eset offset 10h bits description type default reset event 31:5 reserved res 4:0 rpt_en[4:0] 0: repeat conversions for this channel are disabled 1: repeat conversions for this channel are enabled each bit in this field enables the corresponding adc channel for each pass of the repeated adc conversion that is controlled by bit start_repeat in the adc control register . r/w 00h vcc1_r eset note: the adc channel reading registers access require single 16, or 32 bit reads; i.e., two 8 bit reads cannot ensure data coherency. offset see table 33-7, "analog to digital converter register summary" bits description type default reset event 31:10 reserved res 9:0 adcx_[9:0] this read-only field reports the 10-bit output reading of the input adcx. r/w 000h vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 375 MEC1322 34.0 vbat-powered ram 34.1 overview the vbat powered ram provides a 64 byte random accesse d memory that is operational while the main power rail is operational, and will retain its values powered by battery power while the main rail is unpowered. 34.2 references no references have been cited for this feature. 34.3 terminology there is no terminology defined for this section. 34.4 interface this block is designed to be accessed externally via the pin interface and internally via a registered host interface. 34.5 signal description there are no external signals for this block. 34.6 host interface the registers defined for the keyboard scan interface are accessible by the various hosts as indicated in section 34.11, "registers" . 34.7 power, clocks and reset this section defines the power, clock, and reset parameters of the block. figure 34-1: i/o diagram of block vbat-powered ram interrupts power, clocks and reset host interface signal description
MEC1322 ds00001719d-page 376 ? 2014 - 2015 microchip technology inc. 34.7.1 power domains 34.7.2 clock inputs no special clocks are required for this block. 34.7.3 resets 34.8 interrupts this block does not generate any interrupts. 34.9 low power modes the vbat-powered ram automatically enters a low power mode whenever it is not being accessed by the ec. there is no chip-level sleep enable input. 34.10 description the vbat powered ram provides a 64 byte random accessed memory that is operational while vcc1 is powered, and will retain its values powered by vbat while vcc1 is unpowered. the ram is organized as a 16 words x 32-bit wide for a total of 64 bytes. table 34-1: power sources name description vcc1 the main power well used when the vbat ram is accessed by the ec. vbat the power well used to retain memory state while the main power rail is unpowered. table 34-2: reset signals name description vbat_por this signal resets all the registers and logic in this block to their default state. figure 34-2: vbat ram block diagram vbat powered ram ec interface this interface is only operational when main power is present
? 2014 - 2015 microchip technology inc. ds00001719d-page 377 MEC1322 34.11 registers 34.11.1 registers summary the registers listed in the table 34-3, "ec-only register base address table" are for a single instance of the keyboard scan interface block. each 32-bit ram location is an offset from the ec base address. note 34-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. table 34-3: ec-only register base address table block instance instance number host address space base address ( note 34-1 ) vbat-powered ram 0 ec 32-bit internal address space 4000_a800h
MEC1322 ds00001719d-page 378 ? 2014 - 2015 microchip technology inc. 35.0 ec subsystem registers 35.1 introduction this chapter defines a bank of registers associated with the ec subsystem. 35.2 references none 35.3 interface this block is designed to be accessed internally by the ec via the register interface. 35.4 power, clocks and reset this section defines the power, clock, and reset parameters of the block. 35.4.1 power domains 35.4.2 clock inputs this block does not require any special clock inputs. al l register accesses are synchronized to the host clock. 35.4.3 resets 35.5 interrupts this block does not generate any interrupt events. 35.6 low power modes the ec subsystem registers may be put into a low power state by the ch ip?s power, clocks, an d reset (pcr) circuitry. when this block is commanded to sleep it will still allow read/write access to the registers. 35.7 description the ec subsystem registers block is a block implement ed for aggregating miscellaneous registers required by the embedded controller (ec) subsystem that are not unique to a block implemented in the ec subsystem. 35.8 ec-only registers note 35-1 the base address indicates where the first regist er can be accessed in a particular address space for a block instance. table 35-1: power sources name description vcc1 the ec subsystem registers are all implemented on this single power domain. table 35-2: reset signals name description vcc1_reset this reset signal, which is an input to this block, resets all the logic and registers to their initial default state. table 35-3: ec-only register base address table block instance instance number host address space base address ( note 35-1 ) ec_reg_bank 0 ec 32-bit internal address space 4000_fc00h
? 2014 - 2015 microchip technology inc. ds00001719d-page 379 MEC1322 35.8.1 ahb error control 35.8.2 interrupt control table 35-4: runtime register summary offset register name 04h mchp reserved 08h mchp reserved 0ch mchp reserved 10h mchp reserved 14h ahb error control 18h interrupt control 1ch etm trace enable 20h jtag enable 24h mchp reserved 28h wdt event count 2ch mchp reserved 30h mchp reserved 34h mchp reserved 38h adc vref pd 3ch mchp reserved 40h mchp reserved offset 14h bits description type default reset event 7:1 reserved r - - 0 ahb_error_disable 0: ec memory exceptions are enabled. 1: ec memory exceptions are disabled. rw 0h vcc1_r eset offset 18h bits description type default reset event 31:1 reserved r - - 0 nvic_en this bit enables alternate nvic irq?s vectors. the alternate nvic vectors provides each interrupt even t with a dedicated (direct) nvic vector. 0 = alternate nvic vectors disabled 1= alternate nvic vectors enabled r/w 1b vcc1_r eset
MEC1322 ds00001719d-page 380 ? 2014 - 2015 microchip technology inc. 35.8.3 etm trace enable 35.8.4 jtag enable 35.8.5 wdt event count offset 1ch bits description type default reset event 31:1 reserved r - - 0 trace_en this bit enables the arm trace debug port (etm/itm). the trace debug interface pins are forced to the trace functions. 0 = arm trace port disabled 1= arm trace port enabled r/w 0b vcc1_r eset offset 20h bits description type default reset event 31:1 reserved r - - 0jtag_en this bit enables the jtag debug port. 0 = jtag port disabled. jtag cannot be enabled (i.e., the trst# pin is ignored and the jtag signals remain in their non-jtag state). 1= jtag port enabled. a high on trst# enables jtag r/w 0b vcc1_r eset offset 28h bits description type default reset event 31:4 reserved r - - 3:0 wdt_count these ec r/w bits are cleared to 0 on vcc1 por, but not on a wdt. note: this field is written by boot rom firmware to indicate the number of times a wdt fired before loading a good ec code image. r/w 0b vcc1_r eset
? 2014 - 2015 microchip technology inc. ds00001719d-page 381 MEC1322 35.8.6 adc vref pd offset 38h bits description type default reset event 31:1 reserved r - - 0 adc_vref_pd_ref adc vref power down 0=on 1=off r/w 0b vcc1_r eset
MEC1322 ds00001719d-page 382 ? 2014 - 2015 microchip technology inc. 36.0 test mechanisms 36.1 introduction this section defines the xnor chain for board test. other test mechanisms for the arm are described in chapter 7.0, "arm m4f based embedded controller" . 36.2 xnor chain 36.2.1 overview the xnor chain test mode provides a means to confirm that all MEC1322 pins are in contact with the motherboard during assembly and test operations. an example of an xnor chain test structure is illustrated below in 36.2.3figure 36-1 . when the xnor chain test mode is enabled all pins, except for the excluded pins shown in section 36.2.2 , are disconnected from their internal functions and forced as inputs to the xnor chain. this allows a single input pin to toggle the xnor chain output if all other input pins are held high or low. the xnor chain output is the test output pin, pin 17: kso04/gpio103/tfdp_- data/xnor . the tests that are performed when the xnor chain test mode is enabled require the board-level test hardware to con- trol the device pins and observe the results at the xnor chain output pin; e.g., as described in section 36.2.3, "test procedure," on page 383 . 36.2.2 excluded pins all pins in the pinout are included in the xnor chain, except the following: ? power pins (vcc1, avcc, vbat, vref_peci) ? ground pins (vss, avss, vss_vbat) ?cap ? crystal pins (xtal1, xtal2) ? test output pin, pin 17: kso04/gpio103/tfdp_data/xnor ? test port (jtag_rst#, kso02/gpio101/jtag_tdi, kso03/gpio102/jtag_tdo, kso01/gpio100/jtag_tms, an d kso00/gpio000/jtag_tck) figure 36-1: xnor chain test structure i/o#1 i/o#2 i/o#3 i/o#n xnor out
? 2014 - 2015 microchip technology inc. ds00001719d-page 383 MEC1322 36.2.3 test procedure 36.2.3.1 setup warning: ensure power supply is off during setup. 1. connect jtag_rst# to ground. 2. connect the vss, avss, vss_vbat pins to ground. 3. connect the vcc1, avcc, vbat pins to an unpowered 3.3v power source. 4. connect the vref_peci pin to an unpowered 1.8v power source. 5. connect an oscilloscope or volt meter to the test output pin. 6. all other pins should be tied to ground. 36.2.3.2 testing 1. turn on the 3.3v power source. 2. enable the xnor chain as defined in section 36.2.3.3, "procedure to enable the xnor chain" . 3. bring one pin in the chain high. the output on the test output pin, pin 17: kso04/gpio103/tfdp_- data/xnor pin should toggle. then individually toggle each of the remaining pins in the chain. each time an input pin is toggled either high or low the test output pin, pin 17: kso04/gpio103/tfdp_data/xnor pin should toggle. 4. once the xnor test is comp leted, exit the xnor chain test mode by cycling vcc1 power. 36.2.3.3 procedure to en able the xnor chain //begin procedure to enter xnor chain /////////////////////////////////// //reset test interface /////////////////////////////////// force jtag_rst# = 0 force kso00/gpio000/jtag_tck = 0 force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1 wait 100 ns //////////////////////////////// //come out of reset //////////////////////////////// force trst#/jtag_rst# = 1 wait 100 ns force kso00/gpio000/jtag_tck = 1 force kso00/gpio000/jtag_tck = 0 force kso00/gpio000/jtag_tck = 1 note: there are 101 pins in the xnor chain. note: at this point all inputs to the xnor chain are low, except for the jtag_rst# pin, and the output on the test output pin is non-inverted from its initial state, which is dependent on the number of pins in the chain. if the number of input pins in the chain is an even number, the initial state of the test output pin, pin 17: kso04/gpio103/tfdp_data/xnor is low. if the number of input pins in the chain is an odd number, the initial state of the test output pin, pin 17: kso04/gpio103/tfdp_data/xnor is high.
MEC1322 ds00001719d-page 384 ? 2014 - 2015 microchip technology inc. force kso00/gpio000/jtag_tck = 0 force kso00/gpio000/jtag_tck = 1 force kso00/gpio000/jtag_tck = 0 force kso00/gpio000/jtag_tck = 1 force kso00/gpio000/jtag_tck = 0 //////////////////////////////// //sequence 1 // write ir with 7h //////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //1n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //2n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //3n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //4n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //5n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 ////////////////////////////////////// //shift ir 0x7h ///////////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //6n force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //7n force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //8n
? 2014 - 2015 microchip technology inc. ds00001719d-page 385 MEC1322 force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //9n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1; //next will be exit1_ir force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //10n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1; //next will be update_ir force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //11n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0; //next will be idle force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //12n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0; //next will be idle wait 0 ns ////////////////////////////////////////////////////////// // sequence 2 // dir=0, cmd[2:0]=1, data[7:0]=01\h, addr[7:0]=88\h ////////////////////////////////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //1n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //2n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //3n force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 /////////////////////////////////////////// //dir 0 - write ////////////////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //n (dr1) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0
MEC1322 ds00001719d-page 386 ? 2014 - 2015 microchip technology inc. /////////////////////////////////////////// //cmd 1 - test ////////////////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr2) force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr3) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr4) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 /////////////////////////////////////////// //data 0x01 - xnor_en ////////////////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr5) force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr6) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr7) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr8) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p
? 2014 - 2015 microchip technology inc. ds00001719d-page 387 MEC1322 **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr9) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr10) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr11) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr12) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 ////////////////////////////////////////////////////////////// //address 0x88 - cu stomer control ///////////////////////////////////////////////////////////// force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr13) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr14) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr15) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr16) force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p
MEC1322 ds00001719d-page 388 ? 2014 - 2015 microchip technology inc. **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr17) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 1//`tp_gpio102.check(1); force kso00/gpio000/jtag_tck = 0; //n (dr18) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr19) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (dr20) force kso02/gpio101/jtag_tdi = 1 force kso01/gpio100/jtag_tms = 1 force kso00/gpio000/jtag_tck = 1; //p **verify kso03/gpio102/jtag_tdo = 0//`tp_gpio102.check(0); force kso00/gpio000/jtag_tck = 0; //n (e1_dr) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 1 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //n (up_dr) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //n (extra clk) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 force kso00/gpio000/jtag_tck = 1; //p force kso00/gpio000/jtag_tck = 0; //n (extra clk) force kso02/gpio101/jtag_tdi = 0 force kso01/gpio100/jtag_tms = 0 wait 100 ns //////////////////////////////////////////////////////////////////////////// //finished procedure to enter xnor ///////////////////////////////////////////////////////////////////////////
? 2014 - 2015 microchip technology inc. ds00001719d-page 389 MEC1322 37.0 electrical specifications 37.1 maximum ratings* *stresses exceeding those listed could cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at any other condition above thos e indicated in the operation sections of this specification is not implied. 37.1.1 absolute maximu m thermal ratings 37.1.2 absolute maximum supply voltage ratings 37.1.3 absolute maximum i/o voltage ratings note 37-1 the power supply used to power the buffer is shown in the signal power well column of the pin multiplexing tables in section 1.0 ?pin configuration? . 37.2 operational specifications 37.2.1 power supply operat ional characteristics note: when powering this device from laboratory or system power supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is sug gested that a clamp circuit be used. table 37-1: absolute maximum thermal ratings parameter maximum limits operating temperature range 0 o c to +70 o c commercial -40 o c to +85 o c industrial storage temperature range -55 o to +150 o c lead temperature range refer to jedec spec j-std-020b table 37-2: absolute power supply ratings symbol parameter maximum limits vbat 3.0v battery backup power supply with respect to ground -0.3v to +3.63v vcc1 3.3v suspend power supply with respect to ground -0.3v to +3.63v vcc2 3.3v main power supply with respect to ground -0.3v to +3.63v parameter maximum limits voltage with respect to ground on any pin without back- drive protection -0.3v to (power supply used to power the buffer) + 0.3v ( note 37-1 ) table 37-3: power supply operating conditions symbol parameter min typ max units vbat battery backup power supply 2.0 3.0 3.6 v vcc1 suspend power supply 3.135 3.3 3.465 v note: the specification for the vcc1 supply is +/- 5%.
MEC1322 ds00001719d-page 390 ? 2014 - 2015 microchip technology inc. 37.2.2 ac electric al specifications the clock rise and fall times use the standard input thresholds of 0.8v and 2.0v unless otherwise specified and the capacitive values listed in section 37.2.2, "ac electrical specifications," on page 390 . 37.2.3 capacitive loading specifications the following table defines the maximum capacitive load validated for the buffer characteristics listed in table 37-4, ?dc electrical characteristics,? on page 391 . capacitance t a = 25c; fc = 1mhz; v cc = 3.3 vdc note 37-2 the pci buffers are designed to meet the defined pc i local bus specification, rev. 2.1, electrical requirements. note 37-3 all input buffers can be characterized by this capacitance unless otherwise specified. note 37-4 all output buffers can be characterized by this capacitance unless otherwise specified. note: all output pins, except pin under test, tied to ac ground. parameter symbol limits unit notes min typ max input capacitance of pci_i and pci_io pins c in note 37-2 pf input capacitance of pci_clk pin c in note 37-2 pf output load capacitance supported by pci_io, pci_o, and pci_od c out note 37-2 pf susclk input capacitance c in 10 pf input capacitance of peci_i and peci_io c in 10 pf output load capacitance supported by peci_io and od_ph c out 10 pf input capacitance (all other input pins) c in 10 pf note 37-3 output capacitance (all other output pins) c out 20 pf note 37-4
? 2014 - 2015 microchip technology inc. ds00001719d-page 391 MEC1322 37.2.4 dc electrical characteristics for i/o buffers table 37-4: dc electrical characteristics parameter symbol min typ max units comments pio type buffer all pio buffers pull-up current pull-down current i pu i pd 39 39 84 65 162 105 a a internal pu/pd selected via the gpio pin control register. i type input buffer low input level high input level to l e r a n c e schmitt trigger hyster- esis v ili v ihi v hys 0.7x vcc1 400 0.3x vcc1 3.63 v v v mv ttl compatible schmitt trigger input this buffer is not 5v tolerant. o-2 ma type buffer low output level high output level to l e r a n c e v ol v oh vcc1- 0.4 0.4 v v i ol = 2 ma i oh = -2 ma this buffer is not 5v tolerant. io-2 ma type buffer _ _ _ _ _ same characteristics as an i and an o- 2ma. od-2 ma type buffer low output level to l e r a n c e v ol 0.4 v v ol = 2 ma this buffer is not 5v tolerant. iod-2 ma type buffer _ _ _ _ _ same characteristics as an i and an od-2ma. o-4 ma type buffer low output level high output level to l e r a n c e v ol v oh vcc1- 0.4 0.4 v v i ol = 4 ma i oh = -4 ma this buffer is not 5v tolerant. io-4 ma type buffer _ _ _ _ _ same characteristics as an i and an o- 4ma. od-4 ma type buffer low output level to l e r a n c e v ol 0.4 v v ol = 4 ma this buffer is not 5v tolerant. iod-4 ma type buffer _ _ _ _ _ same characteristics as an i and an od-4ma.
MEC1322 ds00001719d-page 392 ? 2014 - 2015 microchip technology inc. o-8 ma type buffer low output level high output level to l e r a n c e v ol v oh vcc1- 0.4 0.4 v v i ol = 8 ma i oh = -8 ma this buffer is not 5v tolerant. io-8 ma type buffer _ _ _ _ _ same characteristics as an i and an o- 8ma. od-8 ma type buffer low output level to l e r a n c e v ol 0.4 v v ol = 8 ma this buffer is not 5v tolerant. iod-8 ma type buffer _ _ _ _ _ same characteristics as an i and an od-8ma. o-12 ma type buffer low output level high output level to l e r a n c e v ol v oh vcc1- 0.4 0.4 v v i ol = 12ma i oh = -12ma this buffer is not 5v tolerant. io-12 ma type buffer _ _ _ _ _ same characteristics as an i and an o- 12ma. od-12 ma type buffer low output level to l e r a n c e v ol 0.4 v i ol = 12ma this buffer is not 5v tolerant. iod-12 ma type buffer _ _ _ _ _ same characteristics as an i and an od-12ma. i_an type buffer i_an type buffer (analog input buffer) i_an voltage range on pins: -0.3v to +3.63v these buffers are not 5v tolerant buffers and they are not backdrive pro- tected table 37-4: dc electrical characteristics (continued) parameter symbol min typ max units comments
? 2014 - 2015 microchip technology inc. ds00001719d-page 393 MEC1322 pci_pio type buffer all pci_pio buffers pull-up current i pu 0.611.5ma internal pu is selected via the gpio pin control register. pci_clk type buffer pci_io type buffers pci_od type buffer pci_iclk pci_io pci_o pci_i pci_od see pci local bus specification rev. 2.1 these buffers are not not 5v tolerant buffers and they are not backdrive pro- tected. peci type buffer v ref buffer connects to cpu voltage pin (processor dependent) peci bus voltage v bus 0.95 1.26 v input current idc 100 a input low current ileak -10 +10 a this buffer is not 5v tolerant this buffer is not backdrive protected. peci_i buffer all input and output voltages are a function of vref buffer input. input voltage range vin -0.3 v ref + 0.3 v low input level vil 0.275 v ref v high input level vih 0.725 v ref v this buffer is not 5v tolerant this buffer is not backdrive protected. peci_io all input and output voltages are a function of vref buffer input. see peci specification. input voltage range vin -0.3 v ref + 0.3 v hysteresis vhys 0.1 v ref 0.2 v ref v low input level vil 0.275 v ref v high input level vih 0.725 v ref v low output level vol 0.25 v ref v 0.5ma < iol < 1ma high output level voh 0.75 v ref vioh = -6ma tolerance 3.63 v this buffer is not 5v tolerant this buffer is not backdrive protected. table 37-4: dc electrical characteristics (continued) parameter symbol min typ max units comments
MEC1322 ds00001719d-page 394 ? 2014 - 2015 microchip technology inc. 37.2.4.1 pin leakage leakage characteristics for all pins is shown in the following table: 37.2.4.2 backdrive protection all signal pins are backdrive protected except those listed in the pin configuration chapter as non-backdrive protected. 37.2.5 adc electrical characteristics crystal oscillator xtal1 (oclk) the MEC1322 crystal oscillator design requ ires a 32.768 khz parallel resonant crystal with load caps in the range 4-18pf. refer to ?application note pcb layout guide for MEC1322? for more information. xtal2 (iclk) low input level high input level v ili v ilh 2.0 0.4 v v vin = 0 to vcc1 table 37-5: pin leakage ( t a = 0 o c to +85 o c) parameter symbol min typ max units comments leakage current i il +/-2 a vin=0v to vcc1 table 37-6: backdrive protection ( t a = 0 o c to +85 o c) parameter symbol min typ max units comments input leakage i il -2 +2 a vin=3.47v@vcc1=0v table 37-7: adc characteristics parameter min typ max units analog supply voltage, avcc 3.135 3.3 3.465 v resolution ? ? 10 bits accuracy ? 1 ? lsb differential non linearity, dnl -1 ? +1 lsb integral non linearity, inl -1.5 ? +1.5 lsb gain error, e gain -2 ? 2 lsb offset error, e offset -2 ? 2 lsb conversion time ? ? 12 s/channel input impedance 3 ? ? m note: the avcc power supply accuracy is shown as 3.3v +/- 5%. table 37-4: dc electrical characteristics (continued) parameter symbol min typ max units comments
? 2014 - 2015 microchip technology inc. ds00001719d-page 395 MEC1322 37.3 thermal characteristics 37.4 power consumption table 37-8: thermal operating conditions rating symbol min. typical max. unit consumer temperature devices operating junction temperature range t j ? ? +125 c operating ambient temperature range - commercial t a 0?+70c operating ambient temperature range - industrial t a -40 ? +85 c power dissipation: internal chip power dissipation: p int = v cc 1 x i vcc 1 from table 37-10 (e.g., 3.45v x 9.75ma = 33.64mw) i/o pin power dissipation: i/o = s (({v cc 1 ? v oh } x i oh ) + s (v ol x i ol )) p d p int + p i / o w maximum allowed power dissipation p dmax (t j ? t a )/ ja w table 37-9: thermal packaging characteristics characteristics symbol typical max. unit notes package thermal resistance, 128-pin vtqfp ja 51.0 ? c/w 1 jc 25.0 ? c/w 1 package thermal resistance, 132-pin dqfn ja 28.0 ? c/w 1 jc 5.0 ? c/w 1 package thermal resistance, 144-pin wfbga ja 50.0 ? c/w 1 jc 17.0 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) and junction to case thermal resistance, theta- jc ( jc ) numbers are achieved by package simulations. table 37-10: vcc1 supply current, i_vcc1 vcc2 vcc1 system state 48 mhz ring oscillator frequency typical (3.3v, 25 0 c) max (3.465v, 70 0 c) max (3.465v, 85 0 c) units comments on on s0 48mhz 8.50 9.75 10.25 ma full on, 48mhz, lpc clock on on on s0 12mhz 6.00 8.00 8.50 ma full on, 12mhz, lpc clock on on on s0 3mhz 5.50 7.00 7.50 ma full on, 3mhz, lpc clock on on on s0 1mhz 5.00 6.50 7.00 ma full on, 1mhz, lpc clock on on on s0 12mhz 3.00 3.70 4.25 ma heavy sleep 1, lpc clock on on on s0 off 0.80 1.50 2.10 ma heavy sleep 2, lpc clock on on on s0 off 0.50 1.25 1.85 ma heavy sleep 3, lpc clock on off on s5 48mhz 7.75 9.25 9.75 ma full on (48mhz), lpc clock off
MEC1322 ds00001719d-page 396 ? 2014 - 2015 microchip technology inc. note 37-1 the sleep states are defined in the system sleep control register in the power, clocks and resets chapter. see table 3-10, ?system sleep control bit encoding,? on page 61 . off on s5 12mhz 5.25 7.00 7.50 ma full on (12mhz), lpc clock off off on s5 3mhz 4.75 6.25 6.75 ma full on (3mhz), lpc clock off off on s5 1mhz 4.50 6.00 6.50 ma full on (1mhz), lpc clock off off on s5 12mhz 2.00 2.75 3.25 ma heavy sleep 1, lpc clock off ( note 37-1 ) off on s5 off 0.65 1.25 1.65 ma heavy sleep 2, lpc clock off ( note 37-1 ) off on s5 off 0.33 0.95 1.55 ma heavy sleep 3, lpc clock off ( note 37-1 ) off on s5 off 0.30 0.90 1.50 ma deepest sleep, lpc clock off ( note 37-1 ) note: full on is defined as follo ws: the processor is not sleeping, the core regulator an d the ring oscillator remain powered, and at least one block is not sleeping. table 37-11: vbat supply current, i_vbat (vbat=3.0v) vcc2 vcc1 system state 48 mhz ring oscillator frequency typical (3.0v, 25 0 c) max (3.0v, 70 0 c) max (3.0v, 85 0 c) units comments off off s5 off 2.50 6.50 9.00 ua 32khz crystal oscillator off off s5 off 2.00 6.00 8.50 ua external 32khz clock on xtal2 pin table 37-12: vbat supply cu rrent, i_vbat (vbat=3.3v) vcc2 vcc1 system state 48 mhz ring oscillator frequency typical (3.3v, 25 0 c) max (3.3v, 70 0 c) max (3.3v, 85 0 c) units comments off off s5 off 2.75 6.75 9.25 ua 32khz crystal oscillator off off s5 off 2.50 6.25 8.75 ua external 32khz clock on xtal2 pin table 37-10: vcc1 supply current, i_vcc1 (continued) vcc2 vcc1 system state 48 mhz ring oscillator frequency typical (3.3v, 25 0 c) max (3.465v, 70 0 c) max (3.465v, 85 0 c) units comments
? 2014 - 2015 microchip technology inc. ds00001719d-page 397 MEC1322 38.0 timing diagrams 38.1 voltage thresholds and power good timing 38.1.1 vcc1_rst# timing figure 38-1: vcc1_rst# timing note 38-1 the arm starts executing instru ctions when ec_proc_ reset deasserts, which has the same timing as t3. figure 38-2: vcc1_rst# rise time note 38-2 this corresponds to the time 2.65us (min) after the vcc1_rst# pin is released, the vcc1_rst# pin input is sampled. see section 3.6.1, "integrated vcc1 power on reset (vcc1_rst#)," on page 53 . note: timing values are preliminary and may change after characterization. table 38-1: vcc1_rst# timing parameters symbol min typ max unit notes vcc1 threshold for pin glitch protection active v th1 0.9 1 1.1 v vcc1 power good threshold v th2 2.16 2.4 2.64 v vcc1 rise time (off to vcc1 =v threshold )v rise 200 s vcc1 fall time (vcc1 =v threshold ) to off v fall 200 s vcc1 > v th2 to vcc1gd (internal) asserted t1 600 s vcc1 < v th2 to vcc1gd (internal) deas- serted and vcc1_rst# pin asserted t2 100 ns vcc1 > v th2 to vcc1_rst# pin deasserted t3 1 ms note 38-1 table 38-2: vcc1_rst# rise time parameters symbol min typ max units notes vcc1_rst# rise time t1 2.65 s note 38-2 undefined functional t1 forced to logic ?0? forced to logic ?0? vcc1gd (internal) glitch protected signal output vcc1 undefined t2 v th2 v th2 v th1 v th1 vcc1_rst# pin t3 vcc1_rst# pin t1
MEC1322 ds00001719d-page 398 ? 2014 - 2015 microchip technology inc. 38.1.2 vbat thresholds and vbat_por note 38-3 vbat is monitored on two events: coin cell insertion and vcc1gd assertion. if vbat is below vth when vcc1gd is asserted a vbat_por is generated. 38.2 clocking ac timing characteristics figure 38-4: clock timing diagram figure 38-3: vbat thresholds and vbat_por table 38-3: vbat thresholds and vbat_por parameters symbol min typ max units notes vbat power on reset threshold v th 1.125 1.25 1.375 v note 38-3 vbat rise time (off to vbat =v threshold ) v rise 100 s vbat vcc1gd vbat_por coin cell insertion vbat ? 2014 - 2015 microchip technology inc. ds00001719d-page 399 MEC1322 note 38-4 this time only applies if the external 32khz clock input is available. note 38-5 susclk is required to have an accuracy of +/- 100 ppm. note 38-6 the drift in frequency after frequency lock if the 32khz clock is removed is determined by varying temperature while voltage is held constant. table 38-4: clock timing parameters clock parameters symbol min typ max units 48 mhz ring oscillator start-up accuracy (without 32 khz present) f su 22 - 53 mhz start-up delay from 0 mhz to start- up accuracy t su --6s operating frequency (with 32 khz present after frequency lock to 48 mhz) f op 47.04 48 48.95 mhz adjustment delay from start-up accuracy to operating accuracy (time to attain frequency lock - with 32 khz present) t adj 0.03 - 4 ( note 38-4 ) ms operating frequency (with 32 khz removed after frequency locked to 48 mhz) f op 43.2 ( note 38-6 ) -52.8 ( note 38-6 ) mhz susclk operating frequency - - 32.768 - khz period - ( note 38-5 ) 30.52 ( note 38-5 )s high time - 10 us low time - 10 us fall time - - - 1 us rise time - - - 1 us
MEC1322 ds00001719d-page 400 ? 2014 - 2015 microchip technology inc. 38.3 gpio timings figure 38-5: gpio timing table 38-5: gpio timing parameters symbol parameter min typ max unit notes t r gpio rise time (push-pull) 0.54 1.31 ns pad type = io2 c l =2pf t f gpio fall time 0.52 1.27 ns t r gpio rise time (push-pull) 0.58 1.46 ns pad type = io4 c l =5pf t f gpio fall time 0.62 1.48 ns t r gpio rise time (push-pull) 0.80 2.00 ns pad type = io8 c l =10pf t f gpio fall time 0.80 1.96 ns t r gpio rise time (push-pull) 1.02 2.46 ns pad type = io12 c l =20pf t f gpio fall time 1.07 2.51 ns t pulse gpio pulse width 60 ns gpioxxx tr tf tpulse tpulse
? 2014 - 2015 microchip technology inc. ds00001719d-page 401 MEC1322 38.4 lpc lclk timing figure 38-6: lpc clock timing note 38-7 the standard clock frequency supported is 33mhz (max 33.3ns period). setting the handshake bit in the host interface allows the lpc interface to support a pci clock rate from 19.2mhz to 33mhz. 38.5 lpc reset# timing figure 38-7: reset timing 38.5.1 lpc bus timing figure 38-8: output timing meas urement conditions, lpc signals table 38-6: lpc cloc k timing parameters name description min typ max units t1 period 30 57 ( note 38- 7 ) nsec t2 high time 11 t3 low time t4 rise time 3 t5 fall time table 38-7: reset timing parameters name description min typ max units t1 lreset# width 1 ms t1 t3 t2 lclk t5 t4 t1 lreset# t3 t2 t1 lclk output delay tri-state outpu t
MEC1322 ds00001719d-page 402 ? 2014 - 2015 microchip technology inc. 38.5.2 lpc input timing figure 38-9: input timing measurement conditions, lpc signals 38.5.3 lpc i/o timing figure 38-10: i/o write figure 38-11: i/o read table 38-8: output timing measurement conditions, lpc signals parameters name description min typ max units t1 lclk to signal valid delay ? bused signals 2 11 ns t2 float to active delay t3 active to float delay 28 table 38-9: input timing measurement conditions, lpc signals parameters name description min typ max units t1 input set up time to lclk ? bused signals 7 ns t2 input hold time from lclk 0 note: l1=start; l2=cyctyp+dir; l3=sync of 0000 note: l1=start; l2=cyctyp+dir; l3=sync of 0000 inputs valid t2 t1 lclk input l1 l2 a ddress data tar sync=0110 l3 tar lclk lframe# lad[3:0]# l1 l2 a ddress tar sync=0110 l3 data tar lclk lframe# lad[3:0]#
? 2014 - 2015 microchip technology inc. ds00001719d-page 403 MEC1322 38.5.4 serial irq timing figure 38-12: setup and hold time table 38-10: setup and hold time name description min typ max units t1 ser_irq setup time to lclk rising 7 nsec t2 ser_irq hold time to lclk rising 0 t2 t1 lclk ser_ irq
MEC1322 ds00001719d-page 404 ? 2014 - 2015 microchip technology inc. 38.6 serial port (uart) data timing figure 38-13: serial port data note 38-8 tbr is 1/baud rate. the baud rate is programmed through the baud_rate_divisor bits located in the programmable baud rate generator registers. the selectable baud rates are listed in table 14- 7, "uart baud rates using clock source 1.8432mhz_clk" and table 14-8, "uart baud rates using clock source 24mhz_clk" . some of the baud rates have some percentage of error because the clock does not divide evenly. this error can be determined from the values in these baud rate tables. table 38-11: serial port data parameters name description min typ max units t1 serial port data bit time t br ( note 3 8-8 ) nsec data (5-8 bits) t1 data txd1, 2 start parity stop (1-2 bits)
? 2014 - 2015 microchip technology inc. ds00001719d-page 405 MEC1322 38.7 peci interface note 38-9 the originator must drive a more restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500 sec. t bit limits apply equally to t bit-a and t bit-m . the MEC1322 is designed to support 2 mhz, or a 500ns bit time. see the peci 3.0 specification from intel corp. for further details. note 38-10 the minimum and maximum bit times are relative to t bit defined in the timing negotiation pulse. see the peci 3.0 specification from intel corp. for further details. note 38-11 ?#nodes? is the number of nodes on the peci bus; host and client nodes are counted as one each. extended trace lengths may appear as extra nodes. refer also to table 23-2, "peci routing guidelines" . see the peci 3.0 specification from intel corp. for further details. table 1.1 name description min max units notes t bit bit time (overall time evident on peci pin) bit time driven by an originator 0.495 0.495 500 250 sec sec note 38-9 t bit,jitter bit time jitter between adjacent bits in a peci mes- sage header or data bytes after timing has been negotiated --% t bit,drift change in bit time across a peci address or peci message bits as driven by the originator. this limit only applies across t bit-a bit drift and t bit-m drift. --% t h1 high level time for logic 1 0.6 0.8 t bit note 38- 10 t h0 high level time for logic 0 0.2 0.4 t bit t pecir rise time (measured from v ol to v ih,min , vtt (nom) ? 5%) -30 + (5 x #nodes) ns note 38- 11 t pecif fall time (measured from v oh to v il,max , vtt (nom) +5%) - (30 x #nodes) ns note 38- 11
MEC1322 ds00001719d-page 406 ? 2014 - 2015 microchip technology inc. 38.8 8042 emulation cpu_reset timing figure 38-14: cpu_reset timing note 38-12 figure 38-14 and table 38-12 refer to figure 11-5: cpu_reset implementation diagram on page 152 in which cpu_reset is the inverse of alt_rst# & kreset. note 38-13 the kbrst pin function is the ou tput of cpu_r eset described in section 11.11.2, "cpu_reset hardware speed-up," on page 151 . table 38-12: cpu_reset timing parameters name description min typ max units t delay delay prior to active pulse 14 15 15.5 s t active active pulse width 6 8 8.5 s t delay t active
? 2014 - 2015 microchip technology inc. ds00001719d-page 407 MEC1322 38.9 keyboard scan matrix timing table 38-13: active pre drive mode timing parameter symbol value units min typ max active predrive mode t predrive 40.87 41.7 42.5 ns
MEC1322 ds00001719d-page 408 ? 2014 - 2015 microchip technology inc. 38.10 ps/2 timing figure 38-15: ps/2 transmit timing table 38-14: ps/2 channel transmission timing parameters name description min typ max units t1 the ps/2 channel?s clk and data lines are floated following ps2_en=1 and ps2_t/r=0. 1000 ns t2 ps2_t/r bit set to clk driven low prepar- ing the ps/2 channel for data transmis- sion. t3 clk line floated to xmit_idle bit de- asserted. 1.7 t4 trailing edge of wr to transmit register to data line driven low. 45 90 t5 trailing edge of ec wr of transmit regis- ter to clk line floated. 90 130 ns t6 initiation of start of transmit cycle by the ps/2 channel controller to the auxiliary peripheral?s responding by latching the start bit and driving the clk line low. 0.002 25.003 ms t7 period of clk 60 302 s t8 duration of clk high (active) 30 151 t9 duration of clk low (inactive) t10 duration of data frame. falling edge of start bit clk (1st clk) to falling edge of par- ity bit clk (10th clk). 2.002 ms 1 2 10 11 b0 b1 b2 b3 b4 b5 b6 b7 p s ps2_clk ps2_dat ps2_en ps2_t/r xmit_idle rdata_rdy write tx reg interrupt t1 t2 t4 t3 t5 t6 t7 t9 t8 t10 t11 t12 t13 t14 t15 note 1 t17
? 2014 - 2015 microchip technology inc. ds00001719d-page 409 MEC1322 t11 data output by MEC1322 following the falling edge of clk. the auxiliary periph- eral device samples data following the ris- ing edge of clk. 1.0 s t12 rising edge following the 11th falling clock edge to ps_t/r bit driven low. 3.5 7.1 s t13 trailing edge of ps_t/r to xmit_idle bit asserted. 500 ns t14 data released to high-z following the ps2_t/r bit going low. t15 xmit_idle bit driven high to interrupt gen- erated. note1- interrupt is cleared by writing a 1 to the status bit in the girq17 source regis- ter. t17 trailing edge of clk is held low prior to going high-z figure 38-16: ps/2 receive timing table 38-14: ps/2 channel transmission timing parameters (continued) name description min typ max units t6 t5 t4 t3 t2 t7 t1 t8 t9 t10 t12 t11 rdata_rdy interrupt ps2_en read rx reg d3 d0 d2 d5 d4 d6 d7 p s d1 ps2_data ps2_clk ps2_t/r
MEC1322 ds00001719d-page 410 ? 2014 - 2015 microchip technology inc. table 38-15: ps/2 channel receive timing diagram parameters name description min typ max units t1 the ps/2 channel?s clk and data lines are floated following ps2_en=1 and ps2_t/r=0. 1000 ns t2 period of clk 60 302 s t3 duration of clk high (active) 30 151 t4 duration of clk low (inactive) t5 data setup time to falling edge of clk. MEC1322 samples the data line on the fall- ing clk edge. 1 t6 data hold time from falling edge of clk. MEC1322 samples the data line on the fall- ing clk edge. 2 t7 duration of data frame. falling edge of start bit clk (1st clk) to falling edge of par- ity bit clk (10th clk). 2.002 ms t8 falling edge of 11th clk to rdata_rdy asserted. 1.6 s t9 trailing edge of the ec?s rd signal of the receive register to rdata_rdy bit de- asserted. 500 ns t10 trailing edge of the ec?s rd signal of the receive register to the clk line released to high-z. t11 ps2_clk is "low" and ps2_data is "hi- z" when ps2_en is de-asserted. t12 rdata_rdy asserted an interrupt is gen- erated.
? 2014 - 2015 microchip technology inc. ds00001719d-page 411 MEC1322 38.11 pwm timing figure 38-17: pwm output timing table 38-16: pwm timing parameters name description min typ max units t1 period 42ns 23.3sec t f frequency 0.04hz 24mhz t2 high time 0 11.65 sec t3 low time 0 11.65 sec t d duty cycle 0 100 % t3 t1 t2 pwmx
MEC1322 ds00001719d-page 412 ? 2014 - 2015 microchip technology inc. 38.12 fan tachometer timing note: t tach is the clock used for the tachometer counter. it is 30.52 * prescaler, where the prescaler is pro- grammed in the fan tachometer timebase prescaler register. figure 38-18: fan tachometer input timing table 38-17: fan tachometer input timing parameters name description min typ max units t1 pulse time 100 sec t2 pulse high time 20 t3 pulse low time 20 t3 t1 t2 fan_tachx
? 2014 - 2015 microchip technology inc. ds00001719d-page 413 MEC1322 38.13 blinking/breathing pwm timing figure 38-19: blinking/breathing pwm output timing table 38-18: blinking/breathing pwm timing parameters, blinking mode name description min typ max units t1 period 7.8ms 32sec t f frequency 0.03125 128 hz t2 high time 0 16 sec t3 low time 0 16 sec t d duty cycle 0 100 % table 38-19: blinking/breathing pwm timing parameters, general purpose name description min typ max units t1 period 5.3us 21.8ms t f frequency 45.8hz 187.5khz t2 high time 0 10.9 ms t3 low time 0 10.9 ms t d duty cycle 0 100 % t3 t1 t2 ledx
MEC1322 ds00001719d-page 414 ? 2014 - 2015 microchip technology inc. 38.14 i 2 c/smbus timing figure 38-20: i 2 c/smbus timing table 38-20: i 2 c/smbus timing parameters symbol parameter standard- mode fast- mode fast- mode plus units min. max. min. max. min. max. f scl scl clock frequency 100 400 1000 khz t buf bus free time 4.7 1.3 0.5 s t su ; sta start condition set-up time 4.7 0.6 0.26 s t hd ; sta start condition hold time 4.0 0.6 0.26 s t low scl low time 4.7 1.3 0.5 s t high scl high time 4.0 0.6 0.26 s t r scl and sda rise time 1.0 0.3 0.12 s t f scl and sda fall time 0.3 0.3 0.12 s t su ; dat data set-up time 0.25 0.1 0.05 s t hd ; dat data hold time 0 0 0 s t su ; sto stop condition set-up time 4.0 0.6 0.26 s t hd;st a t su;st o t su;st a t su;da t t high t f t r t lo w t hd;dat t hd;st a t bu f i2c_dat a i2c_cl k
? 2014 - 2015 microchip technology inc. ds00001719d-page 415 MEC1322 38.15 bc-link master interrupt timing 38.16 bc-link master timing figure 38-21: bc-link err interrupt timing figure 38-22: bc-link read timing busy bc_err bc_err interrupt bc_busy_clr interrupt (controlled by hardware) approxinatley 48 bc clocks bit n t ih bit n-1 bc_dat bc_clk t is t c bit read
MEC1322 ds00001719d-page 416 ? 2014 - 2015 microchip technology inc. note 1: the bc-link master data input (t ih in table 38-21 ) must be stable before next rising edge of clk. 2: the bc-link clock frequency is limited by the application usage model (see bc-link master section 31.5, signal description ). the bc-link clock frequency is controlled by the bc-link clock select register. the tc(high speed) parameter implies both bc-link master and companion devices are located on the same cir- cuit board and a high speed clock setting is possible. figure 38-23: bc-link write timing table 38-21: bc-link master timing diagram parameters name description min typ max units t c (high speed) high spec bc clock frequency 23.5 24 24.5 mhz high spec bc clock period 40.8 41.67 42.5 ns t os bc-link master data output setup time before rising edge of clk. t c -t oh- max nsec t oh bc-link master data hold time after falling edge of clk 10 nsec t is bc-link master data input setup time before rising edge of clk. 15 nsec t ih bc-link master data input hold time after rising edge of clk. 0nsec note: the timing budget equation is as follows for data from bc-link slave to master: tc > tod(master-clk) + tprop(clk) +tod(s lave) + tprop(slave data) + tis(master). bit n bit n-1 t c t oh t os bc_dat bc_clk
? 2014 - 2015 microchip technology inc. ds00001719d-page 417 MEC1322 38.17 serial peripheral interface (spi) timings figure 38-24: spi clock timing note 38-14 this timing value applies when the 48mhz ring oscillator is at its 48mhz operating frequency (with 32 khz present after frequency lock to 48mhz). table 38-22: spi clock timing parameters name description min typ max units tr spi clock rise time. measured from 10% to 90%. 10% of spclk period ns tf spi clock fall time. measured from 90% to 10%. 10% of spclk period ns th/tl spi clock high time/spi clock low time 40% of spclk period 50% of spclk period 60% of spclk period ns tp spi clock period ? as selected by spi clock generator register 20.8 ( note 38- 14 ) 62492.25 ns tr tf th tl tp spiclk
MEC1322 ds00001719d-page 418 ? 2014 - 2015 microchip technology inc. figure 38-25: spi setup and hold times, clkpol=0, tclkph=0, rclkph=0 figure 38-26: spi setup and hold times, clkpol=0, tclkph=0, rclkph=1 38.17.1 spi interface timings the following timing diagrams represent a single-byte transfer over the spi interface using different spclk phase set- tings. data bits are transmitted in bi t order starting with the msb (lsbf=? 0?) or the lsb (lsbf=?1?). see the spi control register for information on the lsbf bit. the cs signal in each diagram is a generic bit-controlled chip select signal required by most peripheral devices. th is signal and additional chip selects can be gpio controlled. note that these timings for full duplex mode are also applicable to half duplex (or bi-directional) mode. table 38-23: spi setup and hold times parameters name description min typ max units t1 data output delay 5 ns t2 data in setup time 10 ns t3 data in hold time 0 ns spdin spdout t1 t2 t3 spclk (clkpol = 0, tclkph = 0, rclkph = 0) setup and hold times for full-duplex and bidrectional modes spdin spdout t1 t2 t3 spclk (clkpol = 0, tclkph = 0, rclkph = 1) setup and hold times for full-duplex and bidrectional modes
? 2014 - 2015 microchip technology inc. ds00001719d-page 419 MEC1322 figure 38-27: interface timing, full duplex mode (tclkph = 0, rclkph = 0) . in this mode, data is available immediately when a device is selected and is sampled on the first and following odd spclk edges by the master and slave. figure 38-28: spi interface timing, full duplex mode (tclkph = 1, rclkph = 0) . in this mode, the master requires an initial spclk edge before data is available. the data from slave is available imme- diately when the slave device is selected. the data is samp led on the first and following odd edges by the master. the data is sampled on the second and following even spclk edges by the slave. spclk (clkpol = 0) spclk (clkpol = 1) spdin (rclkph = 0) spdout (tclkph = 0) cs (gpio) last data bit sampled by master and slave first data bit sampled by master and slave spclk (clkpol = 0) spclk (clkpol = 1) spdout (tclkph = 1) spdin (rclkph = 0) cs (gpio) first data bit sampled by slave last data bit sampled by slave first data bit sampled by master last data bit sampled by master
MEC1322 ds00001719d-page 420 ? 2014 - 2015 microchip technology inc. figure 38-29: spi interface timing, full duplex mode (tclkph = 0, rclkph = 1) in this mode, the data from slave is available immediately when the slave device is selected. the slave device requires an initial spclk edge before data is available. the data is sampled on the second and following even spclk edges by the master. the data is sampled on the first and following odd edges by the slave. figure 38-30: spi interface timing - full duplex mode (tclkph = 1, rclkph = 1) in this mode, the master and slave require an initial spclk edge before data is available. data is sampled on the second and following even spclk edges by the master and slave. spclk (clkpol = 0) spclk (clkpol = 1) spdin (rclkph = 1) spdout (tclkph = 0) cs (gpio) first data bit sampled by master last data bit sampled by master first data bit sampled by slave last data bit sampled by slave spclk (clkpol = 0) spclk (clkpol = 1) spdin (rclkph = 1) spdout (tclkph = 1) cs (gpio) first data bit sampled by master and slave last data bit sampled by master and slave
? 2014 - 2015 microchip technology inc. ds00001719d-page 421 MEC1322 38.18 serial debug port timing figure 38-31: serial debug port timing parameters note 38-15 when the clock divider for the embedded controller is an odd number value greater than 2h, then t clk-l = t clk-h + 15 ns. when the clock divider for the embedded controller is 0h, 1h, or an even number value greater than 2h, then t clk-l = t clk-h . table 38-24: serial debug port interface timing parameters name description min typ max units f clk tfdp clock frequency ( note 38-15 )6-24mhz t p tfdp clock period. 1/fclk s t od tfdp data output delay after falling edge of msclk. 5 nsec t oh tfdp data hold time after falling edge of tfdp clock t p - t od nsec t clk-l tfdp clock low time t p /2 - 3 t p /2 + 3 nsec t clk-h tfdp clock high time (see note 38-15 )t p /2 - 3 t p /2 + 3 nsec t od t oh t p t clk-l t clk-h f clk tfdp clock tfdp data
MEC1322 ds00001719d-page 422 ? 2014 - 2015 microchip technology inc. 38.19 jtag interface timing figure 38-32: jtag power-up & asynchronous reset timing figure 38-33: jtag setup & hold parameters table 38-25: jtag interface timing parameters name description min typ max units t su jtag_rst# de-assertion after vcc1 power is applied 5ms t pw jtag_rst# assertion pulse width 500 nsec f clk jtag_clk frequency (see note) 48 mhz t od tdo output delay after fa lling edge of tclk. 5 10 nsec t oh tdo hold time after falling edge of tclk 1 tclk - t od nsec t is tdi setup time before rising edge of tclk. 5 nsec t ih tdi hold time after rising edge of tclk. 5 nsec note: f clk is the maximum frequency to access a jtag register. vcc1 power jtag_rst# t pw f clk t su 2.8v jtag_clk jtag_clk jtag_tdo jtag_tdi t od t ih t is t oh
? 2014 - 2015 microchip technology inc. ds00001719d-page 423 MEC1322 39.0 memory map address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name 0 32k rom 0 32k rom 32k rom 100000 128k sram 0 128k sram 128k sram 40000400 watchdog timer inter- face 0 wdt registers wdt load register 40000404 watchdog timer inter- face 0 wdt registers wdt control register 40000408 watchdog timer inter- face 0 wdt registers wdt kick register 4000040c watchdog timer inter- face 0 wdt registers wdt count register 40000c00 basic timer 0 basic_timer_ec_only timer count 40000c04 basic timer 0 basic_timer_ec_only timer preload 40000c08 basic timer 0 basic_timer_ec_only timer status 40000c0c basic timer 0 basic_timer_ec_only timer interrupt enable 40000c10 basic timer 0 basic_timer_ec_only timer control 40000c20 basic timer 1 basic_timer_ec_only timer count 40000c24 basic timer 1 basic_timer_ec_only timer preload 40000c28 basic timer 1 basic_timer_ec_only timer status 40000c2c basic timer 1 basic_timer_ec_only timer interrupt enable 40000c30 basic timer 1 basic_timer_ec_only timer control 40000c40 basic timer 2 basic_timer_ec_only timer count 40000c44 basic timer 2 basic_timer_ec_only timer preload 40000c48 basic timer 2 basic_timer_ec_only timer status 40000c4c basic timer 2 basic_timer_ec_only timer interrupt enable 40000c50 basic timer 2 basic_timer_ec_only timer control 40000c60 basic timer 3 basic_timer_ec_only timer count 40000c64 basic timer 3 basic_timer_ec_only timer preload 40000c68 basic timer 3 basic_timer_ec_only timer status 40000c6c basic timer 3 basic_timer_ec_only timer interrupt enable 40000c70 basic timer 3 basic_timer_ec_only timer control 40000c80 basic timer 4 basic_timer_ec_only timer count 40000c84 basic timer 4 basic_timer_ec_only timer preload 40000c88 basic timer 4 basic_timer_ec_only timer status 40000c8c basic timer 4 basic_timer_ec_only timer interrupt enable 40000c90 basic timer 4 basic_timer_ec_only timer control 40000ca0 basic timer 5 basic_timer_ec_only timer count 40000ca4 basic timer 5 basic_timer_ec_only timer preload 40000ca8 basic timer 5 basic_timer_ec_only timer status 40000cac basic timer 5 basic_timer_ec_only timer interrupt enable 40000cb0 basic timer 5 basic_timer_ec_only timer control 40001800 smb device interface 0 smb_ec_only status register 40001800 smb device interface 0 smb_ec_only control register
MEC1322 ds00001719d-page 424 ? 2014 - 2015 microchip technology inc. 40001801 smb device interface 0 smb_ec_only reserved 40001804 smb device interface 0 smb_ec_only own address register 40001806 smb device interface 0 smb_ec_only reserved 40001808 smb device interface 0 smb_ec_only data 40001809 smb device interface 0 smb_ec_only reserved 4000180c smb device interface 0 smb_ec_only smbus master command register 40001810 smb device interface 0 smb_ec_only smbus slave command register 40001814 smb device interface 0 smb_ec_only pec register 40001815 smb device interface 0 smb_ec_only reserved 40001818 smb device interface 0 smb_ec_only data_timing2 40001819 smb device interface 0 smb_ec_only reserved 40001820 smb device interface 0 smb_ec_only completion register 40001824 smb device interface 0 smb_ec_only idle scaling register 40001828 smb device interface 0 smb_ec_only configuration register 4000182c smb device interface 0 smb_ec_only bus clock register 4000182e smb device interface 0 smb_ec_only reserved 40001830 smb device interface 0 smb_ec_only block id register 40001831 smb device interface 0 smb_ec_only reserved 40001834 smb device interface 0 smb_ec_only revision register 40001835 smb device interface 0 smb_ec_only reserved 40001838 smb device interface 0 smb_ec_only bit-bang control register 40001839 smb device interface 0 smb_ec_only reserved 4000183c smb device interface 0 smb_ec_only clock sync 40001840 smb device interface 0 smb_ec_only data timing register 40001844 smb device interface 0 smb_ec_only time-out scaling register 40001848 smb device interface 0 smb_ec_only smbus slave transmit buffer register 40001849 smb device interface 0 smb_ec_only reserved 4000184c smb device interface 0 smb_ec_only smbus slave receive buf- fer register 4000184d smb device interface 0 smb_ec_only reserved 40001850 smb device interface 0 smb_ec_only smbus master transmit bufer register 40001851 smb device interface 0 smb_ec_only reserved 40001854 smb device interface 0 smb_ec_only smbus master receive buffer register 40001855 smb device interface 0 smb_ec_only reserved 40002400 dma 0 dma main dma main control register 40002401 dma 0 dma main dma reserved 40002404 dma 0 dma main dma data register 40002410 dma 0 dma_ch0 dma activate register 40002414 dma 0 dma_ch0 dma memory start address register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 425 MEC1322 40002418 dma 0 dma_ch0 dma memory end address register 4000241c dma 0 dma_ch0 ahb address register 40002420 dma 0 dma_ch0 dma control register 40002424 dma 0 dma_ch0 dma channel interrupt status 40002428 dma 0 dma_ch0 dma channel interrupt enable 4000242c dma 0 dma_ch0 dma test register 40002430 dma 0 dma_ch1 dma activate register 40002434 dma 0 dma_ch1 dma memory start address register 40002438 dma 0 dma_ch1 dma memory end address register 4000243c dma 0 dma_ch1 ahb address register 40002440 dma 0 dma_ch1 dma control register 40002444 dma 0 dma_ch1 dma channel interrupt status 40002448 dma 0 dma_ch1 dma channel interrupt enable 4000244c dma 0 dma_ch1 dma test register 40002450 dma 0 dma_ch2 dma activate register 40002454 dma 0 dma_ch2 dma memory start address register 40002458 dma 0 dma_ch2 dma memory end address register 4000245c dma 0 dma_ch2 ahb address register 40002460 dma 0 dma_ch2 dma control register 40002464 dma 0 dma_ch2 dma channel interrupt status 40002468 dma 0 dma_ch2 dma channel interrupt enable 4000246c dma 0 dma_ch2 dma test register 40002470 dma 0 dma_ch3 dma activate register 40002474 dma 0 dma_ch3 dma memory start address register 40002478 dma 0 dma_ch3 dma memory end address register 4000247c dma 0 dma_ch3 ahb address register 40002480 dma 0 dma_ch3 dma control register 40002484 dma 0 dma_ch3 dma channel interrupt status 40002488 dma 0 dma_ch3 dma channel interrupt enable 4000248c dma 0 dma_ch3 dma test register 40002490 dma 0 dma_ch4 dma activate register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 426 ? 2014 - 2015 microchip technology inc. 40002494 dma 0 dma_ch4 dma memory start address register 40002498 dma 0 dma_ch4 dma memory end address register 4000249c dma 0 dma_ch4 ahb address register 400024a0 dma 0 dma_ch4 dma control register 400024a4 dma 0 dma_ch4 dma channel interrupt status 400024a8 dma 0 dma_ch4 dma channel interrupt enable 400024ac dma 0 dma_ch4 dma test register 400024b0 dma 0 dma_ch5 dma activate register 400024b4 dma 0 dma_ch5 dma memory start address register 400024b8 dma 0 dma_ch5 dma memory end address register 400024bc dma 0 dma_ch5 ahb address register 400024c0 dma 0 dma_ch5 dma control register 400024c4 dma 0 dma_ch5 dma channel interrupt status 400024c8 dma 0 dma_ch5 dma channel interrupt enable 400024cc dma 0 dma_ch5 dma test register 400024d0 dma 0 dma_ch6 dma activate register 400024d4 dma 0 dma_ch6 dma memory start address register 400024d8 dma 0 dma_ch6 dma memory end address register 400024dc dma 0 dma_ch6 ahb address register 400024e0 dma 0 dma_ch6 dma control register 400024e4 dma 0 dma_ch6 dma channel interrupt status 400024e8 dma 0 dma_ch6 dma channel interrupt enable 400024ec dma 0 dma_ch6 dma test register 400024f0 dma 0 dma_ch7 dma activate register 400024f4 dma 0 dma_ch7 dma memory start address register 400024f8 dma 0 dma_ch7 dma memory end address register 400024fc dma 0 dma_ch7 ahb address register 40002500 dma 0 dma_ch7 dma control register 40002504 dma 0 dma_ch7 dma channel interrupt status 40002508 dma 0 dma_ch7 dma channel interrupt enable 4000250c dma 0 dma_ch7 dma test register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 427 MEC1322 40002510 dma 0 dma_ch8 dma activate register 40002514 dma 0 dma_ch8 dma memory start address register 40002518 dma 0 dma_ch8 dma memory end address register 4000251c dma 0 dma_ch8 ahb address register 40002520 dma 0 dma_ch8 dma control register 40002524 dma 0 dma_ch8 dma channel interrupt status 40002528 dma 0 dma_ch8 dma channel interrupt enable 4000252c dma 0 dma_ch8 dma test register 40002530 dma 0 dma_ch9 dma activate register 40002534 dma 0 dma_ch9 dma memory start address register 40002538 dma 0 dma_ch9 dma memory end address register 4000253c dma 0 dma_ch9 ahb address register 40002540 dma 0 dma_ch9 dma control register 40002544 dma 0 dma_ch9 dma channel interrupt status 40002548 dma 0 dma_ch9 dma channel interrupt enable 4000254c dma 0 dma_ch9 dma test register 40002550 dma 0 dma_ch10 dma activate register 40002554 dma 0 dma_ch10 dma memory start address register 40002558 dma 0 dma_ch10 dma memory end address register 4000255c dma 0 dma_ch10 ahb address register 40002560 dma 0 dma_ch10 dma control register 40002564 dma 0 dma_ch10 dma channel interrupt status 40002568 dma 0 dma_ch10 dma channel interrupt enable 4000256c dma 0 dma_ch10 dma test register 40002570 dma 0 dma_ch11 dma activate register 40002574 dma 0 dma_ch11 dma memory start address register 40002578 dma 0 dma_ch11 dma memory end address register 4000257c dma 0 dma_ch11 ahb address register 40002580 dma 0 dma_ch11 dma control register 40002584 dma 0 dma_ch11 dma channel interrupt status 40002588 dma 0 dma_ch11 dma channel interrupt enable address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 428 ? 2014 - 2015 microchip technology inc. 4000258c dma 0 dma_ch11 dma test register 40005800 pwm 0 pwm_ec_only pwm counter on time register 40005804 pwm 0 pwm_ec_only pwm counter off time register 40005808 pwm 0 pwm_ec_only pwm configuration regis- ter 4000580c pwm 0 pwm_ec_only reserved 40005810 pwm 1 pwm_ec_only pwm counter on time register 40005814 pwm 1 pwm_ec_only pwm counter off time register 40005818 pwm 1 pwm_ec_only pwm configuration regis- ter 4000581c pwm 1 pwm_ec_only reserved 40005820 pwm 2 pwm_ec_only pwm counter on time register 40005824 pwm 2 pwm_ec_only pwm counter off time register 40005828 pwm 2 pwm_ec_only pwm configuration regis- ter 4000582c pwm 2 pwm_ec_only reserved 40005830 pwm 3 pwm_ec_only pwm counter on time register 40005834 pwm 3 pwm_ec_only pwm counter off time register 40005838 pwm 3 pwm_ec_only pwm configuration regis- ter 4000583c pwm 3 pwm_ec_only reserved 40006000 tach 0 tach_ec_only tach control register 40006004 tach 0 tach_ec_only tach status register 40006008 tach 0 tach_ec_only tach high limit register 4000600c tach 0 tach_ec_only tach low limit register 40006010 tach 1 tach_ec_only tach control register 40006014 tach 1 tach_ec_only tach status register 40006018 tach 1 tach_ec_only tach high limit register 4000601c tach 1 tach_ec_only tach low limit register 40006400 peci 0 peci_ec_only peci write data register 40006404 peci 0 peci_ec_only peci read data register 40006408 peci 0 peci_ec_only peci control register 4000640c peci 0 peci_ec_only peci status 1 register 40006410 peci 0 peci_ec_only peci status 2 register 40006414 peci 0 peci_ec_only peci error register 40006418 peci 0 peci_ec_only peci interrupt enable 1 register 4000641c peci 0 peci_ec_only peci interrupt enable 2 register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 429 MEC1322 40006420 peci 0 peci_ec_only peci optimal bit time (low byte) register 40006424 peci 0 peci_ec_only peci optimal bit time (high byte) register 40006428 peci 0 peci_ec_only peci request timer (low byte) register 4000642c peci 0 peci_ec_only peci request timer (high byte) register 40006430 peci 0 peci_ec_only peci reserved 40006440 peci 0 peci_ec_only peci block id register 40006444 peci 0 peci_ec_only block revision 40007c00 adc 0 adc registers adc control register 40007c04 adc 0 adc registers adc delay register 40007c08 adc 0 adc registers adc status register 40007c0c adc 0 adc registers adc single register 40007c10 adc 0 adc registers adc repeat register 40007c14 adc 0 adc registers adc channel 0 reading registers 40007c18 adc 0 adc registers adc channel 1 reading registers 40007c1c adc 0 adc registers adc channel 2 reading registers 40007c20 adc 0 adc registers adc channel 3 reading registers 40007c24 adc 0 adc registers adc channel 4 reading registers 40007c54 adc 0 adc registers adc test register 40007c58 adc 0 adc registers adc test register 40007c78 adc 0 adc registers adc test register 40007c7c adc 0 adc registers adc configuration regis- ter 40008c00 trace fifo debug port 0 tfdp data 40008c04 trace fifo debug port 0 tfdp control 40009000 ps/2 0 registers ps/2 transmit buffer reg- ister 40009000 ps/2 0 registers ps/2 receive buffer regis- ter 40009004 ps/2 0 registers ps/2 control register 40009008 ps/2 0 registers ps/2 status register 40009040 ps/2 1 registers ps/2 transmit buffer reg- ister 40009040 ps/2 1 registers ps/2 receive buffer regis- ter 40009044 ps/2 1 registers ps/2 control register 40009048 ps/2 1 registers ps/2 status register 40009080 ps/2 2 registers ps/2 receive buffer regis- ter address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 430 ? 2014 - 2015 microchip technology inc. 40009080 ps/2 2 registers ps/2 transmit buffer reg- ister 40009084 ps/2 2 registers ps/2 control register 40009088 ps/2 2 registers ps/2 status register 400090c0 ps/2 3 registers ps/2 transmit buffer reg- ister 400090c0 ps/2 3 registers ps/2 receive buffer regis- ter 400090c4 ps/2 3 registers ps/2 control register 400090c8 ps/2 3 registers ps/2 status register 40009400 ec gp-spi 0 gp-spi_ec_only spi enable register 40009404 ec gp-spi 0 gp-spi_ec_only spi control register 40009408 ec gp-spi 0 gp-spi_ec_only spi status register 4000940c ec gp-spi 0 gp-spi_ec_only spi tx_data register 40009410 ec gp-spi 0 gp-spi_ec_only spi rx_data register 40009414 ec gp-spi 0 gp-spi_ec_only spi clock control register 40009418 ec gp-spi 0 gp-spi_ec_only spi clock generator reg- ister 40009480 ec gp-spi 1 gp-spi_ec_only spi enable register 40009484 ec gp-spi 1 gp-spi_ec_only spi control register 40009488 ec gp-spi 1 gp-spi_ec_only spi status register 4000948c ec gp-spi 1 gp-spi_ec_only spi tx_data register 40009490 ec gp-spi 1 gp-spi_ec_only spi rx_data register 40009494 ec gp-spi 1 gp-spi_ec_only spi clock control register 40009498 ec gp-spi 1 gp-spi_ec_only spi clock generator reg- ister 40009800 hibernation timer 0 registers htimer x preload register 40009804 hibernation timer 0 registers hibernation timer x control register 40009808 hibernation timer 0 registers hibernation timer x count register 40009c00 keyboard matrix scan support 0 registers reserved 40009c04 keyboard matrix scan support 0 registers kso select register 40009c08 keyboard matrix scan support 0 registers ksi input register 40009c0c keyboard matrix scan support 0 registers ksi status register 40009c10 keyboard matrix scan support 0 registers ksi interrupt enable regis- ter 40009c14 keyboard matrix scan support 0 registers keyscan extended control register 4000a000 rpm fan control 0 rpm_fan fan setting 4000a001 rpm fan control 0 rpm_fan pwm divide 4000a002 rpm fan control 0 rpm_fan fan configuration 1 address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 431 MEC1322 4000a003 rpm fan control 0 rpm_fan fan configuration 2 4000a004 rpm fan control 0 rpm_fan mchp reserved 4000a005 rpm fan control 0 rpm_fan gain 4000a006 rpm fan control 0 rpm_fan fan spin up configuration 4000a007 rpm fan control 0 rpm_fan fan step 4000a008 rpm fan control 0 rpm_fan fan minimum drive 4000a009 rpm fan control 0 rpm_fan valid tach count 4000a00a rpm fan control 0 rpm_fan fan drive fail band low byte 4000a00b rpm fan control 0 rpm_fan fan drive fail band high byte 4000a00c rpm fan control 0 rpm_fan tach target low byte 4000a00d rpm fan control 0 rpm_fan tach target high byte 4000a00e rpm fan control 0 rpm_fan tach reading low byte 4000a00f rpm fan control 0 rpm_fan tach reading high byte 4000a010 rpm fan control 0 rpm_fan pwm driver base fre- quency 4000a011 rpm fan control 0 rpm_fan fan status 4000a012 rpm fan control 0 rpm_fan reserved 4000a014 rpm fan control 0 rpm_fan rpm fan test 4000a015 rpm fan control 0 rpm_fan rpm fan test1 4000a016 rpm fan control 0 rpm_fan rpm fan test2 4000a017 rpm fan control 0 rpm_fan rpm fan test3 4000a400 vbat registers 0 vbat_ec_reg_bank power-fail and reset sta- tus register 4000a404 vbat registers 0 vbat_ec_reg_bank control 4000a800 vbat powered ram 0 registers vbat backed memory 4000ac00 smb device interface 1 smb_ec_only control register 4000ac00 smb device interface 1 smb_ec_only status register 4000ac01 smb device interface 1 smb_ec_only reserved 4000ac04 smb device interface 1 smb_ec_only own address register 4000ac06 smb device interface 1 smb_ec_only reserved 4000ac08 smb device interface 1 smb_ec_only data 4000ac09 smb device interface 1 smb_ec_only reserved 4000ac0c smb device interface 1 smb_ec_only smbus master command register 4000ac10 smb device interface 1 smb_ec_only smbus slave command register 4000ac14 smb device interface 1 smb_ec_only pec register 4000ac15 smb device interface 1 smb_ec_only reserved 4000ac18 smb device interface 1 smb_ec_only data_timing2 4000ac19 smb device interface 1 smb_ec_only reserved 4000ac20 smb device interface 1 smb_ec_only completion register 4000ac24 smb device interface 1 smb_ec_only idle scaling register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 432 ? 2014 - 2015 microchip technology inc. 4000ac28 smb device interface 1 smb_ec_only configuration register 4000ac2c smb device interface 1 smb_ec_only bus clock register 4000ac2e smb device interface 1 smb_ec_only reserved 4000ac30 smb device interface 1 smb_ec_only block id register 4000ac31 smb device interface 1 smb_ec_only reserved 4000ac34 smb device interface 1 smb_ec_only revision register 4000ac35 smb device interface 1 smb_ec_only reserved 4000ac38 smb device interface 1 smb_ec_only bit-bang control register 4000ac39 smb device interface 1 smb_ec_only reserved 4000ac3c smb device interf ace 1 smb_ec_only clock sync 4000ac40 smb device interface 1 smb_ec_only data timing register 4000ac44 smb device interface 1 smb_ec_only time-out scaling register 4000ac48 smb device interface 1 smb_ec_only smbus slave transmit buffer register 4000ac49 smb device interface 1 smb_ec_only reserved 4000ac4c smb device interface 1 smb_ec_only smbus slave receive buf- fer register 4000ac4d smb device interf ace 1 smb_ec_only reserved 4000ac50 smb device interface 1 smb_ec_only smbus master transmit bufer register 4000ac51 smb device interface 1 smb_ec_only reserved 4000ac54 smb device interface 1 smb_ec_only smbus master receive buffer register 4000ac55 smb device interface 1 smb_ec_only reserved 4000b000 smb device interface 2 smb_ec_only control register 4000b000 smb device interface 2 smb_ec_only status register 4000b001 smb device interface 2 smb_ec_only reserved 4000b004 smb device interface 2 smb_ec_only own address register 4000b006 smb device interface 2 smb_ec_only reserved 4000b008 smb device interface 2 smb_ec_only data 4000b009 smb device interface 2 smb_ec_only reserved 4000b00c smb device interface 2 smb_ec_only smbus master command register 4000b010 smb device interface 2 smb_ec_only smbus slave command register 4000b014 smb device interface 2 smb_ec_only pec register 4000b015 smb device interface 2 smb_ec_only reserved 4000b018 smb device interface 2 smb_ec_only data_timing2 4000b019 smb device interface 2 smb_ec_only reserved 4000b020 smb device interface 2 smb_ec_only completion register 4000b024 smb device interface 2 smb_ec_only idle scaling register 4000b028 smb device interface 2 smb_ec_only configuration register 4000b02c smb device interface 2 smb_ec_only bus clock register 4000b02e smb device interface 2 smb_ec_only reserved address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 433 MEC1322 4000b030 smb device interface 2 smb_ec_only block id register 4000b031 smb device interface 2 smb_ec_only reserved 4000b034 smb device interface 2 smb_ec_only revision register 4000b035 smb device interface 2 smb_ec_only reserved 4000b038 smb device interface 2 smb_ec_only bit-bang control register 4000b039 smb device interface 2 smb_ec_only reserved 4000b03c smb device interface 2 smb_ec_only clock sync 4000b040 smb device interface 2 smb_ec_only data timing register 4000b044 smb device interface 2 smb_ec_only time-out scaling register 4000b048 smb device interface 2 smb_ec_only smbus slave transmit buffer register 4000b049 smb device interface 2 smb_ec_only reserved 4000b04c smb device interface 2 smb_ec_only smbus slave receive buf- fer register 4000b04d smb device interface 2 smb_ec_only reserved 4000b050 smb device interface 2 smb_ec_only smbus master transmit bufer register 4000b051 smb device interface 2 smb_ec_only reserved 4000b054 smb device interface 2 smb_ec_only smbus master receive buffer register 4000b055 smb device interface 2 smb_ec_only reserved 4000b400 smb device interface 3 smb_ec_only control register 4000b400 smb device interface 3 smb_ec_only status register 4000b401 smb device interface 3 smb_ec_only reserved 4000b404 smb device interface 3 smb_ec_only own address register 4000b406 smb device interface 3 smb_ec_only reserved 4000b408 smb device interface 3 smb_ec_only data 4000b409 smb device interface 3 smb_ec_only reserved 4000b40c smb device interface 3 smb_ec_only smbus master command register 4000b410 smb device interface 3 smb_ec_only smbus slave command register 4000b414 smb device interface 3 smb_ec_only pec register 4000b415 smb device interface 3 smb_ec_only reserved 4000b418 smb device interfac e 3 smb_ec_only data_timing2 4000b419 smb device interface 3 smb_ec_only reserved 4000b420 smb device interface 3 smb_ec_only completion register 4000b424 smb device interface 3 smb_ec_only idle scaling register 4000b428 smb device interface 3 smb_ec_only configuration register 4000b42c smb device interface 3 smb_ec_only bus clock register 4000b42e smb device interface 3 smb_ec_only reserved 4000b430 smb device interface 3 smb_ec_only block id register 4000b431 smb device interface 3 smb_ec_only reserved 4000b434 smb device interface 3 smb_ec_only revision register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 434 ? 2014 - 2015 microchip technology inc. 4000b435 smb device interface 3 smb_ec_only reserved 4000b438 smb device interface 3 smb_ec_only bit-bang control register 4000b439 smb device interface 3 smb_ec_only reserved 4000b43c smb device interface 3 smb_ec_only clock sync 4000b440 smb device interface 3 smb_ec_only data timing register 4000b444 smb device interface 3 smb_ec_only time-out scaling register 4000b448 smb device interface 3 smb_ec_only smbus slave transmit buffer register 4000b449 smb device interface 3 smb_ec_only reserved 4000b44c smb device interface 3 smb_ec_only smbus slave receive buf- fer register 4000b44d smb device interface 3 smb_ec_only reserved 4000b450 smb device interface 3 smb_ec_only smbus master transmit bufer register 4000b451 smb device interface 3 smb_ec_only reserved 4000b454 smb device interface 3 smb_ec_only smbus master receive buffer register 4000b455 smb device interface 3 smb_ec_only reserved 4000b800 led 0 ec-only registers led configuration 4000b804 led 0 ec-only registers led limits 4000b808 led 0 ec-only registers led delay 4000b80c led 0 ec-only registers led update stepsize 4000b810 led 0 ec-only registers led update interval 4000b900 led 1 ec-only registers led configuration 4000b904 led 1 ec-only registers led limits 4000b908 led 1 ec-only registers led delay 4000b90c led 1 ec-only registers led update stepsize 4000b910 led 1 ec-only registers led update interval 4000ba00 led 2 ec-only registers led configuration 4000ba04 led 2 ec-only registers led limits 4000ba08 led 2 ec-only registers led delay 4000ba0c led 2 ec-only registers led update stepsize 4000ba10 led 2 ec-only registers led update interval 4000bb00 led 3 ec-only registers led configuration 4000bb04 led 3 ec-only registers led limits 4000bb08 led 3 ec-only registers led delay 4000bb0c led 3 ec-only registers led update stepsize 4000bb10 led 3 ec-only registers led update interval 4000bc00 bc-link master 0 registers bc-link status register 4000bc04 bc-link master 0 registers bc-link address register 4000bc08 bc-link master 0 registers bc-link data register 4000bc0c bc-link master 0 registers bc-link clock select reg- ister address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 435 MEC1322 4000c000 ec interrupt aggregator (ints) 0 ints_ec_only girq8 source register 4000c004 ec interrupt aggregator (ints) 0 ints_ec_only girq8 enable set regis- ter 4000c008 ec interrupt aggregator (ints) 0 ints_ec_only girq8 result register 4000c00c ec interrupt aggregator (ints) 0 ints_ec_only girq8 enable clear reg- ister 4000c014 ec interrupt aggregator (ints) 0 ints_ec_only girq9 source register 4000c018 ec interrupt aggregator (ints) 0 ints_ec_only girq9 enable set regis- ter 4000c01c ec interrupt aggregator (ints) 0 ints_ec_only girq9 result register 4000c020 ec interrupt aggregator (ints) 0 ints_ec_only girq9 enable clear reg- ister 4000c028 ec interrupt aggregator (ints) 0 ints_ec_only girq10 source register 4000c02c ec interrupt aggregator (ints) 0 ints_ec_only girq10 enable set regis- ter 4000c030 ec interrupt aggregator (ints) 0 ints_ec_only girq10 result register 4000c034 ec interrupt aggregator (ints) 0 ints_ec_only girq10 enable clear reg- ister 4000c03c ec interrupt aggregator (ints) 0 ints_ec_only girq11 source register 4000c040 ec interrupt aggregator (ints) 0 ints_ec_only girq11 enable set regis- ter 4000c044 ec interrupt aggregator (ints) 0 ints_ec_only girq11 result register 4000c048 ec interrupt aggregator (ints) 0 ints_ec_only girq11 enable clear reg- ister 4000c050 ec interrupt aggregator (ints) 0 ints_ec_only girq12 source register 4000c054 ec interrupt aggregator (ints) 0 ints_ec_only girq12 enable set regis- ter 4000c058 ec interrupt aggregator (ints) 0 ints_ec_only girq12 result register 4000c05c ec interrupt aggregator (ints) 0 ints_ec_only girq12 enable clear reg- ister 4000c064 ec interrupt aggregator (ints) 0 ints_ec_only girq13 source register 4000c068 ec interrupt aggregator (ints) 0 ints_ec_only girq13 enable set regis- ter 4000c06c ec interrupt aggregator (ints) 0 ints_ec_only girq13 result register 4000c070 ec interrupt aggregator (ints) 0 ints_ec_only girq13 enable clear reg- ister 4000c078 ec interrupt aggregator (ints) 0 ints_ec_only girq14 source register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 436 ? 2014 - 2015 microchip technology inc. 4000c07c ec interrupt aggregator (ints) 0 ints_ec_only girq14 enable set regis- ter 4000c080 ec interrupt aggregator (ints) 0 ints_ec_only girq14 result register 4000c084 ec interrupt aggregator (ints) 0 ints_ec_only girq14 enable clear reg- ister 4000c08c ec interrupt aggregator (ints) 0 ints_ec_only girq15 source register 4000c090 ec interrupt aggregator (ints) 0 ints_ec_only girq15 enable set regis- ter 4000c094 ec interrupt aggregator (ints) 0 ints_ec_only girq15 result register 4000c098 ec interrupt aggregator (ints) 0 ints_ec_only girq15 enable clear reg- ister 4000c0a0 ec interrupt aggregator (ints) 0 ints_ec_only girq16 source register 4000c0a4 ec interrupt aggregator (ints) 0 ints_ec_only girq16 enable set regis- ter 4000c0a8 ec interrupt aggregator (ints) 0 ints_ec_only girq16 result register 4000c0ac ec interrupt aggregator (ints) 0 ints_ec_only girq16 enable clear reg- ister 4000c0b4 ec interrupt aggregator (ints) 0 ints_ec_only girq17 source register 4000c0b8 ec interrupt aggregator (ints) 0 ints_ec_only girq17 enable set regis- ter 4000c0bc ec interrupt aggregator (ints) 0 ints_ec_only girq17 result register 4000c0c0 ec interrupt aggregator (ints) 0 ints_ec_only girq17 enable clear reg- ister 4000c0c8 ec interrupt aggregator (ints) 0 ints_ec_only girq18 source register 4000c0cc ec interrupt aggregator (ints) 0 ints_ec_only girq18 enable set regis- ter 4000c0d0 ec interrupt aggregator (ints) 0 ints_ec_only girq18 result register 4000c0d4 ec interrupt aggregator (ints) 0 ints_ec_only girq18 enable clear reg- ister 4000c0dc ec interrupt aggregator (ints) 0 ints_ec_only girq19 source register 4000c0e0 ec interrupt aggregator (ints) 0 ints_ec_only girq19 enable set regis- ter 4000c0e4 ec interrupt aggregator (ints) 0 ints_ec_only girq19 result register 4000c0e8 ec interrupt aggregator (ints) 0 ints_ec_only girq19 enable clear reg- ister 4000c0f0 ec interrupt aggregator (ints) 0 ints_ec_only girq20 source register 4000c0f4 ec interrupt aggregator (ints) 0 ints_ec_only girq20 enable set regis- ter address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 437 MEC1322 4000c0f8 ec interrupt aggregator (ints) 0 ints_ec_only girq20 result register 4000c0fc ec interrupt aggregator (ints) 0 ints_ec_only girq20 enable clear reg- ister 4000c104 ec interrupt aggregator (ints) 0 ints_ec_only girq21 source register 4000c108 ec interrupt aggregator (ints) 0 ints_ec_only girq21 enable set regis- ter 4000c10c ec interrupt aggregator (ints) 0 ints_ec_only girq21 result register 4000c110 ec interrupt aggregator (ints) 0 ints_ec_only girq21 enable clear reg- ister 4000c118 ec interrupt aggregator (ints) 0 ints_ec_only girq22 source register 4000c11c ec interrupt aggregator (ints) 0 ints_ec_only girq22 enable set regis- ter 4000c120 ec interrupt aggregator (ints) 0 ints_ec_only girq22 result register 4000c124 ec interrupt aggregator (ints) 0 ints_ec_only girq22 enable clear reg- ister 4000c12c ec interrupt aggregator (ints) 0 ints_ec_only girq23 source register 4000c130 ec interrupt aggregator (ints) 0 ints_ec_only girq23 enable set regis- ter 4000c134 ec interrupt aggregator (ints) 0 ints_ec_only girq23 result register 4000c138 ec interrupt aggregator (ints) 0 ints_ec_only girq23 enable clear reg- ister 4000c200 ec interrupt aggregator (ints) 0 ints_ec_only block enable set register 4000c204 ec interrupt aggregator (ints) 0 ints_ec_only block enable clear regis- ter 4000c208 ec interrupt aggregator (ints) 0 ints_ec_only block irq vector register 4000fc00 ec_reg_bank 0 ec_reg_bank reserved 4000fc04 ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc08 ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc0c ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc10 ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc11 ec_reg_bank 0 ec_reg_bank reserved 4000fc14 ec_reg_bank 0 ec_reg_bank ahb error control 4000fc15 ec_reg_bank 0 ec_reg_bank reserved 4000fc18 ec_reg_bank 0 ec_reg_bank interrupt control 4000fc1c ec_reg_bank 0 ec_reg_bank etm trace enable 4000fc20 ec_reg_bank 0 ec_reg_bank jtag enable 4000fc24 ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc28 ec_reg_bank 0 ec_reg_bank wdt event count 4000fc2c ec_reg_bank 0 ec_reg_bank mchp reserved address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 438 ? 2014 - 2015 microchip technology inc. 4000fc30 ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc34 ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc38 ec_reg_bank 0 ec_reg_bank adc vref pd 4000fc3c ec_reg_bank 0 ec_reg_bank mchp reserved 4000fc40 ec_reg_bank 0 ec_reg_bank mchp reserved 40080000 jtag 0 jtag_ec_only jtag message obf 40080004 jtag 0 jtag_ec_only jtag message ibf 40080008 jtag 0 jtag_ec_only jtag obf status 40080009 jtag 0 jtag_ec_only jtag ibf status 4008000c jtag 0 jtag_ec_only jtag dbg ctrl 40080100 pcr 0 pcr chip sleep enable regis- ter 40080104 pcr 0 pcr chip clock required reg- ister 40080108 pcr 0 pcr ec sleep enables register 4008010c pcr 0 pcr ec clock required status register 40080110 pcr 0 pcr host sleep enables regis- ter 40080114 pcr 0 pcr host clock required status register 40080118 pcr 0 pcr chi p_pcr_addr_sys- _sleep_ctrl_0 40080120 pcr 0 pcr processor clock control 40080124 pcr 0 pcr ec sleep enable 2 regis- ter 40080128 pcr 0 pcr ec clock required 2 sta- tus register 4008012c pcr 0 pcr slow clock control 40080130 pcr 0 pcr oscillator id register 40080134 pcr 0 pcr reserved 40080138 pcr 0 pcr chip reset enable 4008013c pcr 0 pcr host reset enable 40080140 pcr 0 pcr ec reset enable 40080144 pcr 0 pcr ec reset enable 2 40080148 pcr 0 pcr pcr clock reset control 40081000 gpio 0 gpio registers gpio000 pin control 40081004 gpio 0 gpio registers gpio001 pin control 40081008 gpio 0 gpio registers gpio002 pin control 4008100c gpio 0 gpio registers gpio003 pin control 40081010 gpio 0 gpio registers gpio004 pin control 40081014 gpio 0 gpio registers gpio005 pin control 40081018 gpio 0 gpio registers gpio006 pin control 4008101c gpio 0 gpio registers gpio007 pin control 40081020 gpio 0 gpio registers gpio010 pin control address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 439 MEC1322 40081024 gpio 0 gpio registers gpio011 pin control 40081028 gpio 0 gpio registers gpio012 pin control 4008102c gpio 0 gpio registers gpio013 pin control 40081030 gpio 0 gpio registers gpio014 pin control 40081034 gpio 0 gpio registers gpio015 pin control 40081038 gpio 0 gpio registers gpio016 pin control 4008103c gpio 0 gpio registers gpio017 pin control 40081040 gpio 0 gpio registers gpio020 pin control 40081044 gpio 0 gpio registers gpio021 pin control 40081048 gpio 0 gpio registers gpio022 pin control 4008104c gpio 0 gpio registers gpio023 pin control 40081050 gpio 0 gpio registers gpio024 pin control 40081054 gpio 0 gpio registers gpio025 pin control 40081058 gpio 0 gpio registers gpio026 pin control 4008105c gpio 0 gpio registers gpio027 pin control 40081060 gpio 0 gpio registers gpio030 pin control 40081064 gpio 0 gpio registers gpio031 pin control 40081068 gpio 0 gpio registers gpio032 pin control 4008106c gpio 0 gpio registers gpio033 pin control 40081070 gpio 0 gpio registers gpio034 pin control 40081074 gpio 0 gpio registers gpio035 pin control 40081078 gpio 0 gpio registers gpio036 pin control 40081080 gpio 0 gpio registers gpio040 pin control 40081084 gpio 0 gpio registers gpio041 pin control 40081088 gpio 0 gpio registers gpio042 pin control 4008108c gpio 0 gpio registers gpio043 pin control 40081090 gpio 0 gpio registers gpio044 pin control 40081094 gpio 0 gpio registers gpio045 pin control 40081098 gpio 0 gpio registers gpio046 pin control 4008109c gpio 0 gpio registers gpio047 pin control 400810a0 gpio 0 gpio registers gpio050 pin control 400810a4 gpio 0 gpio registers gpio051 pin control 400810a8 gpio 0 gpio registers gpio052 pin control 400810ac gpio 0 gpio registers gpio053 pin control 400810b0 gpio 0 gpio registers gpio054 pin control 400810b4 gpio 0 gpio registers gpio055 pin control 400810b8 gpio 0 gpio registers gpio056 pin control 400810bc gpio 0 gpio registers gpio057 pin control 400810c0 gpio 0 gpio registers gpio060 pin control 400810c4 gpio 0 gpio registers gpio061 pin control 400810c8 gpio 0 gpio registers gpio062 pin control 400810cc gpio 0 gpio registers gpio063 pin control 400810d0 gpio 0 gpio registers gpio064 pin control address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 440 ? 2014 - 2015 microchip technology inc. 400810d4 gpio 0 gpio registers gpio065 pin control 400810d8 gpio 0 gpio registers gpio066 pin control 400810dc gpio 0 gpio registers gpio067 pin control 40081100 gpio 0 gpio registers gpio100 pin control 40081104 gpio 0 gpio registers gpio101 pin control 40081108 gpio 0 gpio registers gpio102 pin control 4008110c gpio 0 gpio registers gpio103 pin control 40081110 gpio 0 gpio registers gpio104 pin control 40081114 gpio 0 gpio registers gpio105 pin control 40081118 gpio 0 gpio registers gpio106 pin control 4008111c gpio 0 gpio registers gpio107 pin control 40081120 gpio 0 gpio registers gpio110 pin control 40081124 gpio 0 gpio registers gpio111 pin control 40081128 gpio 0 gpio registers gpio112 pin control 4008112c gpio 0 gpio registers gpio113 pin control 40081130 gpio 0 gpio registers gpio114 pin control 40081134 gpio 0 gpio registers gpio115 pin control 40081138 gpio 0 gpio registers gpio116 pin control 4008113c gpio 0 gpio registers gpio117 pin control 40081140 gpio 0 gpio registers gpio120 pin control 40081144 gpio 0 gpio registers gpio121 pin control 40081148 gpio 0 gpio registers gpio122 pin control 4008114c gpio 0 gpio registers gpio123 pin control 40081150 gpio 0 gpio registers gpio124 pin control 40081154 gpio 0 gpio registers gpio125 pin control 40081158 gpio 0 gpio registers gpio126 pin control 4008115c gpio 0 gpio registers gpio127 pin control 40081160 gpio 0 gpio registers gpio130 pin control 40081164 gpio 0 gpio registers gpio131 pin control 40081168 gpio 0 gpio registers gpio132 pin control 4008116c gpio 0 gpio registers gpio133 pin control 40081170 gpio 0 gpio registers gpio134 pin control 40081174 gpio 0 gpio registers gpio135 pin control 40081178 gpio 0 gpio registers gpio136 pin control 40081180 gpio 0 gpio registers gpio140 pin control 40081184 gpio 0 gpio registers gpio141 pin control 40081188 gpio 0 gpio registers gpio142 pin control 4008118c gpio 0 gpio registers gpio143 pin control 40081190 gpio 0 gpio registers gpio144 pin control 40081194 gpio 0 gpio registers gpio145 pin control 40081198 gpio 0 gpio registers gpio146 pin control 4008119c gpio 0 gpio registers gpio147 pin control 400811a0 gpio 0 gpio registers gpio150 pin control address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 441 MEC1322 400811a4 gpio 0 gpio registers gpio151 pin control 400811a8 gpio 0 gpio registers gpio152 pin control 400811ac gpio 0 gpio registers gpio153 pin control 400811b0 gpio 0 gpio registers gpio154 pin control 400811b4 gpio 0 gpio registers gpio155 pin control 400811b8 gpio 0 gpio registers gpio156 pin control 400811bc gpio 0 gpio registers gpio157 pin control 400811c0 gpio 0 gpio registers gpio160 pin control 400811c4 gpio 0 gpio registers gpio161 pin control 400811c8 gpio 0 gpio registers gpio162 pin control 400811cc gpio 0 gpio registers gpio163 pin control 400811d0 gpio 0 gpio registers gpio164 pin control 400811d4 gpio 0 gpio registers gpio165 pin control 40081200 gpio 0 gpio registers gpio200 pin control 40081204 gpio 0 gpio registers gpio201 pin control 40081208 gpio 0 gpio registers gpio202 pin control 4008120c gpio 0 gpio registers gpio203 pin control 40081210 gpio 0 gpio registers gpio204 pin control 40081214 gpio 0 gpio registers reserved 40081218 gpio 0 gpio registers gpio206 pin control 4008121c gpio 0 gpio registers reserved 40081220 gpio 0 gpio registers gpio210 pin control 40081224 gpio 0 gpio registers gpio211 pin control 40081280 gpio 0 gpio registers output gpio[000:036] 40081284 gpio 0 gpio registers output gpio[040:076] 40081288 gpio 0 gpio registers output gpio[100:136] 4008128c gpio 0 gpio registers output gpio[140:176] 40081290 gpio 0 gpio registers output gpio[200:236] 40081300 gpio 0 gpio registers input gpio[000:036] 40081304 gpio 0 gpio registers input gpio[040:076] 40081308 gpio 0 gpio registers input gpio[100:136] 4008130c gpio 0 gpio registers input gpio[140:176] 40081310 gpio 0 gpio registers input gpio[200:236] 40081314 gpio 0 gpio registers reserved 40081500 gpio 0 gpio registers gpio000 pin control 2 40081504 gpio 0 gpio registers gpio001 pin control 2 40081508 gpio 0 gpio registers gpio002 pin control 2 4008150c gpio 0 gpio registers gpio003 pin control 2 40081510 gpio 0 gpio registers gpio004 pin control 2 40081514 gpio 0 gpio registers gpio005 pin control 2 40081518 gpio 0 gpio registers gpio006 pin control 2 4008151c gpio 0 gpio registers gpio007 pin control 2 40081520 gpio 0 gpio registers gpio010 pin control 2 address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 442 ? 2014 - 2015 microchip technology inc. 40081524 gpio 0 gpio registers gpio011 pin control 2 40081528 gpio 0 gpio registers gpio012 pin control 2 4008152c gpio 0 gpio registers gpio013 pin control 2 40081530 gpio 0 gpio registers gpio014 pin control 2 40081534 gpio 0 gpio registers gpio015 pin control 2 40081538 gpio 0 gpio registers gpio016 pin control 2 4008153c gpio 0 gpio registers gpio017 pin control 2 40081540 gpio 0 gpio registers gpio020 pin control 2 40081544 gpio 0 gpio registers gpio021 pin control 2 40081548 gpio 0 gpio registers gpio022 pin control 2 4008154c gpio 0 gpio registers gpio023 pin control 2 40081550 gpio 0 gpio registers gpio024 pin control 2 40081554 gpio 0 gpio registers gpio025 pin control 2 40081558 gpio 0 gpio registers gpio026 pin control 2 4008155c gpio 0 gpio registers gpio027 pin control 2 40081560 gpio 0 gpio registers gpio030 pin control 2 40081564 gpio 0 gpio registers gpio031 pin control 2 40081568 gpio 0 gpio registers gpio032 pin control 2 4008156c gpio 0 gpio registers gpio033 pin control 2 40081570 gpio 0 gpio registers gpio034 pin control 2 40081574 gpio 0 gpio registers gpio035 pin control 2 40081578 gpio 0 gpio registers gpio036 pin control 2 40081580 gpio 0 gpio registers gpio040 pin control 2 40081584 gpio 0 gpio registers gpio041 pin control 2 40081588 gpio 0 gpio registers gpio042 pin control 2 4008158c gpio 0 gpio registers gpio043 pin control 2 40081590 gpio 0 gpio registers gpio044 pin control 2 40081594 gpio 0 gpio registers gpio045 pin control 2 40081598 gpio 0 gpio registers gpio046 pin control 2 4008159c gpio 0 gpio registers gpio047 pin control 2 400815a0 gpio 0 gpio registers gpio050 pin control 2 400815a4 gpio 0 gpio registers gpio051 pin control 2 400815a8 gpio 0 gpio registers gpio052 pin control 2 400815ac gpio 0 gpio registers gpio053 pin control 2 400815b0 gpio 0 gpio registers gpio054 pin control 2 400815b4 gpio 0 gpio registers gpio055 pin control 2 400815b8 gpio 0 gpio registers gpio056 pin control 2 400815bc gpio 0 gpio registers gpio057 pin control 2 400815c0 gpio 0 gpio registers gpio060 pin control 2 400815c4 gpio 0 gpio registers gpio061 pin control 2 400815c8 gpio 0 gpio registers gpio062 pin control 2 400815cc gpio 0 gpio registers gpio063 pin control 2 400815d0 gpio 0 gpio registers gpio064 pin control 2 address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 443 MEC1322 400815d4 gpio 0 gpio registers gpio065 pin control 2 400815d8 gpio 0 gpio registers gpio066 pin control 2 400815dc gpio 0 gpio registers gpio067 pin control 2 400815e0 gpio 0 gpio registers gpio100 pin control 2 400815e4 gpio 0 gpio registers gpio101 pin control 2 400815e8 gpio 0 gpio registers gpio102 pin control 2 400815ec gpio 0 gpio registers gpio103 pin control 2 400815f0 gpio 0 gpio registers gpio104 pin control 2 400815f4 gpio 0 gpio registers gpio105 pin control 2 400815f8 gpio 0 gpio registers gpio106 pin control 2 400815fc gpio 0 gpio registers gpio107 pin control 2 40081600 gpio 0 gpio registers gpio110 pin control 2 40081604 gpio 0 gpio registers gpio111 pin control 2 40081608 gpio 0 gpio registers gpio112 pin control 2 4008160c gpio 0 gpio registers gpio113 pin control 2 40081610 gpio 0 gpio registers gpio114 pin control 2 40081614 gpio 0 gpio registers gpio115 pin control 2 40081618 gpio 0 gpio registers gpio116 pin control 2 4008161c gpio 0 gpio registers gpio117 pin control 2 40081620 gpio 0 gpio registers gpio120 pin control 2 40081624 gpio 0 gpio registers gpio121 pin control 2 40081628 gpio 0 gpio registers gpio122 pin control 2 4008162c gpio 0 gpio registers gpio123 pin control 2 40081630 gpio 0 gpio registers gpio124 pin control 2 40081634 gpio 0 gpio registers gpio125 pin control 2 40081638 gpio 0 gpio registers gpio126 pin control 2 4008163c gpio 0 gpio registers gpio127 pin control 2 40081640 gpio 0 gpio registers gpio130 pin control 2 40081644 gpio 0 gpio registers gpio131 pin control 2 40081648 gpio 0 gpio registers gpio132 pin control 2 4008164c gpio 0 gpio registers gpio133 pin control 2 40081650 gpio 0 gpio registers gpio134 pin control 2 40081654 gpio 0 gpio registers gpio135 pin control 2 40081658 gpio 0 gpio registers gpio136 pin control 2 40081660 gpio 0 gpio registers gpio140 pin control 2 40081664 gpio 0 gpio registers gpio141 pin control 2 40081668 gpio 0 gpio registers gpio142 pin control 2 4008166c gpio 0 gpio registers gpio143 pin control 2 40081670 gpio 0 gpio registers gpio144 pin control 2 40081674 gpio 0 gpio registers gpio145 pin control 2 40081678 gpio 0 gpio registers gpio146 pin control 2 4008167c gpio 0 gpio registers gpio147 pin control 2 40081680 gpio 0 gpio registers gpio150 pin control 2 address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 444 ? 2014 - 2015 microchip technology inc. 40081684 gpio 0 gpio registers gpio151 pin control 2 40081688 gpio 0 gpio registers gpio152 pin control 2 4008168c gpio 0 gpio registers gpio153 pin control 2 40081690 gpio 0 gpio registers gpio154 pin control 2 40081694 gpio 0 gpio registers gpio155 pin control 2 40081698 gpio 0 gpio registers gpio156 pin control 2 4008169c gpio 0 gpio registers gpio157 pin control 2 400816a0 gpio 0 gpio registers gpio160 pin control 2 400816a4 gpio 0 gpio registers gpio161 pin control 2 400816a8 gpio 0 gpio registers gpio162 pin control 2 400816ac gpio 0 gpio registers gpio163 pin control 2 400816b0 gpio 0 gpio registers gpio164 pin control 2 400816b4 gpio 0 gpio registers gpio165 pin control 2 40081720 gpio 0 gpio registers gpio200 pin control 2 40081724 gpio 0 gpio registers gpio201 pin control 2 40081728 gpio 0 gpio registers gpio202 pin control 2 4008172c gpio 0 gpio registers gpio203 pin control 2 40081730 gpio 0 gpio registers gpio204 pin control 2 40081738 gpio 0 gpio registers gpio206 pin control 2 40081740 gpio 0 gpio registers gpio210 pin control 2 40081744 gpio 0 gpio registers gpio211 pin control 2 400f0000 imap 0 emi_runtime emi host-to-ec mailbox register 400f0001 imap 0 emi_runtime ec-to-host mailbox regis- ter 400f0002 imap 0 emi_runtime ec address register 400f0004 imap 0 emi_runtime ec data register 400f0008 imap 0 emi_runtime interrupt source register 400f000a imap 0 emi_runtime interrupt mask register 400f000c imap 0 emi_runtime application id register 400f0100 imap 0 emi_ec_only emi host-to-ec mailbox register 400f0101 imap 0 emi_ec_only ec-to-host mailbox regis- ter 400f0104 imap 0 emi_ec_only memory base address 0 register 400f0108 imap 0 emi_ec_only memory read limit 0 reg- ister 400f010a imap 0 emi_ec_only memory write limit 0 reg- ister 400f010c imap 0 emi_ec_only memory base address 1 register 400f0110 imap 0 emi_ec_only memory read limit 1 reg- ister 400f0112 imap 0 emi_ec_only memory write limit 1 reg- ister address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 445 MEC1322 400f0114 imap 0 emi_ec_only interrupt set register 400f0116 imap 0 emi_ec_only host clear enable register 400f0400 8042 host interface 0 kbc_runtime ec_host data/aux regis- ter (read) 400f0400 8042 host interface 0 kbc_runtime host_ec data register (write) 400f0404 8042 host interface 0 kbc_runtime host_ec command regis- ter (write) 400f0404 8042 host interface 0 kbc_runtime keyboard status read register 400f0500 8042 host interface 0 kbc_ec_only host_ec data/cmd regis- ter 400f0500 8042 host interface 0 kbc_ec_only ec_host data register 400f0504 8042 host interface 0 kbc_ec_only keyboard status read register 400f0508 8042 host interface 0 kbc_ec_only keyboard control register 400f050c 8042 host interface 0 kbc_ec_only ec_host aux register 400f0514 8042 host interface 0 kbc_ec_only pcobf register 400f0730 8042 host interface 0 kbc_configuration activate register 400f0c00 acpi ec interface 0 acpi_runtime acpi os data register byte 0 400f0c00 acpi ec interface 0 acpi_runtime acpi os data register byte 0 400f0c01 acpi ec interface 0 acpi_runtime acpi os data register byte 1 400f0c01 acpi ec interface 0 acpi_runtime acpi os data register byte 1 400f0c02 acpi ec interface 0 acpi_runtime acpi os data register byte 2 400f0c02 acpi ec interface 0 acpi_runtime acpi os data register byte 2 400f0c03 acpi ec interface 0 acpi_runtime acpi os data register byte 3 400f0c03 acpi ec interface 0 acpi_runtime acpi os data register byte 3 400f0c04 acpi ec interface 0 acpi_runtime acpi os command regis- ter 400f0c04 acpi ec interface 0 acpi_runtime status os-register 400f0c05 acpi ec interface 0 acpi_runtime byte control os-register 400f0d00 acpi ec interface 0 acpi _ec_only ec2os data ec-register byte 0 400f0d01 acpi ec interface 0 acpi _ec_only ec2os data ec-register byte 1 400f0d02 acpi ec interface 0 acpi _ec_only ec2os data ec-register byte 2 400f0d03 acpi ec interface 0 acpi _ec_only ec2os data ec-register byte 3 400f0d04 acpi ec interface 0 ac pi_ec_only status ec-register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 446 ? 2014 - 2015 microchip technology inc. 400f0d05 acpi ec inte rface 0 acpi_ec_only byte control ec-register 400f0d08 acpi ec interface 0 acpi_ec_only os2ec data ec-register byte 0 400f0d08 acpi ec interface 0 acpi_ec_only os2ec data ec-register byte 0 400f0d09 acpi ec interface 0 acpi_ec_only os2ec data ec-register byte 1 400f0d0a acpi ec interface 0 acpi_ec_only os2ec data ec-register byte 2 400f0d0b acpi ec interface 0 acpi_ec_only os2ec data ec-register byte 3 400f1000 acpi ec interface 1 acpi_runtime acpi os data register byte 0 400f1000 acpi ec interface 1 acpi_runtime acpi os data register byte 0 400f1001 acpi ec interface 1 acpi_runtime acpi os data register byte 1 400f1001 acpi ec interface 1 acpi_runtime acpi os data register byte 1 400f1002 acpi ec interface 1 acpi_runtime acpi os data register byte 2 400f1002 acpi ec interface 1 acpi_runtime acpi os data register byte 2 400f1003 acpi ec interface 1 acpi_runtime acpi os data register byte 3 400f1003 acpi ec interface 1 acpi_runtime acpi os data register byte 3 400f1004 acpi ec interface 1 acpi_runtime acpi os command regis- ter 400f1004 acpi ec interface 1 acpi_runtime status os-register 400f1005 acpi ec interface 1 acpi_runtime byte control os-register 400f1100 acpi ec interface 1 acpi _ec_only ec2os data ec-register byte 0 400f1101 acpi ec interface 1 acpi _ec_only ec2os data ec-register byte 1 400f1102 acpi ec interface 1 acpi _ec_only ec2os data ec-register byte 2 400f1103 acpi ec interface 1 acpi _ec_only ec2os data ec-register byte 3 400f1104 acpi ec interface 1 ac pi_ec_only status ec-register 400f1105 acpi ec interface 1 acpi _ec_only byte control ec-register 400f1108 acpi ec interface 1 acpi_ec_only os2ec data ec-register byte 0 400f1108 acpi ec interface 1 acpi_ec_only os2ec data ec-register byte 0 400f1109 acpi ec interface 1 acpi_ec_only os2ec data ec-register byte 1 400f110a acpi ec interface 1 acpi_ec_only os2ec data ec-register byte 2 address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 447 MEC1322 400f110b acpi ec interface 1 acpi_ec_only os2ec data ec-register byte 3 400f1400 acpi pm1 0 pm1_runtime pm1 status 1 400f1401 acpi pm1 0 pm1_runtime pm1 status 2 400f1402 acpi pm1 0 pm1_runtime pm1 enable 1 400f1403 acpi pm1 0 pm1_runtime pm1 enable 2 400f1404 acpi pm1 0 pm1_runtime pm1 control 1 400f1405 acpi pm1 0 pm1_runtime pm1 control 2 400f1406 acpi pm1 0 pm1_runtime pm2 control 1 400f1407 acpi pm1 0 pm1_runtime pm2 control 2 400f1500 acpi pm1 0 pm1_ec_only pm1 status 1 400f1501 acpi pm1 0 pm1_ec_only pm1 status 2 400f1502 acpi pm1 0 pm1_ec_only pm1 enable 1 400f1503 acpi pm1 0 pm1_ec_only pm1 enable 2 400f1504 acpi pm1 0 pm1_ec_only pm1 control 1 400f1505 acpi pm1 0 pm1_ec_only pm1 control 2 400f1506 acpi pm1 0 pm1_ec_only pm2 control 1 400f1507 acpi pm1 0 pm1_ec_only pm2 control 2 400f1510 acpi pm1 0 pm1_ec_only pm1 ec pm status 400f1800 8042 host interface 0 legacy_runtime port92 register 400f1900 8042 host interface 0 legacy_ec_only gatea20 control register 400f1908 8042 host interface 0 legacy_ec_only setga20l register 400f190c 8042 host interface 0 legacy_ec_only rstga20l register 400f1b30 8042 host interface 0 legacy_configuration port92 enable register 400f1c00 m16c550a uart 0 uart_ec_only uart programmable baud rate generator (lsb) register 400f1c00 m16c550a uart 0 uart_ec_only uart receive buffer reg- ister 400f1c00 m16c550a uart 0 uart_ec_only uart transmit buffer reg- ister 400f1c01 m16c550a uart 0 uart_ec_only uart programmable baud rate generator (msb) register 400f1c01 m16c550a uart 0 uart_ec_only uart interrupt enable register 400f1c02 m16c550a uart 0 uart_ec_only uart fifo control regis- ter 400f1c02 m16c550a uart 0 uart_ec_only uart interrupt identifica- tion register 400f1c03 m16c550a uart 0 uart_ec_only uart line control regis- ter 400f1c04 m16c550a uart 0 uart_ec_only uart modem control register 400f1c05 m16c550a uart 0 uart_ec_only uart line status register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 448 ? 2014 - 2015 microchip technology inc. 400f1c06 m16c550a uart 0 uart_ec_only uart modem status reg- ister 400f1c07 m16c550a uart 0 uart_ec_only uart scratchpad register 400f1c00 m16c550a uart 0 uart_runtime uart transmit buffer reg- ister 400f1c00 m16c550a uart 0 uart_runtime uart programmable baud rate generator (lsb) register 400f1c00 m16c550a uart 0 uart_runtime uart receive buffer reg- ister 400f1c01 m16c550a uart 0 uart_runtime uart interrupt enable register 400f1c01 m16c550a uart 0 uart_runtime uart programmable baud rate generator (msb) register 400f1c02 m16c550a uart 0 uart_runtime uart fifo control regis- ter 400f1c02 m16c550a uart 0 uart_runtime uart interrupt identifica- tion register 400f1c03 m16c550a uart 0 uart_runtime uart line control regis- ter 400f1c04 m16c550a uart 0 uart_runtime uart modem control register 400f1c05 m16c550a uart 0 uart_runtime uart line status register 400f1c06 m16c550a uart 0 uart_runtime uart modem status reg- ister 400f1c07 m16c550a uart 0 uart_runtime uart scratchpad register 400f1f30 m16c550a uart 0 uart_config uart activate register 400f1ff0 m16c550a uart 0 uart_config uart config select regis- ter 400f2400 mailbox registers inter- face 0 mbx_runtime mbx_index register 400f2401 mailbox registers inter- face 0 mbx_runtime mbx_data_register 400f2500 mailbox registers inter- face 0 mbx_ec_only host-to-ec mailbox reg- ister 400f2504 mailbox registers inter- face 0 mbx_ec_only ec-to-host mailbox regis- ter 400f2508 mailbox registers inter- face 0 mbx_ec_only smi interrupt source reg- ister 400f250c mailbox registers inter- face 0 mbx_ec_only smi interrupt mask regis- ter 400f2510 mailbox registers inter- face 0 mbx_ec_only mailbox register [3:0] 400f2514 mailbox registers inter- face 0 mbx_ec_only mailbox register [7:4] 400f2518 mailbox registers inter- face 0 mbx_ec_only mailbox register [bh:8] address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 449 MEC1322 400f251c mailbox registers inter- face 0 mbx_ec_only mailbox register [fh:ch] 400f2520 mailbox registers inter- face 0 mbx_ec_only mailbox register [13h:10h] 400f2524 mailbox registers inter- face 0 mbx_ec_only mailbox register [17h:14h] 400f2528 mailbox registers inter- face 0 mbx_ec_only mailbox register [1bh:18h] 400f252c mailbox registers inter- face 0 mbx_ec_only mailbox register [1fh:1ch] 400f2530 mailbox registers inter- face 0 mbx_ec_only mailbox register [23h:20h] 400f2534 mailbox registers inter- face 0 mbx_ec_only mailbox register [27h:24h] 400f2538 mailbox registers inter- face 0 mbx_ec_only mailbox register [2ah:28h] 400f2c00 rtc 0 rtc seconds 400f2c01 rtc 0 rtc seconds alarm 400f2c02 rtc 0 rtc minutes 400f2c03 rtc 0 rtc minutes alarm 400f2c04 rtc 0 rtc hours 400f2c05 rtc 0 rtc hours alarm 400f2c06 rtc 0 rtc day of week 400f2c07 rtc 0 rtc day of month 400f2c08 rtc 0 rtc month 400f2c09 rtc 0 rtc year 400f2c0a rtc 0 rtc register a 400f2c0b rtc 0 rtc register b 400f2c0c rtc 0 rtc register c 400f2c0d rtc 0 rtc register d 400f2c10 rtc 0 rtc rtc control 400f2c14 rtc 0 rtc week alarm 400f2c18 rtc 0 rtc daylight savings forward 400f2c1c rtc 0 rtc daylight savings backward 400f2c20 rtc 0 rtc rtc test mode 400f3000 lpc 0 lpc_runtime configuration port index register 400f3001 lpc 0 lpc_runtime configuration port data register 400f3100 lpc 0 lpc_ec_only reserved 400f3104 lpc 0 lpc_ec_only lpc bus monitor register 400f3108 lpc 0 lpc_ec_only host bus error register 400f310c lpc 0 lpc_ec_only ec serirq register 400f3110 lpc 0 lpc_ec_only ec clock control register 400f3114 lpc 0 lpc_ec_only reserved 400f3118 lpc 0 lpc_ec_only reserved address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 450 ? 2014 - 2015 microchip technology inc. 400f3120 lpc 0 lpc_ec_only bar inhibit register 400f3130 lpc 0 lpc_ec_only lpc bar init register 400f3140 lpc 0 lpc_ec_only memory bar inhibit 400f31fc lpc 0 lpc_ec_only memory host configuration register 400f3330 lpc 0 lpc_config lpc activate 400f3340 lpc 0 lpc_config sirq0 interrupt configura- tion register 400f3341 lpc 0 lpc_config sirq1 interrupt configura- tion register 400f3342 lpc 0 lpc_config sirq2 interrupt configura- tion register 400f3343 lpc 0 lpc_config sirq3 interrupt configura- tion register 400f3344 lpc 0 lpc_config sirq4 interrupt configura- tion register 400f3345 lpc 0 lpc_config sirq5 interrupt configura- tion register 400f3346 lpc 0 lpc_config sirq6 interrupt configura- tion register 400f3347 lpc 0 lpc_config sirq7 interrupt configura- tion register 400f3348 lpc 0 lpc_config sirq8 interrupt configura- tion register 400f3349 lpc 0 lpc_config sirq9 interrupt configura- tion register 400f334a lpc 0 lpc_config sirq10 interrupt configu- ration register 400f334b lpc 0 lpc_config sirq11 interrupt configu- ration register 400f334c lpc 0 lpc_config sirq12 interrupt configu- ration register 400f334d lpc 0 lpc_config sirq13 interrupt configu- ration register 400f334e lpc 0 lpc_config sirq14 interrupt configu- ration register 400f334f lpc 0 lpc_config sirq15 interrupt configu- ration register 400f3360 lpc 0 lpc_config lpc interface bar regis- ter 400f3364 lpc 0 lpc_config em interface 0 bar 400f3368 lpc 0 lpc_config uart 0 bar register 400f3378 lpc 0 lpc_config keyboard controller bar 400f3388 lpc 0 lpc_config acpi ec interface 0 bar 400f338c lpc 0 lpc_config acpi ec interface 1 bar 400f3390 lpc 0 lpc_config acpi pm1 interface bar 400f3394 lpc 0 lpc_config legacy (gatea20) inter- face bar address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
? 2014 - 2015 microchip technology inc. ds00001719d-page 451 MEC1322 400f3398 lpc 0 lpc_config mailbox registers interface bar 400f33c0 lpc 0 lpc_config mailbox registers i/f mem- ory bar 400f33c6 lpc 0 lpc_config acpi ec interface 0 mem- ory bar 400f33cc lpc 0 lpc_config acpi ec interface 1 mem- ory bar 400f33d2 lpc 0 lpc_config em interface 0 memory bar 400fff00 global configuration registers 0 gcr gcr reserved registers 400fff07 global configuration registers 0 gcr logical device number register 400fff08 global configuration registers 0 gcr gcr reserved registers 400fff20 global configuration registers 0 gcr device id register 400fff21 global configuration registers 0 gcr device revision hard wired register 400fff22 global configuration registers 0 gcr gcr reserved 400fff25 global configuration registers 0 gcr gcr reserved 400fff28 global configuration registers 0 gcr gcr build register 400fff2a global configuration registers 0 gcr gcr reserved registers 400fff2c global configuration registers 0 gcr gcr scratch register address (hex) hw block instance name hw block instance no. reg. bank name reg. instance name
MEC1322 ds00001719d-page 452 ? 2014 - 2015 microchip technology inc. appendix a: revision history table a-1: data sheet revision history revision section/figure/entry correction ds00001719d (09-14-15 table 37-1, "absolute maximum ther- mal ratings" , table 37-8, "thermal operating conditions" and ta b l e 3 7 - 10, "vcc1 supply current, i_vcc1" updated tables to add industrial tem- perature information. table 37-11, "vbat supply current, i_vbat (vbat=3.0v)" and table 37- 12, "vbat supply current, i_vbat (vbat=3.3v)" updated tables to remove internal 32khz oscillator information. product identification system added industrial ordering information. ds00001719c (06-15-15) table 27-9, "ec-only register base address table" updated base addresses table 15-3, "interrupt event aggrega- tor routing summary" and ta b l e 1 5 - 22, "bit definitions for girq19 source, enable, and result registers" updated locations for lreset# and vcc_pwrgd bits section 29.15.4, "ps2 status regis- ter" updated description of rec_timeout bit table 37-8, "thermal operating con- ditions" and table 37-9, "thermal packaging characteristics" updated tables. product features added 144 wfbga package table 1-3, "MEC1322 144 wfbga pin configuration" , figure 1-1, "MEC1322 pin name to 144-pin wfbga ball mapping (top)" and figure 1-5, "144-pin wfbga package outline" added 144 wfbga pinout and package drawing. product identification system added 144 wfbga package ordering information section 8.0, "ram and rom" described the distinction between sram optimized for instructions and optimized for data. section 20.7, "pin multiplexing con- trol" updated note on gpio pins that do not exist in the 128 pin package. ds00001719b (06-03-14) throughout document pis page features part number changed from MEC1322/ 24 to MEC1322. ?c0? added to package information sub-bullet added following ?lpc inter- face?: ?supports lpc bus frequencies of 19mhz to 33mhz?. ds00001719a (04-14-14) rev a - document release
? 2014 - 2015 microchip technology inc. ds00001719d-page 453 MEC1322 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
MEC1322 ds00001719d-page 454 ? 2014 - 2015 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. (1) xxx (2) package device device: MEC1322 (1) temperature range: blank = commercial 0 o c to 70 o c i = industrial -40 o c to 85 o c package: nu = 128 pin vtqfp (2) lzy = 132 pin dqfn (2) sz = 144 pin wfbga (2) rom version: c0 = standard rom tape and reel option: blank = tray packaging tr = tape and reel (3) examples: a) MEC1322-nu-c0 = 128-pin vtqfp, commercial b) MEC1322i-lzy-c0 = 132-pin dqfn, industrial c) MEC1322-sz-c0 = 144-pin wfbga, commercial xx rom version - note 3: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. note 2: all package options are rohs compliant. for rohs compliance and environmental information, please visit http://www.micro chip.com/pagehandler/en-us/aboutus/ ehs.html . note 1: these products meet the halogen maximum concentration values per iec61249-2-21. - - [x] (3) tape and reel option xx temperature range
? 2014 - 2015 microchip technology inc. ds00001719d-page 455 MEC1322 information contained in this publication regarding device applic ations and the like is provided only for your convenience and may be super- seded by updates. it is your responsibility to ensure that your application meets with your spec ifications. microchip makes no rep- resentations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from th is information and its use. use of micro- chip devices in life support and/or safety applications is entirel y at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or ex penses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashf lex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tradem arks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kl eernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, pi cdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, va risense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademark of microchi p technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014 - 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632777645 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature ma y be a violation of the digita l millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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